1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/firmware/qcom/qcom_scm.h> 14 #include <linux/pm_domain.h> 15 #include <linux/soc/qcom/llcc-qcom.h> 16 17 #define GPU_PAS_ID 13 18 19 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 20 { 21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 22 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 23 24 /* Check that the GMU is idle */ 25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) 26 return false; 27 28 /* Check tha the CX master is idle */ 29 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 30 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 31 return false; 32 33 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 34 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 35 } 36 37 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 38 { 39 /* wait for CP to drain ringbuffer: */ 40 if (!adreno_idle(gpu, ring)) 41 return false; 42 43 if (spin_until(_a6xx_check_idle(gpu))) { 44 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 45 gpu->name, __builtin_return_address(0), 46 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 47 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 48 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 49 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 50 return false; 51 } 52 53 return true; 54 } 55 56 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 57 { 58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 59 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 60 61 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 62 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 63 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 64 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 65 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 66 } 67 } 68 69 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 70 { 71 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 72 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 73 uint32_t wptr; 74 unsigned long flags; 75 76 update_shadow_rptr(gpu, ring); 77 78 spin_lock_irqsave(&ring->preempt_lock, flags); 79 80 /* Copy the shadow to the actual register */ 81 ring->cur = ring->next; 82 83 /* Make sure to wrap wptr if we need to */ 84 wptr = get_wptr(ring); 85 86 /* Update HW if this is the current ring and we are not in preempt*/ 87 if (!a6xx_in_preempt(a6xx_gpu)) { 88 if (a6xx_gpu->cur_ring == ring) 89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 90 else 91 ring->restore_wptr = true; 92 } else { 93 ring->restore_wptr = true; 94 } 95 96 spin_unlock_irqrestore(&ring->preempt_lock, flags); 97 } 98 99 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 100 u64 iova) 101 { 102 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 103 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 104 CP_REG_TO_MEM_0_CNT(2) | 105 CP_REG_TO_MEM_0_64B); 106 OUT_RING(ring, lower_32_bits(iova)); 107 OUT_RING(ring, upper_32_bits(iova)); 108 } 109 110 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 111 struct msm_ringbuffer *ring, struct msm_file_private *ctx) 112 { 113 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; 114 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 115 phys_addr_t ttbr; 116 u32 asid; 117 u64 memptr = rbmemptr(ring, ttbr0); 118 119 if (ctx->seqno == ring->cur_ctx_seqno) 120 return; 121 122 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 123 return; 124 125 if (!sysprof) { 126 if (!adreno_is_a7xx(adreno_gpu)) { 127 /* Turn off protected mode to write to special registers */ 128 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 129 OUT_RING(ring, 0); 130 } 131 132 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); 133 OUT_RING(ring, 1); 134 } 135 136 /* Execute the table update */ 137 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 138 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 139 140 OUT_RING(ring, 141 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 142 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 143 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 144 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 145 146 /* 147 * Write the new TTBR0 to the memstore. This is good for debugging. 148 * Needed for preemption 149 */ 150 OUT_PKT7(ring, CP_MEM_WRITE, 5); 151 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 152 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 153 OUT_RING(ring, lower_32_bits(ttbr)); 154 OUT_RING(ring, upper_32_bits(ttbr)); 155 OUT_RING(ring, ctx->seqno); 156 157 /* 158 * Sync both threads after switching pagetables and enable BR only 159 * to make sure BV doesn't race ahead while BR is still switching 160 * pagetables. 161 */ 162 if (adreno_is_a7xx(&a6xx_gpu->base)) { 163 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 164 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 165 } 166 167 /* 168 * And finally, trigger a uche flush to be sure there isn't anything 169 * lingering in that part of the GPU 170 */ 171 172 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 173 OUT_RING(ring, CACHE_INVALIDATE); 174 175 if (!sysprof) { 176 /* 177 * Wait for SRAM clear after the pgtable update, so the 178 * two can happen in parallel: 179 */ 180 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 181 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 182 OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 183 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); 184 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); 185 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 186 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 187 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); 188 189 if (!adreno_is_a7xx(adreno_gpu)) { 190 /* Re-enable protected mode: */ 191 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 192 OUT_RING(ring, 1); 193 } 194 } 195 } 196 197 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 198 { 199 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 200 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 201 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 202 struct msm_ringbuffer *ring = submit->ring; 203 unsigned int i, ibs = 0; 204 205 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 206 207 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 208 rbmemptr_stats(ring, index, cpcycles_start)); 209 210 /* 211 * For PM4 the GMU register offsets are calculated from the base of the 212 * GPU registers so we need to add 0x1a800 to the register value on A630 213 * to get the right value from PM4. 214 */ 215 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 216 rbmemptr_stats(ring, index, alwayson_start)); 217 218 /* Invalidate CCU depth and color */ 219 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 220 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 221 222 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 223 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 224 225 /* Submit the commands */ 226 for (i = 0; i < submit->nr_cmds; i++) { 227 switch (submit->cmd[i].type) { 228 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 229 break; 230 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 231 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 232 break; 233 fallthrough; 234 case MSM_SUBMIT_CMD_BUF: 235 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 236 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 237 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 238 OUT_RING(ring, submit->cmd[i].size); 239 ibs++; 240 break; 241 } 242 243 /* 244 * Periodically update shadow-wptr if needed, so that we 245 * can see partial progress of submits with large # of 246 * cmds.. otherwise we could needlessly stall waiting for 247 * ringbuffer state, simply due to looking at a shadow 248 * rptr value that has not been updated 249 */ 250 if ((ibs % 32) == 0) 251 update_shadow_rptr(gpu, ring); 252 } 253 254 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 255 rbmemptr_stats(ring, index, cpcycles_end)); 256 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 257 rbmemptr_stats(ring, index, alwayson_end)); 258 259 /* Write the fence to the scratch register */ 260 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 261 OUT_RING(ring, submit->seqno); 262 263 /* 264 * Execute a CACHE_FLUSH_TS event. This will ensure that the 265 * timestamp is written to the memory and then triggers the interrupt 266 */ 267 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 268 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 269 CP_EVENT_WRITE_0_IRQ); 270 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 271 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 272 OUT_RING(ring, submit->seqno); 273 274 trace_msm_gpu_submit_flush(submit, 275 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 276 277 a6xx_flush(gpu, ring); 278 } 279 280 static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, 281 struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) 282 { 283 OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12); 284 285 OUT_RING(ring, SMMU_INFO); 286 /* don't save SMMU, we write the record from the kernel instead */ 287 OUT_RING(ring, 0); 288 OUT_RING(ring, 0); 289 290 /* privileged and non secure buffer save */ 291 OUT_RING(ring, NON_SECURE_SAVE_ADDR); 292 OUT_RING(ring, lower_32_bits( 293 a6xx_gpu->preempt_iova[ring->id])); 294 OUT_RING(ring, upper_32_bits( 295 a6xx_gpu->preempt_iova[ring->id])); 296 297 /* user context buffer save, seems to be unnused by fw */ 298 OUT_RING(ring, NON_PRIV_SAVE_ADDR); 299 OUT_RING(ring, 0); 300 OUT_RING(ring, 0); 301 302 OUT_RING(ring, COUNTER); 303 /* seems OK to set to 0 to disable it */ 304 OUT_RING(ring, 0); 305 OUT_RING(ring, 0); 306 } 307 308 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 309 { 310 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 311 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 312 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 313 struct msm_ringbuffer *ring = submit->ring; 314 unsigned int i, ibs = 0; 315 316 /* 317 * Toggle concurrent binning for pagetable switch and set the thread to 318 * BR since only it can execute the pagetable switch packets. 319 */ 320 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 321 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 322 323 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 324 325 /* 326 * If preemption is enabled, then set the pseudo register for the save 327 * sequence 328 */ 329 if (gpu->nr_rings > 1) 330 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); 331 332 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 333 rbmemptr_stats(ring, index, cpcycles_start)); 334 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 335 rbmemptr_stats(ring, index, alwayson_start)); 336 337 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 338 OUT_RING(ring, CP_SET_THREAD_BOTH); 339 340 OUT_PKT7(ring, CP_SET_MARKER, 1); 341 OUT_RING(ring, 0x101); /* IFPC disable */ 342 343 OUT_PKT7(ring, CP_SET_MARKER, 1); 344 OUT_RING(ring, 0x00d); /* IB1LIST start */ 345 346 /* Submit the commands */ 347 for (i = 0; i < submit->nr_cmds; i++) { 348 switch (submit->cmd[i].type) { 349 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 350 break; 351 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 352 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 353 break; 354 fallthrough; 355 case MSM_SUBMIT_CMD_BUF: 356 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 357 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 358 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 359 OUT_RING(ring, submit->cmd[i].size); 360 ibs++; 361 break; 362 } 363 364 /* 365 * Periodically update shadow-wptr if needed, so that we 366 * can see partial progress of submits with large # of 367 * cmds.. otherwise we could needlessly stall waiting for 368 * ringbuffer state, simply due to looking at a shadow 369 * rptr value that has not been updated 370 */ 371 if ((ibs % 32) == 0) 372 update_shadow_rptr(gpu, ring); 373 } 374 375 OUT_PKT7(ring, CP_SET_MARKER, 1); 376 OUT_RING(ring, 0x00e); /* IB1LIST end */ 377 378 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), 379 rbmemptr_stats(ring, index, cpcycles_end)); 380 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 381 rbmemptr_stats(ring, index, alwayson_end)); 382 383 /* Write the fence to the scratch register */ 384 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 385 OUT_RING(ring, submit->seqno); 386 387 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 388 OUT_RING(ring, CP_SET_THREAD_BR); 389 390 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 391 OUT_RING(ring, CCU_INVALIDATE_DEPTH); 392 393 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 394 OUT_RING(ring, CCU_INVALIDATE_COLOR); 395 396 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 397 OUT_RING(ring, CP_SET_THREAD_BV); 398 399 /* 400 * Make sure the timestamp is committed once BV pipe is 401 * completely done with this submission. 402 */ 403 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 404 OUT_RING(ring, CACHE_CLEAN | BIT(27)); 405 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 406 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 407 OUT_RING(ring, submit->seqno); 408 409 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 410 OUT_RING(ring, CP_SET_THREAD_BR); 411 412 /* 413 * This makes sure that BR doesn't race ahead and commit 414 * timestamp to memstore while BV is still processing 415 * this submission. 416 */ 417 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 418 OUT_RING(ring, 0); 419 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 420 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 421 OUT_RING(ring, submit->seqno); 422 423 a6xx_gpu->last_seqno[ring->id] = submit->seqno; 424 425 /* write the ringbuffer timestamp */ 426 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 427 OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); 428 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 429 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 430 OUT_RING(ring, submit->seqno); 431 432 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 433 OUT_RING(ring, CP_SET_THREAD_BOTH); 434 435 OUT_PKT7(ring, CP_SET_MARKER, 1); 436 OUT_RING(ring, 0x100); /* IFPC enable */ 437 438 /* If preemption is enabled */ 439 if (gpu->nr_rings > 1) { 440 /* Yield the floor on command completion */ 441 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 442 443 /* 444 * If dword[2:1] are non zero, they specify an address for 445 * the CP to write the value of dword[3] to on preemption 446 * complete. Write 0 to skip the write 447 */ 448 OUT_RING(ring, 0x00); 449 OUT_RING(ring, 0x00); 450 /* Data value - not used if the address above is 0 */ 451 OUT_RING(ring, 0x01); 452 /* generate interrupt on preemption completion */ 453 OUT_RING(ring, 0x00); 454 } 455 456 457 trace_msm_gpu_submit_flush(submit, 458 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 459 460 a6xx_flush(gpu, ring); 461 462 /* Check to see if we need to start preemption */ 463 a6xx_preempt_trigger(gpu); 464 } 465 466 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 467 { 468 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 469 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 470 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 471 const struct adreno_reglist *reg; 472 unsigned int i; 473 u32 cgc_delay, cgc_hyst; 474 u32 val, clock_cntl_on; 475 476 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) 477 return; 478 479 if (adreno_is_a630(adreno_gpu)) 480 clock_cntl_on = 0x8aa8aa02; 481 else if (adreno_is_a610(adreno_gpu)) 482 clock_cntl_on = 0xaaa8aa82; 483 else if (adreno_is_a702(adreno_gpu)) 484 clock_cntl_on = 0xaaaaaa82; 485 else 486 clock_cntl_on = 0x8aa8aa82; 487 488 cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; 489 cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; 490 491 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 492 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); 493 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 494 state ? cgc_delay : 0); 495 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 496 state ? cgc_hyst : 0); 497 498 if (!adreno_gpu->info->a6xx->hwcg) { 499 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); 500 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); 501 502 if (state) { 503 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); 504 505 if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, 506 val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { 507 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); 508 return; 509 } 510 511 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); 512 } 513 514 return; 515 } 516 517 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 518 519 /* Don't re-program the registers if they are already correct */ 520 if ((!state && !val) || (state && (val == clock_cntl_on))) 521 return; 522 523 /* Disable SP clock before programming HWCG registers */ 524 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 525 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 526 527 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) 528 gpu_write(gpu, reg->offset, state ? reg->value : 0); 529 530 /* Enable SP clock */ 531 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 532 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 533 534 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 535 } 536 537 static void a6xx_set_cp_protect(struct msm_gpu *gpu) 538 { 539 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 540 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; 541 unsigned i; 542 543 /* 544 * Enable access protection to privileged registers, fault on an access 545 * protect violation and select the last span to protect from the start 546 * address all the way to the end of the register address space 547 */ 548 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 549 A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | 550 A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | 551 A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); 552 553 for (i = 0; i < protect->count - 1; i++) { 554 /* Intentionally skip writing to some registers */ 555 if (protect->regs[i]) 556 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); 557 } 558 /* last CP_PROTECT to have "infinite" length on the last entry */ 559 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); 560 } 561 562 static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 563 { 564 gpu->ubwc_config.rgb565_predicator = 0; 565 gpu->ubwc_config.uavflagprd_inv = 0; 566 gpu->ubwc_config.min_acc_len = 0; 567 gpu->ubwc_config.ubwc_swizzle = 0x6; 568 gpu->ubwc_config.macrotile_mode = 0; 569 gpu->ubwc_config.highest_bank_bit = 15; 570 571 if (adreno_is_a610(gpu)) { 572 gpu->ubwc_config.highest_bank_bit = 13; 573 gpu->ubwc_config.min_acc_len = 1; 574 gpu->ubwc_config.ubwc_swizzle = 0x7; 575 } 576 577 if (adreno_is_a618(gpu)) 578 gpu->ubwc_config.highest_bank_bit = 14; 579 580 if (adreno_is_a619(gpu)) 581 /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ 582 gpu->ubwc_config.highest_bank_bit = 13; 583 584 if (adreno_is_a619_holi(gpu)) 585 gpu->ubwc_config.highest_bank_bit = 13; 586 587 if (adreno_is_a621(gpu)) { 588 gpu->ubwc_config.highest_bank_bit = 13; 589 gpu->ubwc_config.amsbc = 1; 590 gpu->ubwc_config.uavflagprd_inv = 2; 591 } 592 593 if (adreno_is_a640_family(gpu)) 594 gpu->ubwc_config.amsbc = 1; 595 596 if (adreno_is_a680(gpu)) 597 gpu->ubwc_config.macrotile_mode = 1; 598 599 if (adreno_is_a650(gpu) || 600 adreno_is_a660(gpu) || 601 adreno_is_a690(gpu) || 602 adreno_is_a730(gpu) || 603 adreno_is_a740_family(gpu)) { 604 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 605 gpu->ubwc_config.highest_bank_bit = 16; 606 gpu->ubwc_config.amsbc = 1; 607 gpu->ubwc_config.rgb565_predicator = 1; 608 gpu->ubwc_config.uavflagprd_inv = 2; 609 gpu->ubwc_config.macrotile_mode = 1; 610 } 611 612 if (adreno_is_7c3(gpu)) { 613 gpu->ubwc_config.highest_bank_bit = 14; 614 gpu->ubwc_config.amsbc = 1; 615 gpu->ubwc_config.rgb565_predicator = 1; 616 gpu->ubwc_config.uavflagprd_inv = 2; 617 gpu->ubwc_config.macrotile_mode = 1; 618 } 619 620 if (adreno_is_a702(gpu)) { 621 gpu->ubwc_config.highest_bank_bit = 14; 622 gpu->ubwc_config.min_acc_len = 1; 623 } 624 } 625 626 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 627 { 628 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 629 /* 630 * We subtract 13 from the highest bank bit (13 is the minimum value 631 * allowed by hw) and write the lowest two bits of the remaining value 632 * as hbb_lo and the one above it as hbb_hi to the hardware. 633 */ 634 BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13); 635 u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13; 636 u32 hbb_hi = hbb >> 2; 637 u32 hbb_lo = hbb & 3; 638 u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1; 639 u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2); 640 641 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 642 level2_swizzling_dis << 12 | 643 adreno_gpu->ubwc_config.rgb565_predicator << 11 | 644 hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 | 645 adreno_gpu->ubwc_config.min_acc_len << 3 | 646 hbb_lo << 1 | ubwc_mode); 647 648 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 649 level2_swizzling_dis << 6 | hbb_hi << 4 | 650 adreno_gpu->ubwc_config.min_acc_len << 3 | 651 hbb_lo << 1 | ubwc_mode); 652 653 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 654 level2_swizzling_dis << 12 | hbb_hi << 10 | 655 adreno_gpu->ubwc_config.uavflagprd_inv << 4 | 656 adreno_gpu->ubwc_config.min_acc_len << 3 | 657 hbb_lo << 1 | ubwc_mode); 658 659 if (adreno_is_a7xx(adreno_gpu)) 660 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 661 FIELD_PREP(GENMASK(8, 5), hbb_lo)); 662 663 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 664 adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); 665 666 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, 667 adreno_gpu->ubwc_config.macrotile_mode); 668 } 669 670 static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) 671 { 672 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 673 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 674 const struct adreno_reglist_list *reglist; 675 void *ptr = a6xx_gpu->pwrup_reglist_ptr; 676 struct cpu_gpu_lock *lock = ptr; 677 u32 *dest = (u32 *)&lock->regs[0]; 678 int i; 679 680 reglist = adreno_gpu->info->a6xx->pwrup_reglist; 681 682 lock->gpu_req = lock->cpu_req = lock->turn = 0; 683 lock->ifpc_list_len = 0; 684 lock->preemption_list_len = reglist->count; 685 686 /* 687 * For each entry in each of the lists, write the offset and the current 688 * register value into the GPU buffer 689 */ 690 for (i = 0; i < reglist->count; i++) { 691 *dest++ = reglist->regs[i]; 692 *dest++ = gpu_read(gpu, reglist->regs[i]); 693 } 694 695 /* 696 * The overall register list is composed of 697 * 1. Static IFPC-only registers 698 * 2. Static IFPC + preemption registers 699 * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) 700 * 701 * The first two lists are static. Size of these lists are stored as 702 * number of pairs in ifpc_list_len and preemption_list_len 703 * respectively. With concurrent binning, Some of the perfcounter 704 * registers being virtualized, CP needs to know the pipe id to program 705 * the aperture inorder to restore the same. Thus, third list is a 706 * dynamic list with triplets as 707 * (<aperture, shifted 12 bits> <address> <data>), and the length is 708 * stored as number for triplets in dynamic_list_len. 709 */ 710 lock->dynamic_list_len = 0; 711 } 712 713 static int a7xx_preempt_start(struct msm_gpu *gpu) 714 { 715 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 716 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 717 struct msm_ringbuffer *ring = gpu->rb[0]; 718 719 if (gpu->nr_rings <= 1) 720 return 0; 721 722 /* Turn CP protection off */ 723 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 724 OUT_RING(ring, 0); 725 726 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); 727 728 /* Yield the floor on command completion */ 729 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 730 OUT_RING(ring, 0x00); 731 OUT_RING(ring, 0x00); 732 OUT_RING(ring, 0x00); 733 /* Generate interrupt on preemption completion */ 734 OUT_RING(ring, 0x00); 735 736 a6xx_flush(gpu, ring); 737 738 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 739 } 740 741 static int a6xx_cp_init(struct msm_gpu *gpu) 742 { 743 struct msm_ringbuffer *ring = gpu->rb[0]; 744 745 OUT_PKT7(ring, CP_ME_INIT, 8); 746 747 OUT_RING(ring, 0x0000002f); 748 749 /* Enable multiple hardware contexts */ 750 OUT_RING(ring, 0x00000003); 751 752 /* Enable error detection */ 753 OUT_RING(ring, 0x20000000); 754 755 /* Don't enable header dump */ 756 OUT_RING(ring, 0x00000000); 757 OUT_RING(ring, 0x00000000); 758 759 /* No workarounds enabled */ 760 OUT_RING(ring, 0x00000000); 761 762 /* Pad rest of the cmds with 0's */ 763 OUT_RING(ring, 0x00000000); 764 OUT_RING(ring, 0x00000000); 765 766 a6xx_flush(gpu, ring); 767 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 768 } 769 770 static int a7xx_cp_init(struct msm_gpu *gpu) 771 { 772 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 773 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 774 struct msm_ringbuffer *ring = gpu->rb[0]; 775 u32 mask; 776 777 /* Disable concurrent binning before sending CP init */ 778 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 779 OUT_RING(ring, BIT(27)); 780 781 OUT_PKT7(ring, CP_ME_INIT, 7); 782 783 /* Use multiple HW contexts */ 784 mask = BIT(0); 785 786 /* Enable error detection */ 787 mask |= BIT(1); 788 789 /* Set default reset state */ 790 mask |= BIT(3); 791 792 /* Disable save/restore of performance counters across preemption */ 793 mask |= BIT(6); 794 795 /* Enable the register init list with the spinlock */ 796 mask |= BIT(8); 797 798 OUT_RING(ring, mask); 799 800 /* Enable multiple hardware contexts */ 801 OUT_RING(ring, 0x00000003); 802 803 /* Enable error detection */ 804 OUT_RING(ring, 0x20000000); 805 806 /* Operation mode mask */ 807 OUT_RING(ring, 0x00000002); 808 809 /* *Don't* send a power up reg list for concurrent binning (TODO) */ 810 /* Lo address */ 811 OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); 812 /* Hi address */ 813 OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); 814 /* BIT(31) set => read the regs from the list */ 815 OUT_RING(ring, BIT(31)); 816 817 a6xx_flush(gpu, ring); 818 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 819 } 820 821 /* 822 * Check that the microcode version is new enough to include several key 823 * security fixes. Return true if the ucode is safe. 824 */ 825 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 826 struct drm_gem_object *obj) 827 { 828 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 829 struct msm_gpu *gpu = &adreno_gpu->base; 830 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; 831 u32 *buf = msm_gem_get_vaddr(obj); 832 bool ret = false; 833 834 if (IS_ERR(buf)) 835 return false; 836 837 /* A7xx is safe! */ 838 if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu)) 839 return true; 840 841 /* 842 * Targets up to a640 (a618, a630 and a640) need to check for a 843 * microcode version that is patched to support the whereami opcode or 844 * one that is new enough to include it by default. 845 * 846 * a650 tier targets don't need whereami but still need to be 847 * equal to or newer than 0.95 for other security fixes 848 * 849 * a660 targets have all the critical security fixes from the start 850 */ 851 if (!strcmp(sqe_name, "a630_sqe.fw")) { 852 /* 853 * If the lowest nibble is 0xa that is an indication that this 854 * microcode has been patched. The actual version is in dword 855 * [3] but we only care about the patchlevel which is the lowest 856 * nibble of dword [3] 857 * 858 * Otherwise check that the firmware is greater than or equal 859 * to 1.90 which was the first version that had this fix built 860 * in 861 */ 862 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 863 (buf[0] & 0xfff) >= 0x190) { 864 a6xx_gpu->has_whereami = true; 865 ret = true; 866 goto out; 867 } 868 869 DRM_DEV_ERROR(&gpu->pdev->dev, 870 "a630 SQE ucode is too old. Have version %x need at least %x\n", 871 buf[0] & 0xfff, 0x190); 872 } else if (!strcmp(sqe_name, "a650_sqe.fw")) { 873 if ((buf[0] & 0xfff) >= 0x095) { 874 ret = true; 875 goto out; 876 } 877 878 DRM_DEV_ERROR(&gpu->pdev->dev, 879 "a650 SQE ucode is too old. Have version %x need at least %x\n", 880 buf[0] & 0xfff, 0x095); 881 } else if (!strcmp(sqe_name, "a660_sqe.fw")) { 882 ret = true; 883 } else { 884 DRM_DEV_ERROR(&gpu->pdev->dev, 885 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); 886 } 887 out: 888 msm_gem_put_vaddr(obj); 889 return ret; 890 } 891 892 static int a6xx_ucode_load(struct msm_gpu *gpu) 893 { 894 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 895 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 896 897 if (!a6xx_gpu->sqe_bo) { 898 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 899 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 900 901 if (IS_ERR(a6xx_gpu->sqe_bo)) { 902 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 903 904 a6xx_gpu->sqe_bo = NULL; 905 DRM_DEV_ERROR(&gpu->pdev->dev, 906 "Could not allocate SQE ucode: %d\n", ret); 907 908 return ret; 909 } 910 911 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 912 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 913 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 914 drm_gem_object_put(a6xx_gpu->sqe_bo); 915 916 a6xx_gpu->sqe_bo = NULL; 917 return -EPERM; 918 } 919 } 920 921 /* 922 * Expanded APRIV and targets that support WHERE_AM_I both need a 923 * privileged buffer to store the RPTR shadow 924 */ 925 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && 926 !a6xx_gpu->shadow_bo) { 927 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, 928 sizeof(u32) * gpu->nr_rings, 929 MSM_BO_WC | MSM_BO_MAP_PRIV, 930 gpu->aspace, &a6xx_gpu->shadow_bo, 931 &a6xx_gpu->shadow_iova); 932 933 if (IS_ERR(a6xx_gpu->shadow)) 934 return PTR_ERR(a6xx_gpu->shadow); 935 936 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); 937 } 938 939 a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE, 940 MSM_BO_WC | MSM_BO_MAP_PRIV, 941 gpu->aspace, &a6xx_gpu->pwrup_reglist_bo, 942 &a6xx_gpu->pwrup_reglist_iova); 943 944 if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) 945 return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); 946 947 msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); 948 949 return 0; 950 } 951 952 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 953 { 954 static bool loaded; 955 int ret; 956 957 if (loaded) 958 return 0; 959 960 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 961 962 loaded = !ret; 963 return ret; 964 } 965 966 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 967 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 968 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 969 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 970 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 971 A6XX_RBBM_INT_0_MASK_CP_RB | \ 972 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 973 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 974 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 975 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 976 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 977 978 #define A7XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 979 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 980 A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \ 981 A6XX_RBBM_INT_0_MASK_CP_SW | \ 982 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 983 A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \ 984 A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \ 985 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 986 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 987 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 988 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 989 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ 990 A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ 991 A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 992 993 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ 994 A6XX_CP_APRIV_CNTL_RBFETCH | \ 995 A6XX_CP_APRIV_CNTL_RBPRIVLEVEL | \ 996 A6XX_CP_APRIV_CNTL_RBRPWB) 997 998 #define A7XX_BR_APRIVMASK (A7XX_APRIV_MASK | \ 999 A6XX_CP_APRIV_CNTL_CDREAD | \ 1000 A6XX_CP_APRIV_CNTL_CDWRITE) 1001 1002 static int hw_init(struct msm_gpu *gpu) 1003 { 1004 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1005 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1006 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1007 u64 gmem_range_min; 1008 unsigned int i; 1009 int ret; 1010 1011 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1012 /* Make sure the GMU keeps the GPU on while we set it up */ 1013 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1014 if (ret) 1015 return ret; 1016 } 1017 1018 /* Clear GBIF halt in case GX domain was not collapsed */ 1019 if (adreno_is_a619_holi(adreno_gpu)) { 1020 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1021 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1022 1023 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); 1024 gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL); 1025 } else if (a6xx_has_gbif(adreno_gpu)) { 1026 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1027 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1028 1029 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); 1030 gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT); 1031 } 1032 1033 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 1034 1035 if (adreno_is_a619_holi(adreno_gpu)) 1036 a6xx_sptprac_enable(gmu); 1037 1038 /* 1039 * Disable the trusted memory range - we don't actually supported secure 1040 * memory rendering at this point in time and we don't want to block off 1041 * part of the virtual memory space. 1042 */ 1043 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); 1044 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 1045 1046 if (!adreno_is_a7xx(adreno_gpu)) { 1047 /* Turn on 64 bit addressing for all blocks */ 1048 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 1049 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 1050 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 1051 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 1052 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 1053 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 1054 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 1055 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 1056 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 1057 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 1058 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 1059 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 1060 } 1061 1062 /* enable hardware clockgating */ 1063 a6xx_set_hwcg(gpu, true); 1064 1065 /* VBIF/GBIF start*/ 1066 if (adreno_is_a610_family(adreno_gpu) || 1067 adreno_is_a640_family(adreno_gpu) || 1068 adreno_is_a650_family(adreno_gpu) || 1069 adreno_is_a7xx(adreno_gpu)) { 1070 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 1071 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 1072 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 1073 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 1074 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 1075 adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); 1076 } else { 1077 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 1078 } 1079 1080 if (adreno_is_a630(adreno_gpu)) 1081 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 1082 1083 if (adreno_is_a7xx(adreno_gpu)) 1084 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0); 1085 1086 /* Make all blocks contribute to the GPU BUSY perf counter */ 1087 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 1088 1089 /* Disable L2 bypass in the UCHE */ 1090 if (adreno_is_a7xx(adreno_gpu)) { 1091 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); 1092 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); 1093 } else { 1094 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, 0x0001ffffffffffc0llu); 1095 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); 1096 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); 1097 } 1098 1099 if (!(adreno_is_a650_family(adreno_gpu) || 1100 adreno_is_a702(adreno_gpu) || 1101 adreno_is_a730(adreno_gpu))) { 1102 gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M; 1103 1104 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 1105 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min); 1106 1107 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, 1108 gmem_range_min + adreno_gpu->info->gmem - 1); 1109 } 1110 1111 if (adreno_is_a7xx(adreno_gpu)) 1112 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23)); 1113 else { 1114 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 1115 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 1116 } 1117 1118 if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { 1119 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 1120 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1121 } else if (adreno_is_a610_family(adreno_gpu)) { 1122 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); 1123 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); 1124 } else if (!adreno_is_a7xx(adreno_gpu)) { 1125 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 1126 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1127 } 1128 1129 if (adreno_is_a660_family(adreno_gpu)) 1130 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 1131 1132 /* Setting the mem pool size */ 1133 if (adreno_is_a610(adreno_gpu)) { 1134 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); 1135 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); 1136 } else if (adreno_is_a702(adreno_gpu)) { 1137 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); 1138 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); 1139 } else if (!adreno_is_a7xx(adreno_gpu)) 1140 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 1141 1142 1143 /* Set the default primFifo threshold values */ 1144 if (adreno_gpu->info->a6xx->prim_fifo_threshold) 1145 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 1146 adreno_gpu->info->a6xx->prim_fifo_threshold); 1147 1148 /* Set the AHB default slave response to "ERROR" */ 1149 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 1150 1151 /* Turn on performance counters */ 1152 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 1153 1154 if (adreno_is_a7xx(adreno_gpu)) { 1155 /* Turn on the IFPC counter (countable 4 on XOCLK4) */ 1156 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, 1157 FIELD_PREP(GENMASK(7, 0), 0x4)); 1158 } 1159 1160 /* Select CP0 to always count cycles */ 1161 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); 1162 1163 a6xx_set_ubwc_config(gpu); 1164 1165 /* Enable fault detection */ 1166 if (adreno_is_a730(adreno_gpu) || 1167 adreno_is_a740_family(adreno_gpu)) 1168 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); 1169 else if (adreno_is_a690(adreno_gpu)) 1170 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); 1171 else if (adreno_is_a619(adreno_gpu)) 1172 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); 1173 else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 1174 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); 1175 else 1176 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); 1177 1178 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); 1179 1180 /* Set weights for bicubic filtering */ 1181 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { 1182 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 1183 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1184 0x3fe05ff4); 1185 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1186 0x3fa0ebee); 1187 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1188 0x3f5193ed); 1189 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1190 0x3f0243f0); 1191 } 1192 1193 /* Set up the CX GMU counter 0 to count busy ticks */ 1194 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 1195 1196 /* Enable the power counter */ 1197 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); 1198 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 1199 1200 /* Protect registers from the CP */ 1201 a6xx_set_cp_protect(gpu); 1202 1203 if (adreno_is_a660_family(adreno_gpu)) { 1204 if (adreno_is_a690(adreno_gpu)) 1205 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801); 1206 else 1207 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); 1208 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); 1209 } else if (adreno_is_a702(adreno_gpu)) { 1210 /* Something to do with the HLSQ cluster */ 1211 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); 1212 } 1213 1214 if (adreno_is_a690(adreno_gpu)) 1215 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); 1216 /* Set dualQ + disable afull for A660 GPU */ 1217 else if (adreno_is_a660(adreno_gpu)) 1218 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); 1219 else if (adreno_is_a7xx(adreno_gpu)) 1220 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 1221 FIELD_PREP(GENMASK(19, 16), 6) | 1222 FIELD_PREP(GENMASK(15, 12), 6) | 1223 FIELD_PREP(GENMASK(11, 8), 9) | 1224 BIT(3) | BIT(2) | 1225 FIELD_PREP(GENMASK(1, 0), 2)); 1226 1227 /* Enable expanded apriv for targets that support it */ 1228 if (gpu->hw_apriv) { 1229 if (adreno_is_a7xx(adreno_gpu)) { 1230 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1231 A7XX_BR_APRIVMASK); 1232 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL, 1233 A7XX_APRIV_MASK); 1234 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL, 1235 A7XX_APRIV_MASK); 1236 } else 1237 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1238 BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); 1239 } 1240 1241 if (adreno_is_a750(adreno_gpu)) { 1242 /* Disable ubwc merged UFC request feature */ 1243 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); 1244 1245 /* Enable TP flaghint and other performance settings */ 1246 gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); 1247 } else if (adreno_is_a7xx(adreno_gpu)) { 1248 /* Disable non-ubwc read reqs from passing write reqs */ 1249 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); 1250 } 1251 1252 /* Enable interrupts */ 1253 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 1254 adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK); 1255 1256 ret = adreno_hw_init(gpu); 1257 if (ret) 1258 goto out; 1259 1260 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 1261 1262 /* Set the ringbuffer address */ 1263 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 1264 1265 /* Targets that support extended APRIV can use the RPTR shadow from 1266 * hardware but all the other ones need to disable the feature. Targets 1267 * that support the WHERE_AM_I opcode can use that instead 1268 */ 1269 if (adreno_gpu->base.hw_apriv) 1270 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 1271 else 1272 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 1273 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 1274 1275 /* Configure the RPTR shadow if needed: */ 1276 if (a6xx_gpu->shadow_bo) { 1277 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, 1278 shadowptr(a6xx_gpu, gpu->rb[0])); 1279 for (unsigned int i = 0; i < gpu->nr_rings; i++) 1280 a6xx_gpu->shadow[i] = 0; 1281 } 1282 1283 /* ..which means "always" on A7xx, also for BV shadow */ 1284 if (adreno_is_a7xx(adreno_gpu)) { 1285 gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, 1286 rbmemptr(gpu->rb[0], bv_rptr)); 1287 } 1288 1289 a6xx_preempt_hw_init(gpu); 1290 1291 /* Always come up on rb 0 */ 1292 a6xx_gpu->cur_ring = gpu->rb[0]; 1293 1294 for (i = 0; i < gpu->nr_rings; i++) 1295 gpu->rb[i]->cur_ctx_seqno = 0; 1296 1297 /* Enable the SQE_to start the CP engine */ 1298 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 1299 1300 if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) { 1301 a7xx_patch_pwrup_reglist(gpu); 1302 a6xx_gpu->pwrup_reglist_emitted = true; 1303 } 1304 1305 ret = adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu); 1306 if (ret) 1307 goto out; 1308 1309 /* 1310 * Try to load a zap shader into the secure world. If successful 1311 * we can use the CP to switch out of secure mode. If not then we 1312 * have no resource but to try to switch ourselves out manually. If we 1313 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 1314 * be blocked and a permissions violation will soon follow. 1315 */ 1316 ret = a6xx_zap_shader_init(gpu); 1317 if (!ret) { 1318 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 1319 OUT_RING(gpu->rb[0], 0x00000000); 1320 1321 a6xx_flush(gpu, gpu->rb[0]); 1322 if (!a6xx_idle(gpu, gpu->rb[0])) 1323 return -EINVAL; 1324 } else if (ret == -ENODEV) { 1325 /* 1326 * This device does not use zap shader (but print a warning 1327 * just in case someone got their dt wrong.. hopefully they 1328 * have a debug UART to realize the error of their ways... 1329 * if you mess this up you are about to crash horribly) 1330 */ 1331 dev_warn_once(gpu->dev->dev, 1332 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 1333 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 1334 ret = 0; 1335 } else { 1336 return ret; 1337 } 1338 1339 out: 1340 if (adreno_has_gmu_wrapper(adreno_gpu)) 1341 return ret; 1342 1343 /* Last step - yield the ringbuffer */ 1344 a7xx_preempt_start(gpu); 1345 1346 /* 1347 * Tell the GMU that we are done touching the GPU and it can start power 1348 * management 1349 */ 1350 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1351 1352 if (a6xx_gpu->gmu.legacy) { 1353 /* Take the GMU out of its special boot mode */ 1354 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1355 } 1356 1357 return ret; 1358 } 1359 1360 static int a6xx_hw_init(struct msm_gpu *gpu) 1361 { 1362 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1363 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1364 int ret; 1365 1366 mutex_lock(&a6xx_gpu->gmu.lock); 1367 ret = hw_init(gpu); 1368 mutex_unlock(&a6xx_gpu->gmu.lock); 1369 1370 return ret; 1371 } 1372 1373 static void a6xx_dump(struct msm_gpu *gpu) 1374 { 1375 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 1376 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 1377 adreno_dump(gpu); 1378 } 1379 1380 static void a6xx_recover(struct msm_gpu *gpu) 1381 { 1382 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1383 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1384 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1385 int i, active_submits; 1386 1387 adreno_dump_info(gpu); 1388 1389 for (i = 0; i < 8; i++) 1390 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1391 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1392 1393 if (hang_debug) 1394 a6xx_dump(gpu); 1395 1396 /* 1397 * To handle recovery specific sequences during the rpm suspend we are 1398 * about to trigger 1399 */ 1400 a6xx_gpu->hung = true; 1401 1402 /* Halt SQE first */ 1403 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1404 1405 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 1406 1407 /* active_submit won't change until we make a submission */ 1408 mutex_lock(&gpu->active_lock); 1409 active_submits = gpu->active_submits; 1410 1411 /* 1412 * Temporarily clear active_submits count to silence a WARN() in the 1413 * runtime suspend cb 1414 */ 1415 gpu->active_submits = 0; 1416 1417 if (adreno_has_gmu_wrapper(adreno_gpu)) { 1418 /* Drain the outstanding traffic on memory buses */ 1419 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1420 1421 /* Reset the GPU to a clean state */ 1422 a6xx_gpu_sw_reset(gpu, true); 1423 a6xx_gpu_sw_reset(gpu, false); 1424 } 1425 1426 reinit_completion(&gmu->pd_gate); 1427 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); 1428 dev_pm_genpd_synced_poweroff(gmu->cxpd); 1429 1430 /* Drop the rpm refcount from active submits */ 1431 if (active_submits) 1432 pm_runtime_put(&gpu->pdev->dev); 1433 1434 /* And the final one from recover worker */ 1435 pm_runtime_put_sync(&gpu->pdev->dev); 1436 1437 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) 1438 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); 1439 1440 dev_pm_genpd_remove_notifier(gmu->cxpd); 1441 1442 pm_runtime_use_autosuspend(&gpu->pdev->dev); 1443 1444 if (active_submits) 1445 pm_runtime_get(&gpu->pdev->dev); 1446 1447 pm_runtime_get_sync(&gpu->pdev->dev); 1448 1449 gpu->active_submits = active_submits; 1450 mutex_unlock(&gpu->active_lock); 1451 1452 msm_gpu_hw_init(gpu); 1453 a6xx_gpu->hung = false; 1454 } 1455 1456 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 1457 { 1458 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1459 static const char *uche_clients[7] = { 1460 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", 1461 }; 1462 u32 val; 1463 1464 if (adreno_is_a7xx(adreno_gpu)) { 1465 if (mid != 1 && mid != 2 && mid != 3 && mid != 8) 1466 return "UNKNOWN"; 1467 } else { 1468 if (mid < 1 || mid > 3) 1469 return "UNKNOWN"; 1470 } 1471 1472 /* 1473 * The source of the data depends on the mid ID read from FSYNR1. 1474 * and the client ID read from the UCHE block 1475 */ 1476 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); 1477 1478 if (adreno_is_a7xx(adreno_gpu)) { 1479 /* Bit 3 for mid=3 indicates BR or BV */ 1480 static const char *uche_clients_a7xx[16] = { 1481 "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", 1482 "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP", 1483 "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", 1484 "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP", 1485 }; 1486 1487 /* LPAC has the same clients as BR and BV, but because it is 1488 * compute-only some of them do not exist and there are holes 1489 * in the array. 1490 */ 1491 static const char *uche_clients_lpac_a7xx[8] = { 1492 "-", "LPAC_SP", "-", "-", 1493 "LPAC_HLSQ", "-", "-", "LPAC_TP", 1494 }; 1495 1496 val &= GENMASK(6, 0); 1497 1498 /* mid=3 refers to BR or BV */ 1499 if (mid == 3) { 1500 if (val < ARRAY_SIZE(uche_clients_a7xx)) 1501 return uche_clients_a7xx[val]; 1502 else 1503 return "UCHE"; 1504 } 1505 1506 /* mid=8 refers to LPAC */ 1507 if (mid == 8) { 1508 if (val < ARRAY_SIZE(uche_clients_lpac_a7xx)) 1509 return uche_clients_lpac_a7xx[val]; 1510 else 1511 return "UCHE_LPAC"; 1512 } 1513 1514 /* mid=2 is a catchall for everything else in LPAC */ 1515 if (mid == 2) 1516 return "UCHE_LPAC"; 1517 1518 /* mid=1 is a catchall for everything else in BR/BV */ 1519 return "UCHE"; 1520 } else if (adreno_is_a660_family(adreno_gpu)) { 1521 static const char *uche_clients_a660[8] = { 1522 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP", 1523 }; 1524 1525 static const char *uche_clients_a660_not[8] = { 1526 "not VFD", "not SP", "not VSC", "not VPC", 1527 "not HLSQ", "not PC", "not LRZ", "not TP", 1528 }; 1529 1530 val &= GENMASK(6, 0); 1531 1532 if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660)) 1533 return uche_clients_a660[val]; 1534 1535 if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not)) 1536 return uche_clients_a660_not[val]; 1537 1538 return "UCHE"; 1539 } else { 1540 /* mid = 3 is most precise and refers to only one block per client */ 1541 if (mid == 3) 1542 return uche_clients[val & 7]; 1543 1544 /* For mid=2 the source is TP or VFD except when the client id is 0 */ 1545 if (mid == 2) 1546 return ((val & 7) == 0) ? "TP" : "TP|VFD"; 1547 1548 /* For mid=1 just return "UCHE" as a catchall for everything else */ 1549 return "UCHE"; 1550 } 1551 } 1552 1553 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) 1554 { 1555 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1556 1557 if (id == 0) 1558 return "CP"; 1559 else if (id == 4) 1560 return "CCU"; 1561 else if (id == 6) 1562 return "CDP Prefetch"; 1563 else if (id == 7) 1564 return "GMU"; 1565 else if (id == 5 && adreno_is_a7xx(adreno_gpu)) 1566 return "Flag cache"; 1567 1568 return a6xx_uche_fault_block(gpu, id); 1569 } 1570 1571 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 1572 { 1573 struct msm_gpu *gpu = arg; 1574 struct adreno_smmu_fault_info *info = data; 1575 const char *block = "unknown"; 1576 1577 u32 scratch[] = { 1578 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1579 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1580 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1581 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), 1582 }; 1583 1584 if (info) 1585 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); 1586 1587 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); 1588 } 1589 1590 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 1591 { 1592 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 1593 1594 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 1595 u32 val; 1596 1597 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 1598 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 1599 dev_err_ratelimited(&gpu->pdev->dev, 1600 "CP | opcode error | possible opcode=0x%8.8X\n", 1601 val); 1602 } 1603 1604 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 1605 dev_err_ratelimited(&gpu->pdev->dev, 1606 "CP ucode error interrupt\n"); 1607 1608 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 1609 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 1610 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 1611 1612 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 1613 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 1614 1615 dev_err_ratelimited(&gpu->pdev->dev, 1616 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 1617 val & (1 << 20) ? "READ" : "WRITE", 1618 (val & 0x3ffff), val); 1619 } 1620 1621 if (status & A6XX_CP_INT_CP_AHB_ERROR && !adreno_is_a7xx(to_adreno_gpu(gpu))) 1622 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 1623 1624 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 1625 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 1626 1627 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 1628 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 1629 1630 } 1631 1632 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1633 { 1634 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1635 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1636 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1637 1638 /* 1639 * If stalled on SMMU fault, we could trip the GPU's hang detection, 1640 * but the fault handler will trigger the devcore dump, and we want 1641 * to otherwise resume normally rather than killing the submit, so 1642 * just bail. 1643 */ 1644 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1645 return; 1646 1647 /* 1648 * Force the GPU to stay on until after we finish 1649 * collecting information 1650 */ 1651 if (!adreno_has_gmu_wrapper(adreno_gpu)) 1652 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 1653 1654 DRM_DEV_ERROR(&gpu->pdev->dev, 1655 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 1656 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, 1657 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 1658 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1659 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1660 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 1661 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 1662 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 1663 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 1664 1665 /* Turn off the hangcheck timer to keep it from bothering us */ 1666 del_timer(&gpu->hangcheck_timer); 1667 1668 kthread_queue_work(gpu->worker, &gpu->recover_work); 1669 } 1670 1671 static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) 1672 { 1673 u32 status; 1674 1675 status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); 1676 gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); 1677 1678 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); 1679 1680 /* 1681 * Ignore FASTBLEND violations, because the HW will silently fall back 1682 * to legacy blending. 1683 */ 1684 if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1685 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { 1686 del_timer(&gpu->hangcheck_timer); 1687 1688 kthread_queue_work(gpu->worker, &gpu->recover_work); 1689 } 1690 } 1691 1692 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1693 { 1694 struct msm_drm_private *priv = gpu->dev->dev_private; 1695 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1696 1697 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1698 1699 if (priv->disable_err_irq) 1700 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1701 1702 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1703 a6xx_fault_detect_irq(gpu); 1704 1705 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1706 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1707 1708 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1709 a6xx_cp_hw_err_irq(gpu); 1710 1711 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1712 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1713 1714 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1715 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1716 1717 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1718 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1719 1720 if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1721 a7xx_sw_fuse_violation_irq(gpu); 1722 1723 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { 1724 msm_gpu_retire(gpu); 1725 a6xx_preempt_trigger(gpu); 1726 } 1727 1728 if (status & A6XX_RBBM_INT_0_MASK_CP_SW) 1729 a6xx_preempt_irq(gpu); 1730 1731 return IRQ_HANDLED; 1732 } 1733 1734 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1735 { 1736 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1737 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1738 } 1739 1740 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1741 { 1742 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1743 struct msm_gpu *gpu = &adreno_gpu->base; 1744 u32 cntl1_regval = 0; 1745 1746 if (IS_ERR(a6xx_gpu->llc_mmio)) 1747 return; 1748 1749 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1750 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1751 1752 gpu_scid &= 0x1f; 1753 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1754 (gpu_scid << 15) | (gpu_scid << 20); 1755 1756 /* On A660, the SCID programming for UCHE traffic is done in 1757 * A6XX_GBIF_SCACHE_CNTL0[14:10] 1758 */ 1759 if (adreno_is_a660_family(adreno_gpu)) 1760 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | 1761 (1 << 8), (gpu_scid << 10) | (1 << 8)); 1762 } 1763 1764 /* 1765 * For targets with a MMU500, activate the slice but don't program the 1766 * register. The XBL will take care of that. 1767 */ 1768 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1769 if (!a6xx_gpu->have_mmu500) { 1770 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1771 1772 gpuhtw_scid &= 0x1f; 1773 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1774 } 1775 } 1776 1777 if (!cntl1_regval) 1778 return; 1779 1780 /* 1781 * Program the slice IDs for the various GPU blocks and GPU MMU 1782 * pagetables 1783 */ 1784 if (!a6xx_gpu->have_mmu500) { 1785 a6xx_llc_write(a6xx_gpu, 1786 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1787 1788 /* 1789 * Program cacheability overrides to not allocate cache 1790 * lines on a write miss 1791 */ 1792 a6xx_llc_rmw(a6xx_gpu, 1793 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1794 return; 1795 } 1796 1797 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); 1798 } 1799 1800 static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1801 { 1802 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1803 struct msm_gpu *gpu = &adreno_gpu->base; 1804 1805 if (IS_ERR(a6xx_gpu->llc_mmio)) 1806 return; 1807 1808 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1809 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1810 1811 gpu_scid &= GENMASK(4, 0); 1812 1813 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, 1814 FIELD_PREP(GENMASK(29, 25), gpu_scid) | 1815 FIELD_PREP(GENMASK(24, 20), gpu_scid) | 1816 FIELD_PREP(GENMASK(19, 15), gpu_scid) | 1817 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 1818 FIELD_PREP(GENMASK(9, 5), gpu_scid) | 1819 FIELD_PREP(GENMASK(4, 0), gpu_scid)); 1820 1821 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, 1822 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 1823 BIT(8)); 1824 } 1825 1826 llcc_slice_activate(a6xx_gpu->htw_llc_slice); 1827 } 1828 1829 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 1830 { 1831 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1832 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1833 return; 1834 1835 llcc_slice_putd(a6xx_gpu->llc_slice); 1836 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 1837 } 1838 1839 static void a6xx_llc_slices_init(struct platform_device *pdev, 1840 struct a6xx_gpu *a6xx_gpu, bool is_a7xx) 1841 { 1842 struct device_node *phandle; 1843 1844 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1845 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1846 return; 1847 1848 /* 1849 * There is a different programming path for A6xx targets with an 1850 * mmu500 attached, so detect if that is the case 1851 */ 1852 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 1853 a6xx_gpu->have_mmu500 = (phandle && 1854 of_device_is_compatible(phandle, "arm,mmu-500")); 1855 of_node_put(phandle); 1856 1857 if (is_a7xx || !a6xx_gpu->have_mmu500) 1858 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem"); 1859 else 1860 a6xx_gpu->llc_mmio = NULL; 1861 1862 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 1863 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 1864 1865 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1866 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 1867 } 1868 1869 static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) 1870 { 1871 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1872 struct msm_gpu *gpu = &adreno_gpu->base; 1873 u32 fuse_val; 1874 int ret; 1875 1876 if (adreno_is_a750(adreno_gpu)) { 1877 /* 1878 * Assume that if qcom scm isn't available, that whatever 1879 * replacement allows writing the fuse register ourselves. 1880 * Users of alternative firmware need to make sure this 1881 * register is writeable or indicate that it's not somehow. 1882 * Print a warning because if you mess this up you're about to 1883 * crash horribly. 1884 */ 1885 if (!qcom_scm_is_available()) { 1886 dev_warn_once(gpu->dev->dev, 1887 "SCM is not available, poking fuse register\n"); 1888 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, 1889 A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1890 A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | 1891 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); 1892 adreno_gpu->has_ray_tracing = true; 1893 return 0; 1894 } 1895 1896 ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | 1897 QCOM_SCM_GPU_TSENSE_EN_REQ); 1898 if (ret) 1899 return ret; 1900 1901 /* 1902 * On a750 raytracing may be disabled by the firmware, find out 1903 * whether that's the case. The scm call above sets the fuse 1904 * register. 1905 */ 1906 fuse_val = a6xx_llc_read(a6xx_gpu, 1907 REG_A7XX_CX_MISC_SW_FUSE_VALUE); 1908 adreno_gpu->has_ray_tracing = 1909 !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); 1910 } else if (adreno_is_a740(adreno_gpu)) { 1911 /* Raytracing is always enabled on a740 */ 1912 adreno_gpu->has_ray_tracing = true; 1913 } 1914 1915 return 0; 1916 } 1917 1918 1919 #define GBIF_CLIENT_HALT_MASK BIT(0) 1920 #define GBIF_ARB_HALT_MASK BIT(1) 1921 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) 1922 #define VBIF_RESET_ACK_MASK 0xF0 1923 #define GPR0_GBIF_HALT_REQUEST 0x1E0 1924 1925 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) 1926 { 1927 struct msm_gpu *gpu = &adreno_gpu->base; 1928 1929 if (adreno_is_a619_holi(adreno_gpu)) { 1930 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); 1931 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & 1932 (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); 1933 } else if (!a6xx_has_gbif(adreno_gpu)) { 1934 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); 1935 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 1936 (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK); 1937 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 1938 1939 return; 1940 } 1941 1942 if (gx_off) { 1943 /* Halt the gx side of GBIF */ 1944 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); 1945 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); 1946 } 1947 1948 /* Halt new client requests on GBIF */ 1949 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 1950 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1951 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 1952 1953 /* Halt all AXI requests on GBIF */ 1954 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 1955 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1956 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 1957 1958 /* The GBIF halt needs to be explicitly cleared */ 1959 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 1960 } 1961 1962 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) 1963 { 1964 /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ 1965 if (adreno_is_a610(to_adreno_gpu(gpu))) 1966 return; 1967 1968 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); 1969 /* Perform a bogus read and add a brief delay to ensure ordering. */ 1970 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); 1971 udelay(1); 1972 1973 /* The reset line needs to be asserted for at least 100 us */ 1974 if (assert) 1975 udelay(100); 1976 } 1977 1978 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) 1979 { 1980 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1981 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1982 int ret; 1983 1984 gpu->needs_hw_init = true; 1985 1986 trace_msm_gpu_resume(0); 1987 1988 mutex_lock(&a6xx_gpu->gmu.lock); 1989 ret = a6xx_gmu_resume(a6xx_gpu); 1990 mutex_unlock(&a6xx_gpu->gmu.lock); 1991 if (ret) 1992 return ret; 1993 1994 msm_devfreq_resume(gpu); 1995 1996 adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu); 1997 1998 return ret; 1999 } 2000 2001 static int a6xx_pm_resume(struct msm_gpu *gpu) 2002 { 2003 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2004 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2005 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2006 unsigned long freq = gpu->fast_rate; 2007 struct dev_pm_opp *opp; 2008 int ret; 2009 2010 gpu->needs_hw_init = true; 2011 2012 trace_msm_gpu_resume(0); 2013 2014 mutex_lock(&a6xx_gpu->gmu.lock); 2015 2016 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); 2017 if (IS_ERR(opp)) { 2018 ret = PTR_ERR(opp); 2019 goto err_set_opp; 2020 } 2021 dev_pm_opp_put(opp); 2022 2023 /* Set the core clock and bus bw, having VDD scaling in mind */ 2024 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 2025 2026 pm_runtime_resume_and_get(gmu->dev); 2027 pm_runtime_resume_and_get(gmu->gxpd); 2028 2029 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 2030 if (ret) 2031 goto err_bulk_clk; 2032 2033 if (adreno_is_a619_holi(adreno_gpu)) 2034 a6xx_sptprac_enable(gmu); 2035 2036 /* If anything goes south, tear the GPU down piece by piece.. */ 2037 if (ret) { 2038 err_bulk_clk: 2039 pm_runtime_put(gmu->gxpd); 2040 pm_runtime_put(gmu->dev); 2041 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2042 } 2043 err_set_opp: 2044 mutex_unlock(&a6xx_gpu->gmu.lock); 2045 2046 if (!ret) 2047 msm_devfreq_resume(gpu); 2048 2049 return ret; 2050 } 2051 2052 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) 2053 { 2054 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2055 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2056 int i, ret; 2057 2058 trace_msm_gpu_suspend(0); 2059 2060 a6xx_llc_deactivate(a6xx_gpu); 2061 2062 msm_devfreq_suspend(gpu); 2063 2064 mutex_lock(&a6xx_gpu->gmu.lock); 2065 ret = a6xx_gmu_stop(a6xx_gpu); 2066 mutex_unlock(&a6xx_gpu->gmu.lock); 2067 if (ret) 2068 return ret; 2069 2070 if (a6xx_gpu->shadow_bo) 2071 for (i = 0; i < gpu->nr_rings; i++) 2072 a6xx_gpu->shadow[i] = 0; 2073 2074 gpu->suspend_count++; 2075 2076 return 0; 2077 } 2078 2079 static int a6xx_pm_suspend(struct msm_gpu *gpu) 2080 { 2081 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2082 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2083 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2084 int i; 2085 2086 trace_msm_gpu_suspend(0); 2087 2088 msm_devfreq_suspend(gpu); 2089 2090 mutex_lock(&a6xx_gpu->gmu.lock); 2091 2092 /* Drain the outstanding traffic on memory buses */ 2093 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 2094 2095 if (adreno_is_a619_holi(adreno_gpu)) 2096 a6xx_sptprac_disable(gmu); 2097 2098 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 2099 2100 pm_runtime_put_sync(gmu->gxpd); 2101 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2102 pm_runtime_put_sync(gmu->dev); 2103 2104 mutex_unlock(&a6xx_gpu->gmu.lock); 2105 2106 if (a6xx_gpu->shadow_bo) 2107 for (i = 0; i < gpu->nr_rings; i++) 2108 a6xx_gpu->shadow[i] = 0; 2109 2110 gpu->suspend_count++; 2111 2112 return 0; 2113 } 2114 2115 static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2116 { 2117 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2118 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2119 2120 mutex_lock(&a6xx_gpu->gmu.lock); 2121 2122 /* Force the GPU power on so we can read this register */ 2123 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2124 2125 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2126 2127 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2128 2129 mutex_unlock(&a6xx_gpu->gmu.lock); 2130 2131 return 0; 2132 } 2133 2134 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2135 { 2136 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2137 return 0; 2138 } 2139 2140 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 2141 { 2142 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2143 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2144 2145 return a6xx_gpu->cur_ring; 2146 } 2147 2148 static void a6xx_destroy(struct msm_gpu *gpu) 2149 { 2150 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2151 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2152 2153 if (a6xx_gpu->sqe_bo) { 2154 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 2155 drm_gem_object_put(a6xx_gpu->sqe_bo); 2156 } 2157 2158 if (a6xx_gpu->shadow_bo) { 2159 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 2160 drm_gem_object_put(a6xx_gpu->shadow_bo); 2161 } 2162 2163 a6xx_llc_slices_destroy(a6xx_gpu); 2164 2165 a6xx_gmu_remove(a6xx_gpu); 2166 2167 adreno_gpu_cleanup(adreno_gpu); 2168 2169 kfree(a6xx_gpu); 2170 } 2171 2172 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) 2173 { 2174 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2175 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2176 u64 busy_cycles; 2177 2178 /* 19.2MHz */ 2179 *out_sample_rate = 19200000; 2180 2181 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 2182 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 2183 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 2184 2185 return busy_cycles; 2186 } 2187 2188 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 2189 bool suspended) 2190 { 2191 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2192 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2193 2194 mutex_lock(&a6xx_gpu->gmu.lock); 2195 a6xx_gmu_set_freq(gpu, opp, suspended); 2196 mutex_unlock(&a6xx_gpu->gmu.lock); 2197 } 2198 2199 static struct msm_gem_address_space * 2200 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) 2201 { 2202 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2203 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2204 unsigned long quirks = 0; 2205 2206 /* 2207 * This allows GPU to set the bus attributes required to use system 2208 * cache on behalf of the iommu page table walker. 2209 */ 2210 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && 2211 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) 2212 quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; 2213 2214 return adreno_iommu_create_address_space(gpu, pdev, quirks); 2215 } 2216 2217 static struct msm_gem_address_space * 2218 a6xx_create_private_address_space(struct msm_gpu *gpu) 2219 { 2220 struct msm_mmu *mmu; 2221 2222 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 2223 2224 if (IS_ERR(mmu)) 2225 return ERR_CAST(mmu); 2226 2227 return msm_gem_address_space_create(mmu, 2228 "gpu", 0x100000000ULL, 2229 adreno_private_address_space_size(gpu)); 2230 } 2231 2232 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2233 { 2234 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2235 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2236 2237 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 2238 return a6xx_gpu->shadow[ring->id]; 2239 2240 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 2241 } 2242 2243 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2244 { 2245 struct msm_cp_state cp_state = { 2246 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 2247 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 2248 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 2249 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), 2250 }; 2251 bool progress; 2252 2253 /* 2254 * Adjust the remaining data to account for what has already been 2255 * fetched from memory, but not yet consumed by the SQE. 2256 * 2257 * This is not *technically* correct, the amount buffered could 2258 * exceed the IB size due to hw prefetching ahead, but: 2259 * 2260 * (1) We aren't trying to find the exact position, just whether 2261 * progress has been made 2262 * (2) The CP_REG_TO_MEM at the end of a submit should be enough 2263 * to prevent prefetching into an unrelated submit. (And 2264 * either way, at some point the ROQ will be full.) 2265 */ 2266 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16; 2267 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16; 2268 2269 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); 2270 2271 ring->last_cp_state = cp_state; 2272 2273 return progress; 2274 } 2275 2276 static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) 2277 { 2278 if (!info->speedbins) 2279 return UINT_MAX; 2280 2281 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) 2282 if (info->speedbins[i].fuse == fuse) 2283 return BIT(info->speedbins[i].speedbin); 2284 2285 return UINT_MAX; 2286 } 2287 2288 static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) 2289 { 2290 u32 supp_hw; 2291 u32 speedbin; 2292 int ret; 2293 2294 ret = adreno_read_speedbin(dev, &speedbin); 2295 /* 2296 * -ENOENT means that the platform doesn't support speedbin which is 2297 * fine 2298 */ 2299 if (ret == -ENOENT) { 2300 return 0; 2301 } else if (ret) { 2302 dev_err_probe(dev, ret, 2303 "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); 2304 return ret; 2305 } 2306 2307 supp_hw = fuse_to_supp_hw(info, speedbin); 2308 2309 if (supp_hw == UINT_MAX) { 2310 DRM_DEV_ERROR(dev, 2311 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", 2312 speedbin); 2313 supp_hw = BIT(0); /* Default */ 2314 } 2315 2316 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); 2317 if (ret) 2318 return ret; 2319 2320 return 0; 2321 } 2322 2323 static const struct adreno_gpu_funcs funcs = { 2324 .base = { 2325 .get_param = adreno_get_param, 2326 .set_param = adreno_set_param, 2327 .hw_init = a6xx_hw_init, 2328 .ucode_load = a6xx_ucode_load, 2329 .pm_suspend = a6xx_gmu_pm_suspend, 2330 .pm_resume = a6xx_gmu_pm_resume, 2331 .recover = a6xx_recover, 2332 .submit = a6xx_submit, 2333 .active_ring = a6xx_active_ring, 2334 .irq = a6xx_irq, 2335 .destroy = a6xx_destroy, 2336 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2337 .show = a6xx_show, 2338 #endif 2339 .gpu_busy = a6xx_gpu_busy, 2340 .gpu_get_freq = a6xx_gmu_get_freq, 2341 .gpu_set_freq = a6xx_gpu_set_freq, 2342 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2343 .gpu_state_get = a6xx_gpu_state_get, 2344 .gpu_state_put = a6xx_gpu_state_put, 2345 #endif 2346 .create_address_space = a6xx_create_address_space, 2347 .create_private_address_space = a6xx_create_private_address_space, 2348 .get_rptr = a6xx_get_rptr, 2349 .progress = a6xx_progress, 2350 }, 2351 .get_timestamp = a6xx_gmu_get_timestamp, 2352 }; 2353 2354 static const struct adreno_gpu_funcs funcs_gmuwrapper = { 2355 .base = { 2356 .get_param = adreno_get_param, 2357 .set_param = adreno_set_param, 2358 .hw_init = a6xx_hw_init, 2359 .ucode_load = a6xx_ucode_load, 2360 .pm_suspend = a6xx_pm_suspend, 2361 .pm_resume = a6xx_pm_resume, 2362 .recover = a6xx_recover, 2363 .submit = a6xx_submit, 2364 .active_ring = a6xx_active_ring, 2365 .irq = a6xx_irq, 2366 .destroy = a6xx_destroy, 2367 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2368 .show = a6xx_show, 2369 #endif 2370 .gpu_busy = a6xx_gpu_busy, 2371 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2372 .gpu_state_get = a6xx_gpu_state_get, 2373 .gpu_state_put = a6xx_gpu_state_put, 2374 #endif 2375 .create_address_space = a6xx_create_address_space, 2376 .create_private_address_space = a6xx_create_private_address_space, 2377 .get_rptr = a6xx_get_rptr, 2378 .progress = a6xx_progress, 2379 }, 2380 .get_timestamp = a6xx_get_timestamp, 2381 }; 2382 2383 static const struct adreno_gpu_funcs funcs_a7xx = { 2384 .base = { 2385 .get_param = adreno_get_param, 2386 .set_param = adreno_set_param, 2387 .hw_init = a6xx_hw_init, 2388 .ucode_load = a6xx_ucode_load, 2389 .pm_suspend = a6xx_gmu_pm_suspend, 2390 .pm_resume = a6xx_gmu_pm_resume, 2391 .recover = a6xx_recover, 2392 .submit = a7xx_submit, 2393 .active_ring = a6xx_active_ring, 2394 .irq = a6xx_irq, 2395 .destroy = a6xx_destroy, 2396 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2397 .show = a6xx_show, 2398 #endif 2399 .gpu_busy = a6xx_gpu_busy, 2400 .gpu_get_freq = a6xx_gmu_get_freq, 2401 .gpu_set_freq = a6xx_gpu_set_freq, 2402 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2403 .gpu_state_get = a6xx_gpu_state_get, 2404 .gpu_state_put = a6xx_gpu_state_put, 2405 #endif 2406 .create_address_space = a6xx_create_address_space, 2407 .create_private_address_space = a6xx_create_private_address_space, 2408 .get_rptr = a6xx_get_rptr, 2409 .progress = a6xx_progress, 2410 }, 2411 .get_timestamp = a6xx_gmu_get_timestamp, 2412 }; 2413 2414 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 2415 { 2416 struct msm_drm_private *priv = dev->dev_private; 2417 struct platform_device *pdev = priv->gpu_pdev; 2418 struct adreno_platform_config *config = pdev->dev.platform_data; 2419 struct device_node *node; 2420 struct a6xx_gpu *a6xx_gpu; 2421 struct adreno_gpu *adreno_gpu; 2422 struct msm_gpu *gpu; 2423 bool is_a7xx; 2424 int ret; 2425 2426 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 2427 if (!a6xx_gpu) 2428 return ERR_PTR(-ENOMEM); 2429 2430 adreno_gpu = &a6xx_gpu->base; 2431 gpu = &adreno_gpu->base; 2432 2433 mutex_init(&a6xx_gpu->gmu.lock); 2434 2435 adreno_gpu->registers = NULL; 2436 2437 /* Check if there is a GMU phandle and set it up */ 2438 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 2439 /* FIXME: How do we gracefully handle this? */ 2440 BUG_ON(!node); 2441 2442 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); 2443 2444 adreno_gpu->base.hw_apriv = 2445 !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); 2446 2447 /* gpu->info only gets assigned in adreno_gpu_init() */ 2448 is_a7xx = config->info->family == ADRENO_7XX_GEN1 || 2449 config->info->family == ADRENO_7XX_GEN2 || 2450 config->info->family == ADRENO_7XX_GEN3; 2451 2452 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); 2453 2454 ret = a6xx_set_supported_hw(&pdev->dev, config->info); 2455 if (ret) { 2456 a6xx_llc_slices_destroy(a6xx_gpu); 2457 kfree(a6xx_gpu); 2458 return ERR_PTR(ret); 2459 } 2460 2461 if (is_a7xx) 2462 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); 2463 else if (adreno_has_gmu_wrapper(adreno_gpu)) 2464 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); 2465 else 2466 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 2467 if (ret) { 2468 a6xx_destroy(&(a6xx_gpu->base.base)); 2469 return ERR_PTR(ret); 2470 } 2471 2472 /* 2473 * For now only clamp to idle freq for devices where this is known not 2474 * to cause power supply issues: 2475 */ 2476 if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 2477 priv->gpu_clamp_to_idle = true; 2478 2479 if (adreno_has_gmu_wrapper(adreno_gpu)) 2480 ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); 2481 else 2482 ret = a6xx_gmu_init(a6xx_gpu, node); 2483 of_node_put(node); 2484 if (ret) { 2485 a6xx_destroy(&(a6xx_gpu->base.base)); 2486 return ERR_PTR(ret); 2487 } 2488 2489 if (adreno_is_a7xx(adreno_gpu)) { 2490 ret = a7xx_cx_mem_init(a6xx_gpu); 2491 if (ret) { 2492 a6xx_destroy(&(a6xx_gpu->base.base)); 2493 return ERR_PTR(ret); 2494 } 2495 } 2496 2497 if (gpu->aspace) 2498 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 2499 a6xx_fault_handler); 2500 2501 a6xx_calc_ubwc_config(adreno_gpu); 2502 /* Set up the preemption specific bits and pieces for each ringbuffer */ 2503 a6xx_preempt_init(gpu); 2504 2505 return gpu; 2506 } 2507