1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 3 #ifndef _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H 4 #define _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H 5 6 /* ADC Channel Index */ 7 #define MT6358_AUXADC_BATADC 0 8 #define MT6358_AUXADC_VCDT 1 9 #define MT6358_AUXADC_BAT_TEMP 2 10 #define MT6358_AUXADC_CHIP_TEMP 3 11 #define MT6358_AUXADC_ACCDET 4 12 #define MT6358_AUXADC_VDCXO 5 13 #define MT6358_AUXADC_TSX_TEMP 6 14 #define MT6358_AUXADC_HPOFS_CAL 7 15 #define MT6358_AUXADC_DCXO_TEMP 8 16 #define MT6358_AUXADC_VBIF 9 17 #define MT6358_AUXADC_VCORE_TEMP 10 18 #define MT6358_AUXADC_VPROC_TEMP 11 19 #define MT6358_AUXADC_VGPU_TEMP 12 20 #define MT6358_AUXADC_VBAT 13 21 22 #endif 23