1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr 11 12#include "r9a07g043.dtsi" 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a55"; 21 reg = <0>; 22 device_type = "cpu"; 23 #cooling-cells = <2>; 24 next-level-cache = <&L3_CA55>; 25 enable-method = "psci"; 26 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 27 operating-points-v2 = <&cluster0_opp>; 28 }; 29 30 L3_CA55: cache-controller-0 { 31 compatible = "cache"; 32 cache-unified; 33 cache-size = <0x40000>; 34 cache-level = <3>; 35 }; 36 }; 37 38 pmu { 39 compatible = "arm,cortex-a55-pmu"; 40 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 41 }; 42 43 psci { 44 compatible = "arm,psci-1.0", "arm,psci-0.2"; 45 method = "smc"; 46 }; 47 48 timer { 49 compatible = "arm,armv8-timer"; 50 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 51 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 52 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 53 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 54 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 55 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 56 "hyp-virt"; 57 }; 58}; 59 60&soc { 61 interrupt-parent = <&gic>; 62 63 cru: video@10830000 { 64 compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru"; 65 reg = <0 0x10830000 0 0x400>; 66 clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>, 67 <&cpg CPG_MOD R9A07G043_CRU_PCLK>, 68 <&cpg CPG_MOD R9A07G043_CRU_ACLK>; 69 clock-names = "video", "apb", "axi"; 70 interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>, 71 <SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>, 72 <SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>; 73 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; 74 resets = <&cpg R9A07G043_CRU_PRESETN>, 75 <&cpg R9A07G043_CRU_ARESETN>; 76 reset-names = "presetn", "aresetn"; 77 power-domains = <&cpg>; 78 status = "disabled"; 79 80 ports { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 port@1 { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 reg = <1>; 89 crucsi2: endpoint@0 { 90 reg = <0>; 91 remote-endpoint = <&csi2cru>; 92 }; 93 }; 94 }; 95 }; 96 97 csi2: csi2@10830400 { 98 compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2"; 99 reg = <0 0x10830400 0 0xfc00>; 100 interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>; 101 clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>, 102 <&cpg CPG_MOD R9A07G043_CRU_VCLK>, 103 <&cpg CPG_MOD R9A07G043_CRU_PCLK>; 104 clock-names = "system", "video", "apb"; 105 resets = <&cpg R9A07G043_CRU_PRESETN>, 106 <&cpg R9A07G043_CRU_CMN_RSTB>; 107 reset-names = "presetn", "cmn-rstb"; 108 power-domains = <&cpg>; 109 status = "disabled"; 110 111 ports { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 115 port@0 { 116 reg = <0>; 117 }; 118 119 port@1 { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 reg = <1>; 123 124 csi2cru: endpoint@0 { 125 reg = <0>; 126 remote-endpoint = <&crucsi2>; 127 }; 128 }; 129 }; 130 }; 131 132 irqc: interrupt-controller@110a0000 { 133 compatible = "renesas,r9a07g043u-irqc", 134 "renesas,rzg2l-irqc"; 135 reg = <0 0x110a0000 0 0x10000>; 136 #interrupt-cells = <2>; 137 #address-cells = <0>; 138 interrupt-controller; 139 interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>, 140 <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, 141 <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, 142 <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>, 143 <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>, 144 <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>, 145 <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>, 146 <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>, 147 <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>, 148 <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>, 149 <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>, 150 <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>, 151 <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>, 152 <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>, 153 <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>, 154 <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>, 155 <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>, 156 <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>, 157 <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>, 158 <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>, 159 <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>, 160 <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>, 161 <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>, 162 <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>, 163 <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>, 164 <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>, 165 <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>, 166 <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>, 167 <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>, 168 <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>, 169 <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>, 170 <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>, 171 <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>, 172 <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>, 173 <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>, 174 <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>, 175 <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>, 176 <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>, 177 <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>, 178 <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>, 179 <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>, 180 <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>, 181 <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>, 182 <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>, 183 <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>, 184 <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>, 185 <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>, 186 <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>; 187 interrupt-names = "nmi", 188 "irq0", "irq1", "irq2", "irq3", 189 "irq4", "irq5", "irq6", "irq7", 190 "tint0", "tint1", "tint2", "tint3", 191 "tint4", "tint5", "tint6", "tint7", 192 "tint8", "tint9", "tint10", "tint11", 193 "tint12", "tint13", "tint14", "tint15", 194 "tint16", "tint17", "tint18", "tint19", 195 "tint20", "tint21", "tint22", "tint23", 196 "tint24", "tint25", "tint26", "tint27", 197 "tint28", "tint29", "tint30", "tint31", 198 "bus-err", "ec7tie1-0", "ec7tie2-0", 199 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", 200 "ec7tiovf-1"; 201 clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, 202 <&cpg CPG_MOD R9A07G043_IA55_PCLK>; 203 clock-names = "clk", "pclk"; 204 power-domains = <&cpg>; 205 resets = <&cpg R9A07G043_IA55_RESETN>; 206 }; 207 208 gic: interrupt-controller@11900000 { 209 compatible = "arm,gic-v3"; 210 #interrupt-cells = <3>; 211 #address-cells = <0>; 212 interrupt-controller; 213 reg = <0x0 0x11900000 0 0x40000>, 214 <0x0 0x11940000 0 0x60000>; 215 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 216 }; 217}; 218 219&sysc { 220 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>, 221 <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>, 222 <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>, 223 <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; 224 interrupt-names = "lpm_int", "ca55stbydone_int", 225 "cm33stbyr_int", "ca55_deny"; 226}; 227