1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 static void 78 mt7530_mutex_lock(struct mt7530_priv *priv) 79 { 80 if (priv->bus) 81 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 82 } 83 84 static void 85 mt7530_mutex_unlock(struct mt7530_priv *priv) 86 { 87 if (priv->bus) 88 mutex_unlock(&priv->bus->mdio_lock); 89 } 90 91 static void 92 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 93 { 94 struct mii_bus *bus = priv->bus; 95 int ret; 96 97 mt7530_mutex_lock(priv); 98 99 /* Write the desired MMD Devad */ 100 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 101 MII_MMD_CTRL, MDIO_MMD_VEND2); 102 if (ret < 0) 103 goto err; 104 105 /* Write the desired MMD register address */ 106 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 107 MII_MMD_DATA, reg); 108 if (ret < 0) 109 goto err; 110 111 /* Select the Function : DATA with no post increment */ 112 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 113 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 114 if (ret < 0) 115 goto err; 116 117 /* Write the data into MMD's selected register */ 118 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 119 MII_MMD_DATA, val); 120 err: 121 if (ret < 0) 122 dev_err(&bus->dev, "failed to write mmd register\n"); 123 124 mt7530_mutex_unlock(priv); 125 } 126 127 static void 128 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 129 { 130 struct mii_bus *bus = priv->bus; 131 u32 val; 132 int ret; 133 134 mt7530_mutex_lock(priv); 135 136 /* Write the desired MMD Devad */ 137 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 138 MII_MMD_CTRL, MDIO_MMD_VEND2); 139 if (ret < 0) 140 goto err; 141 142 /* Write the desired MMD register address */ 143 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 144 MII_MMD_DATA, reg); 145 if (ret < 0) 146 goto err; 147 148 /* Select the Function : DATA with no post increment */ 149 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 150 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 151 if (ret < 0) 152 goto err; 153 154 /* Read the content of the MMD's selected register */ 155 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 156 MII_MMD_DATA); 157 val &= ~mask; 158 val |= set; 159 /* Write the data into MMD's selected register */ 160 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 161 MII_MMD_DATA, val); 162 err: 163 if (ret < 0) 164 dev_err(&bus->dev, "failed to write mmd register\n"); 165 166 mt7530_mutex_unlock(priv); 167 } 168 169 static void 170 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 171 { 172 core_rmw(priv, reg, 0, val); 173 } 174 175 static void 176 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 177 { 178 core_rmw(priv, reg, val, 0); 179 } 180 181 static int 182 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 183 { 184 int ret; 185 186 ret = regmap_write(priv->regmap, reg, val); 187 188 if (ret < 0) 189 dev_err(priv->dev, 190 "failed to write mt7530 register\n"); 191 192 return ret; 193 } 194 195 static u32 196 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 197 { 198 int ret; 199 u32 val; 200 201 ret = regmap_read(priv->regmap, reg, &val); 202 if (ret) { 203 WARN_ON_ONCE(1); 204 dev_err(priv->dev, 205 "failed to read mt7530 register\n"); 206 return 0; 207 } 208 209 return val; 210 } 211 212 static void 213 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 214 { 215 mt7530_mutex_lock(priv); 216 217 mt7530_mii_write(priv, reg, val); 218 219 mt7530_mutex_unlock(priv); 220 } 221 222 static u32 223 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 224 { 225 return mt7530_mii_read(p->priv, p->reg); 226 } 227 228 static u32 229 _mt7530_read(struct mt7530_dummy_poll *p) 230 { 231 u32 val; 232 233 mt7530_mutex_lock(p->priv); 234 235 val = mt7530_mii_read(p->priv, p->reg); 236 237 mt7530_mutex_unlock(p->priv); 238 239 return val; 240 } 241 242 static u32 243 mt7530_read(struct mt7530_priv *priv, u32 reg) 244 { 245 struct mt7530_dummy_poll p; 246 247 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 248 return _mt7530_read(&p); 249 } 250 251 static void 252 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 253 u32 mask, u32 set) 254 { 255 mt7530_mutex_lock(priv); 256 257 regmap_update_bits(priv->regmap, reg, mask, set); 258 259 mt7530_mutex_unlock(priv); 260 } 261 262 static void 263 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 264 { 265 mt7530_rmw(priv, reg, val, val); 266 } 267 268 static void 269 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 270 { 271 mt7530_rmw(priv, reg, val, 0); 272 } 273 274 static int 275 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 276 { 277 u32 val; 278 int ret; 279 struct mt7530_dummy_poll p; 280 281 /* Set the command operating upon the MAC address entries */ 282 val = ATC_BUSY | ATC_MAT(0) | cmd; 283 mt7530_write(priv, MT7530_ATC, val); 284 285 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 286 ret = readx_poll_timeout(_mt7530_read, &p, val, 287 !(val & ATC_BUSY), 20, 20000); 288 if (ret < 0) { 289 dev_err(priv->dev, "reset timeout\n"); 290 return ret; 291 } 292 293 /* Additional sanity for read command if the specified 294 * entry is invalid 295 */ 296 val = mt7530_read(priv, MT7530_ATC); 297 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 298 return -EINVAL; 299 300 if (rsp) 301 *rsp = val; 302 303 return 0; 304 } 305 306 static void 307 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 308 { 309 u32 reg[3]; 310 int i; 311 312 /* Read from ARL table into an array */ 313 for (i = 0; i < 3; i++) { 314 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 315 316 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 317 __func__, __LINE__, i, reg[i]); 318 } 319 320 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 321 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 322 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 323 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 324 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 325 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 326 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 327 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 328 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 329 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 330 } 331 332 static void 333 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 334 u8 port_mask, const u8 *mac, 335 u8 aging, u8 type) 336 { 337 u32 reg[3] = { 0 }; 338 int i; 339 340 reg[1] |= vid & CVID_MASK; 341 reg[1] |= ATA2_IVL; 342 reg[1] |= ATA2_FID(FID_BRIDGED); 343 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 344 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 345 /* STATIC_ENT indicate that entry is static wouldn't 346 * be aged out and STATIC_EMP specified as erasing an 347 * entry 348 */ 349 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 350 reg[1] |= mac[5] << MAC_BYTE_5; 351 reg[1] |= mac[4] << MAC_BYTE_4; 352 reg[0] |= mac[3] << MAC_BYTE_3; 353 reg[0] |= mac[2] << MAC_BYTE_2; 354 reg[0] |= mac[1] << MAC_BYTE_1; 355 reg[0] |= mac[0] << MAC_BYTE_0; 356 357 /* Write array into the ARL table */ 358 for (i = 0; i < 3; i++) 359 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 360 } 361 362 /* Set up switch core clock for MT7530 */ 363 static void mt7530_pll_setup(struct mt7530_priv *priv) 364 { 365 /* Disable core clock */ 366 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 367 368 /* Disable PLL */ 369 core_write(priv, CORE_GSWPLL_GRP1, 0); 370 371 /* Set core clock into 500Mhz */ 372 core_write(priv, CORE_GSWPLL_GRP2, 373 RG_GSWPLL_POSDIV_500M(1) | 374 RG_GSWPLL_FBKDIV_500M(25)); 375 376 /* Enable PLL */ 377 core_write(priv, CORE_GSWPLL_GRP1, 378 RG_GSWPLL_EN_PRE | 379 RG_GSWPLL_POSDIV_200M(2) | 380 RG_GSWPLL_FBKDIV_200M(32)); 381 382 udelay(20); 383 384 /* Enable core clock */ 385 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 386 } 387 388 /* If port 6 is available as a CPU port, always prefer that as the default, 389 * otherwise don't care. 390 */ 391 static struct dsa_port * 392 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 393 { 394 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 395 396 if (dsa_port_is_cpu(cpu_dp)) 397 return cpu_dp; 398 399 return NULL; 400 } 401 402 /* Setup port 6 interface mode and TRGMII TX circuit */ 403 static void 404 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 405 { 406 struct mt7530_priv *priv = ds->priv; 407 u32 ncpo1, ssc_delta, xtal; 408 409 /* Disable the MT7530 TRGMII clocks */ 410 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 411 412 if (interface == PHY_INTERFACE_MODE_RGMII) { 413 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 414 P6_INTF_MODE(0)); 415 return; 416 } 417 418 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 419 420 xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; 421 422 if (xtal == MT7530_XTAL_25MHZ) 423 ssc_delta = 0x57; 424 else 425 ssc_delta = 0x87; 426 427 if (priv->id == ID_MT7621) { 428 /* PLL frequency: 125MHz: 1.0GBit */ 429 if (xtal == MT7530_XTAL_40MHZ) 430 ncpo1 = 0x0640; 431 if (xtal == MT7530_XTAL_25MHZ) 432 ncpo1 = 0x0a00; 433 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 434 if (xtal == MT7530_XTAL_40MHZ) 435 ncpo1 = 0x0c80; 436 if (xtal == MT7530_XTAL_25MHZ) 437 ncpo1 = 0x1400; 438 } 439 440 /* Setup the MT7530 TRGMII Tx Clock */ 441 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 442 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 443 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 444 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 445 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 446 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 447 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 448 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 449 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 450 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 451 452 /* Enable the MT7530 TRGMII clocks */ 453 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 454 } 455 456 static void 457 mt7531_pll_setup(struct mt7530_priv *priv) 458 { 459 enum mt7531_xtal_fsel xtal; 460 u32 top_sig; 461 u32 hwstrap; 462 u32 val; 463 464 val = mt7530_read(priv, MT7531_CREV); 465 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 466 hwstrap = mt7530_read(priv, MT753X_TRAP); 467 if ((val & CHIP_REV_M) > 0) 468 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 469 MT7531_XTAL_FSEL_25MHZ; 470 else 471 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 472 MT7531_XTAL_FSEL_40MHZ; 473 474 /* Step 1 : Disable MT7531 COREPLL */ 475 val = mt7530_read(priv, MT7531_PLLGP_EN); 476 val &= ~EN_COREPLL; 477 mt7530_write(priv, MT7531_PLLGP_EN, val); 478 479 /* Step 2: switch to XTAL output */ 480 val = mt7530_read(priv, MT7531_PLLGP_EN); 481 val |= SW_CLKSW; 482 mt7530_write(priv, MT7531_PLLGP_EN, val); 483 484 val = mt7530_read(priv, MT7531_PLLGP_CR0); 485 val &= ~RG_COREPLL_EN; 486 mt7530_write(priv, MT7531_PLLGP_CR0, val); 487 488 /* Step 3: disable PLLGP and enable program PLLGP */ 489 val = mt7530_read(priv, MT7531_PLLGP_EN); 490 val |= SW_PLLGP; 491 mt7530_write(priv, MT7531_PLLGP_EN, val); 492 493 /* Step 4: program COREPLL output frequency to 500MHz */ 494 val = mt7530_read(priv, MT7531_PLLGP_CR0); 495 val &= ~RG_COREPLL_POSDIV_M; 496 val |= 2 << RG_COREPLL_POSDIV_S; 497 mt7530_write(priv, MT7531_PLLGP_CR0, val); 498 usleep_range(25, 35); 499 500 switch (xtal) { 501 case MT7531_XTAL_FSEL_25MHZ: 502 val = mt7530_read(priv, MT7531_PLLGP_CR0); 503 val &= ~RG_COREPLL_SDM_PCW_M; 504 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 505 mt7530_write(priv, MT7531_PLLGP_CR0, val); 506 break; 507 case MT7531_XTAL_FSEL_40MHZ: 508 val = mt7530_read(priv, MT7531_PLLGP_CR0); 509 val &= ~RG_COREPLL_SDM_PCW_M; 510 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 511 mt7530_write(priv, MT7531_PLLGP_CR0, val); 512 break; 513 } 514 515 /* Set feedback divide ratio update signal to high */ 516 val = mt7530_read(priv, MT7531_PLLGP_CR0); 517 val |= RG_COREPLL_SDM_PCW_CHG; 518 mt7530_write(priv, MT7531_PLLGP_CR0, val); 519 /* Wait for at least 16 XTAL clocks */ 520 usleep_range(10, 20); 521 522 /* Step 5: set feedback divide ratio update signal to low */ 523 val = mt7530_read(priv, MT7531_PLLGP_CR0); 524 val &= ~RG_COREPLL_SDM_PCW_CHG; 525 mt7530_write(priv, MT7531_PLLGP_CR0, val); 526 527 /* Enable 325M clock for SGMII */ 528 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 529 530 /* Enable 250SSC clock for RGMII */ 531 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 532 533 /* Step 6: Enable MT7531 PLL */ 534 val = mt7530_read(priv, MT7531_PLLGP_CR0); 535 val |= RG_COREPLL_EN; 536 mt7530_write(priv, MT7531_PLLGP_CR0, val); 537 538 val = mt7530_read(priv, MT7531_PLLGP_EN); 539 val |= EN_COREPLL; 540 mt7530_write(priv, MT7531_PLLGP_EN, val); 541 usleep_range(25, 35); 542 } 543 544 static void 545 mt7530_mib_reset(struct dsa_switch *ds) 546 { 547 struct mt7530_priv *priv = ds->priv; 548 549 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 550 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 551 } 552 553 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 554 { 555 return mdiobus_read_nested(priv->bus, port, regnum); 556 } 557 558 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 559 u16 val) 560 { 561 return mdiobus_write_nested(priv->bus, port, regnum, val); 562 } 563 564 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 565 int devad, int regnum) 566 { 567 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 568 } 569 570 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 571 int regnum, u16 val) 572 { 573 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 574 } 575 576 static int 577 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 578 int regnum) 579 { 580 struct mt7530_dummy_poll p; 581 u32 reg, val; 582 int ret; 583 584 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 585 586 mt7530_mutex_lock(priv); 587 588 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 589 !(val & MT7531_PHY_ACS_ST), 20, 100000); 590 if (ret < 0) { 591 dev_err(priv->dev, "poll timeout\n"); 592 goto out; 593 } 594 595 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 596 MT7531_MDIO_DEV_ADDR(devad) | regnum; 597 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 598 599 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 600 !(val & MT7531_PHY_ACS_ST), 20, 100000); 601 if (ret < 0) { 602 dev_err(priv->dev, "poll timeout\n"); 603 goto out; 604 } 605 606 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 607 MT7531_MDIO_DEV_ADDR(devad); 608 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 609 610 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 611 !(val & MT7531_PHY_ACS_ST), 20, 100000); 612 if (ret < 0) { 613 dev_err(priv->dev, "poll timeout\n"); 614 goto out; 615 } 616 617 ret = val & MT7531_MDIO_RW_DATA_MASK; 618 out: 619 mt7530_mutex_unlock(priv); 620 621 return ret; 622 } 623 624 static int 625 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 626 int regnum, u16 data) 627 { 628 struct mt7530_dummy_poll p; 629 u32 val, reg; 630 int ret; 631 632 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 633 634 mt7530_mutex_lock(priv); 635 636 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 637 !(val & MT7531_PHY_ACS_ST), 20, 100000); 638 if (ret < 0) { 639 dev_err(priv->dev, "poll timeout\n"); 640 goto out; 641 } 642 643 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 644 MT7531_MDIO_DEV_ADDR(devad) | regnum; 645 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 646 647 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 648 !(val & MT7531_PHY_ACS_ST), 20, 100000); 649 if (ret < 0) { 650 dev_err(priv->dev, "poll timeout\n"); 651 goto out; 652 } 653 654 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 655 MT7531_MDIO_DEV_ADDR(devad) | data; 656 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 657 658 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 659 !(val & MT7531_PHY_ACS_ST), 20, 100000); 660 if (ret < 0) { 661 dev_err(priv->dev, "poll timeout\n"); 662 goto out; 663 } 664 665 out: 666 mt7530_mutex_unlock(priv); 667 668 return ret; 669 } 670 671 static int 672 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 673 { 674 struct mt7530_dummy_poll p; 675 int ret; 676 u32 val; 677 678 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 679 680 mt7530_mutex_lock(priv); 681 682 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 683 !(val & MT7531_PHY_ACS_ST), 20, 100000); 684 if (ret < 0) { 685 dev_err(priv->dev, "poll timeout\n"); 686 goto out; 687 } 688 689 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 690 MT7531_MDIO_REG_ADDR(regnum); 691 692 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 693 694 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 695 !(val & MT7531_PHY_ACS_ST), 20, 100000); 696 if (ret < 0) { 697 dev_err(priv->dev, "poll timeout\n"); 698 goto out; 699 } 700 701 ret = val & MT7531_MDIO_RW_DATA_MASK; 702 out: 703 mt7530_mutex_unlock(priv); 704 705 return ret; 706 } 707 708 static int 709 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 710 u16 data) 711 { 712 struct mt7530_dummy_poll p; 713 int ret; 714 u32 reg; 715 716 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 717 718 mt7530_mutex_lock(priv); 719 720 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 721 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 722 if (ret < 0) { 723 dev_err(priv->dev, "poll timeout\n"); 724 goto out; 725 } 726 727 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 728 MT7531_MDIO_REG_ADDR(regnum) | data; 729 730 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 731 732 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 733 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 734 if (ret < 0) { 735 dev_err(priv->dev, "poll timeout\n"); 736 goto out; 737 } 738 739 out: 740 mt7530_mutex_unlock(priv); 741 742 return ret; 743 } 744 745 static int 746 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 747 { 748 struct mt7530_priv *priv = bus->priv; 749 750 return priv->info->phy_read_c22(priv, port, regnum); 751 } 752 753 static int 754 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 755 { 756 struct mt7530_priv *priv = bus->priv; 757 758 return priv->info->phy_read_c45(priv, port, devad, regnum); 759 } 760 761 static int 762 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 763 { 764 struct mt7530_priv *priv = bus->priv; 765 766 return priv->info->phy_write_c22(priv, port, regnum, val); 767 } 768 769 static int 770 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 771 u16 val) 772 { 773 struct mt7530_priv *priv = bus->priv; 774 775 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 776 } 777 778 static void 779 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 780 uint8_t *data) 781 { 782 int i; 783 784 if (stringset != ETH_SS_STATS) 785 return; 786 787 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 788 ethtool_puts(&data, mt7530_mib[i].name); 789 } 790 791 static void 792 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 793 uint64_t *data) 794 { 795 struct mt7530_priv *priv = ds->priv; 796 const struct mt7530_mib_desc *mib; 797 u32 reg, i; 798 u64 hi; 799 800 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 801 mib = &mt7530_mib[i]; 802 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 803 804 data[i] = mt7530_read(priv, reg); 805 if (mib->size == 2) { 806 hi = mt7530_read(priv, reg + 4); 807 data[i] |= hi << 32; 808 } 809 } 810 } 811 812 static int 813 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 814 { 815 if (sset != ETH_SS_STATS) 816 return 0; 817 818 return ARRAY_SIZE(mt7530_mib); 819 } 820 821 static int 822 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 823 { 824 struct mt7530_priv *priv = ds->priv; 825 unsigned int secs = msecs / 1000; 826 unsigned int tmp_age_count; 827 unsigned int error = -1; 828 unsigned int age_count; 829 unsigned int age_unit; 830 831 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 832 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 833 return -ERANGE; 834 835 /* iterate through all possible age_count to find the closest pair */ 836 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 837 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 838 839 if (tmp_age_unit <= AGE_UNIT_MAX) { 840 unsigned int tmp_error = secs - 841 (tmp_age_count + 1) * (tmp_age_unit + 1); 842 843 /* found a closer pair */ 844 if (error > tmp_error) { 845 error = tmp_error; 846 age_count = tmp_age_count; 847 age_unit = tmp_age_unit; 848 } 849 850 /* found the exact match, so break the loop */ 851 if (!error) 852 break; 853 } 854 } 855 856 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 857 858 return 0; 859 } 860 861 static const char *mt7530_p5_mode_str(unsigned int mode) 862 { 863 switch (mode) { 864 case MUX_PHY_P0: 865 return "MUX PHY P0"; 866 case MUX_PHY_P4: 867 return "MUX PHY P4"; 868 default: 869 return "GMAC5"; 870 } 871 } 872 873 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 874 { 875 struct mt7530_priv *priv = ds->priv; 876 u8 tx_delay = 0; 877 int val; 878 879 mutex_lock(&priv->reg_mutex); 880 881 val = mt7530_read(priv, MT753X_MTRAP); 882 883 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 884 885 switch (priv->p5_mode) { 886 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 887 case MUX_PHY_P0: 888 val |= MT7530_P5_PHY0_SEL; 889 fallthrough; 890 891 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 892 case MUX_PHY_P4: 893 /* Setup the MAC by default for the cpu port */ 894 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); 895 break; 896 897 /* GMAC5: P5 -> SoC MAC or external PHY */ 898 default: 899 val |= MT7530_P5_MAC_SEL; 900 break; 901 } 902 903 /* Setup RGMII settings */ 904 if (phy_interface_mode_is_rgmii(interface)) { 905 val |= MT7530_P5_RGMII_MODE; 906 907 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 908 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 909 910 /* Don't set delay in DSA mode */ 911 if (!dsa_is_dsa_port(priv->ds, 5) && 912 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 913 interface == PHY_INTERFACE_MODE_RGMII_ID)) 914 tx_delay = 4; /* n * 0.5 ns */ 915 916 /* P5 RGMII TX Clock Control: delay x */ 917 mt7530_write(priv, MT7530_P5RGMIITXCR, 918 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 919 920 /* reduce P5 RGMII Tx driving, 8mA */ 921 mt7530_write(priv, MT7530_IO_DRV_CR, 922 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 923 } 924 925 mt7530_write(priv, MT753X_MTRAP, val); 926 927 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 928 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 929 930 mutex_unlock(&priv->reg_mutex); 931 } 932 933 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 934 * of the Open Systems Interconnection basic reference model (OSI/RM) are 935 * described; the medium access control (MAC) and logical link control (LLC) 936 * sublayers. The MAC sublayer is the one facing the physical layer. 937 * 938 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 939 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 940 * of the Bridge, at least two Ports, and higher layer entities with at least a 941 * Spanning Tree Protocol Entity included. 942 * 943 * Each Bridge Port also functions as an end station and shall provide the MAC 944 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 945 * distinct LLC Entity that supports protocol identification, multiplexing, and 946 * demultiplexing, for protocol data unit (PDU) transmission and reception by 947 * one or more higher layer entities. 948 * 949 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 950 * Entity associated with each Bridge Port is modeled as being directly 951 * connected to the attached Local Area Network (LAN). 952 * 953 * On the switch with CPU port architecture, CPU port functions as Management 954 * Port, and the Management Port functionality is provided by software which 955 * functions as an end station. Software is connected to an IEEE 802 LAN that is 956 * wholly contained within the system that incorporates the Bridge. Software 957 * provides access to the LLC Entity associated with each Bridge Port by the 958 * value of the source port field on the special tag on the frame received by 959 * software. 960 * 961 * We call frames that carry control information to determine the active 962 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 963 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 964 * Protocol Data Units (MVRPDUs), and frames from other link constrained 965 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 966 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 967 * forwarded by a Bridge. Permanently configured entries in the filtering 968 * database (FDB) ensure that such frames are discarded by the Forwarding 969 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 970 * 971 * Each of the reserved MAC addresses specified in Table 8-1 972 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 973 * permanently configured in the FDB in C-VLAN components and ERs. 974 * 975 * Each of the reserved MAC addresses specified in Table 8-2 976 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 977 * configured in the FDB in S-VLAN components. 978 * 979 * Each of the reserved MAC addresses specified in Table 8-3 980 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 981 * TPMR components. 982 * 983 * The FDB entries for reserved MAC addresses shall specify filtering for all 984 * Bridge Ports and all VIDs. Management shall not provide the capability to 985 * modify or remove entries for reserved MAC addresses. 986 * 987 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 988 * propagation of PDUs within a Bridged Network, as follows: 989 * 990 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 991 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 992 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 993 * PDUs transmitted using this destination address, or any other addresses 994 * that appear in Table 8-1, Table 8-2, and Table 8-3 995 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 996 * therefore travel no further than those stations that can be reached via a 997 * single individual LAN from the originating station. 998 * 999 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1000 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1001 * Bridge can forward; however, this address is relayed by a TPMR component. 1002 * PDUs using this destination address, or any of the other addresses that 1003 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1004 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1005 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1006 * C-VLAN component, or MAC Bridge. 1007 * 1008 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1009 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1010 * relayed by TPMR components and S-VLAN components. PDUs using this 1011 * destination address, or any of the other addresses that appear in Table 8-1 1012 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1013 * will be relayed by TPMR components and S-VLAN components but will propagate 1014 * no further than the nearest C-VLAN component or MAC Bridge. 1015 * 1016 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1017 * port, we must not filter these frames but forward them to CPU port. 1018 * 1019 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1020 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1021 * For link-local frames, only CPU port should be designated as destination port 1022 * in the FDB, and the other functions of the Forwarding Process must not 1023 * interfere with the decision of the transmission Port. We call this process 1024 * trapping frames to CPU port. 1025 * 1026 * Therefore, on the switch with CPU port architecture, link-local frames must 1027 * be trapped to CPU port, and certain link-local frames received by a Port of a 1028 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1029 * from it. 1030 * 1031 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1032 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1033 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1034 * doesn't count) of this architecture will either function as a standard MAC 1035 * Bridge or a standard VLAN Bridge. 1036 * 1037 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1038 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1039 * we don't need to relay PDUs using the destination addresses specified on the 1040 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1041 * section where they must be relayed by TPMR components. 1042 * 1043 * One option to trap link-local frames to CPU port is to add static FDB entries 1044 * with CPU port designated as destination port. However, because that 1045 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1046 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1047 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1048 * entries. This switch intellectual property can only hold a maximum of 2048 1049 * entries. Using this option, there also isn't a mechanism to prevent 1050 * link-local frames from being discarded when the spanning tree Port State of 1051 * the reception Port is discarding. 1052 * 1053 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1054 * registers. Whilst this applies to every VID, it doesn't contain all of the 1055 * reserved MAC addresses without affecting the remaining Standard Group MAC 1056 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1057 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1058 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1059 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1060 * The latter option provides better but not complete conformance. 1061 * 1062 * This switch intellectual property also does not provide a mechanism to trap 1063 * link-local frames with specific destination addresses to CPU port by Bridge, 1064 * to conform to the filtering rules for the distinct Bridge components. 1065 * 1066 * Therefore, regardless of the type of the Bridge component, link-local frames 1067 * with these destination addresses will be trapped to CPU port: 1068 * 1069 * 01-80-C2-00-00-[00,01,02,03,0E] 1070 * 1071 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1072 * 1073 * Link-local frames with these destination addresses won't be trapped to CPU 1074 * port which won't conform to IEEE Std 802.1Q-2022: 1075 * 1076 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1077 * 1078 * In a Bridge comprising an S-VLAN component: 1079 * 1080 * Link-local frames with these destination addresses will be trapped to CPU 1081 * port which won't conform to IEEE Std 802.1Q-2022: 1082 * 1083 * 01-80-C2-00-00-00 1084 * 1085 * Link-local frames with these destination addresses won't be trapped to CPU 1086 * port which won't conform to IEEE Std 802.1Q-2022: 1087 * 1088 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1089 * 1090 * To trap link-local frames to CPU port as conformant as this switch 1091 * intellectual property can allow, link-local frames are made to be regarded as 1092 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1093 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1094 * State function of the Forwarding Process. 1095 * 1096 * The only remaining interference is the ingress rules. When the reception Port 1097 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1098 * There doesn't seem to be a mechanism on the switch intellectual property to 1099 * have link-local frames bypass this function of the Forwarding Process. 1100 */ 1101 static void 1102 mt753x_trap_frames(struct mt7530_priv *priv) 1103 { 1104 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them 1105 * VLAN-untagged. 1106 */ 1107 mt7530_rmw(priv, MT753X_BPC, 1108 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1109 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1110 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1111 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1112 BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1113 TO_CPU_FW_CPU_ONLY); 1114 1115 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress 1116 * them VLAN-untagged. 1117 */ 1118 mt7530_rmw(priv, MT753X_RGAC1, 1119 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1120 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1121 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1122 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1123 R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1124 TO_CPU_FW_CPU_ONLY); 1125 1126 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress 1127 * them VLAN-untagged. 1128 */ 1129 mt7530_rmw(priv, MT753X_RGAC2, 1130 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1131 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1132 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1133 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1134 R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1135 TO_CPU_FW_CPU_ONLY); 1136 } 1137 1138 static void 1139 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1140 { 1141 struct mt7530_priv *priv = ds->priv; 1142 1143 /* Enable Mediatek header mode on the cpu port */ 1144 mt7530_write(priv, MT7530_PVC_P(port), 1145 PORT_SPEC_TAG); 1146 1147 /* Enable flooding on the CPU port */ 1148 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1149 UNU_FFP(BIT(port))); 1150 1151 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1152 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1153 * is affine to the inbound user port. 1154 */ 1155 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 1156 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1157 1158 /* CPU port gets connected to all user ports of 1159 * the switch. 1160 */ 1161 mt7530_write(priv, MT7530_PCR_P(port), 1162 PCR_MATRIX(dsa_user_ports(priv->ds))); 1163 1164 /* Set to fallback mode for independent VLAN learning */ 1165 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1166 MT7530_PORT_FALLBACK_MODE); 1167 } 1168 1169 static int 1170 mt7530_port_enable(struct dsa_switch *ds, int port, 1171 struct phy_device *phy) 1172 { 1173 struct dsa_port *dp = dsa_to_port(ds, port); 1174 struct mt7530_priv *priv = ds->priv; 1175 1176 mutex_lock(&priv->reg_mutex); 1177 1178 /* Allow the user port gets connected to the cpu port and also 1179 * restore the port matrix if the port is the member of a certain 1180 * bridge. 1181 */ 1182 if (dsa_port_is_user(dp)) { 1183 struct dsa_port *cpu_dp = dp->cpu_dp; 1184 1185 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1186 } 1187 priv->ports[port].enable = true; 1188 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1189 priv->ports[port].pm); 1190 1191 mutex_unlock(&priv->reg_mutex); 1192 1193 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1194 return 0; 1195 1196 if (port == 5) 1197 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 1198 else if (port == 6) 1199 mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); 1200 1201 return 0; 1202 } 1203 1204 static void 1205 mt7530_port_disable(struct dsa_switch *ds, int port) 1206 { 1207 struct mt7530_priv *priv = ds->priv; 1208 1209 mutex_lock(&priv->reg_mutex); 1210 1211 /* Clear up all port matrix which could be restored in the next 1212 * enablement for the port. 1213 */ 1214 priv->ports[port].enable = false; 1215 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1216 PCR_MATRIX_CLR); 1217 1218 mutex_unlock(&priv->reg_mutex); 1219 1220 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1221 return; 1222 1223 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ 1224 if (port == 5 && priv->p5_mode == GMAC5) 1225 mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); 1226 else if (port == 6) 1227 mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); 1228 } 1229 1230 static int 1231 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1232 { 1233 struct mt7530_priv *priv = ds->priv; 1234 int length; 1235 u32 val; 1236 1237 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1238 * largest MTU of the user ports. Because the switch only has a global 1239 * RX length register, only allowing CPU port here is enough. 1240 */ 1241 if (!dsa_is_cpu_port(ds, port)) 1242 return 0; 1243 1244 mt7530_mutex_lock(priv); 1245 1246 val = mt7530_mii_read(priv, MT7530_GMACCR); 1247 val &= ~MAX_RX_PKT_LEN_MASK; 1248 1249 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1250 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1251 if (length <= 1522) { 1252 val |= MAX_RX_PKT_LEN_1522; 1253 } else if (length <= 1536) { 1254 val |= MAX_RX_PKT_LEN_1536; 1255 } else if (length <= 1552) { 1256 val |= MAX_RX_PKT_LEN_1552; 1257 } else { 1258 val &= ~MAX_RX_JUMBO_MASK; 1259 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1260 val |= MAX_RX_PKT_LEN_JUMBO; 1261 } 1262 1263 mt7530_mii_write(priv, MT7530_GMACCR, val); 1264 1265 mt7530_mutex_unlock(priv); 1266 1267 return 0; 1268 } 1269 1270 static int 1271 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1272 { 1273 return MT7530_MAX_MTU; 1274 } 1275 1276 static void 1277 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1278 { 1279 struct mt7530_priv *priv = ds->priv; 1280 u32 stp_state; 1281 1282 switch (state) { 1283 case BR_STATE_DISABLED: 1284 stp_state = MT7530_STP_DISABLED; 1285 break; 1286 case BR_STATE_BLOCKING: 1287 stp_state = MT7530_STP_BLOCKING; 1288 break; 1289 case BR_STATE_LISTENING: 1290 stp_state = MT7530_STP_LISTENING; 1291 break; 1292 case BR_STATE_LEARNING: 1293 stp_state = MT7530_STP_LEARNING; 1294 break; 1295 case BR_STATE_FORWARDING: 1296 default: 1297 stp_state = MT7530_STP_FORWARDING; 1298 break; 1299 } 1300 1301 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1302 FID_PST(FID_BRIDGED, stp_state)); 1303 } 1304 1305 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, 1306 const struct net_device *bridge_dev, 1307 bool join) __must_hold(&priv->reg_mutex) 1308 { 1309 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; 1310 struct mt7530_port *p = &priv->ports[port], *other_p; 1311 struct dsa_port *cpu_dp = dp->cpu_dp; 1312 u32 port_bitmap = BIT(cpu_dp->index); 1313 int other_port; 1314 bool isolated; 1315 1316 dsa_switch_for_each_user_port(other_dp, priv->ds) { 1317 other_port = other_dp->index; 1318 other_p = &priv->ports[other_port]; 1319 1320 if (dp == other_dp) 1321 continue; 1322 1323 /* Add/remove this port to/from the port matrix of the other 1324 * ports in the same bridge. If the port is disabled, port 1325 * matrix is kept and not being setup until the port becomes 1326 * enabled. 1327 */ 1328 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) 1329 continue; 1330 1331 isolated = p->isolated && other_p->isolated; 1332 1333 if (join && !isolated) { 1334 other_p->pm |= PCR_MATRIX(BIT(port)); 1335 port_bitmap |= BIT(other_port); 1336 } else { 1337 other_p->pm &= ~PCR_MATRIX(BIT(port)); 1338 } 1339 1340 if (other_p->enable) 1341 mt7530_rmw(priv, MT7530_PCR_P(other_port), 1342 PCR_MATRIX_MASK, other_p->pm); 1343 } 1344 1345 /* Add/remove the all other ports to this port matrix. For !join 1346 * (leaving the bridge), only the CPU port will remain in the port matrix 1347 * of this port. 1348 */ 1349 p->pm = PCR_MATRIX(port_bitmap); 1350 if (priv->ports[port].enable) 1351 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); 1352 } 1353 1354 static int 1355 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1356 struct switchdev_brport_flags flags, 1357 struct netlink_ext_ack *extack) 1358 { 1359 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1360 BR_BCAST_FLOOD | BR_ISOLATED)) 1361 return -EINVAL; 1362 1363 return 0; 1364 } 1365 1366 static int 1367 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1368 struct switchdev_brport_flags flags, 1369 struct netlink_ext_ack *extack) 1370 { 1371 struct mt7530_priv *priv = ds->priv; 1372 1373 if (flags.mask & BR_LEARNING) 1374 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1375 flags.val & BR_LEARNING ? 0 : SA_DIS); 1376 1377 if (flags.mask & BR_FLOOD) 1378 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), 1379 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1380 1381 if (flags.mask & BR_MCAST_FLOOD) 1382 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), 1383 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1384 1385 if (flags.mask & BR_BCAST_FLOOD) 1386 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), 1387 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1388 1389 if (flags.mask & BR_ISOLATED) { 1390 struct dsa_port *dp = dsa_to_port(ds, port); 1391 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); 1392 1393 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); 1394 1395 mutex_lock(&priv->reg_mutex); 1396 mt7530_update_port_member(priv, port, bridge_dev, true); 1397 mutex_unlock(&priv->reg_mutex); 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int 1404 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1405 struct dsa_bridge bridge, bool *tx_fwd_offload, 1406 struct netlink_ext_ack *extack) 1407 { 1408 struct mt7530_priv *priv = ds->priv; 1409 1410 mutex_lock(&priv->reg_mutex); 1411 1412 mt7530_update_port_member(priv, port, bridge.dev, true); 1413 1414 /* Set to fallback mode for independent VLAN learning */ 1415 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1416 MT7530_PORT_FALLBACK_MODE); 1417 1418 mutex_unlock(&priv->reg_mutex); 1419 1420 return 0; 1421 } 1422 1423 static void 1424 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1425 { 1426 struct mt7530_priv *priv = ds->priv; 1427 bool all_user_ports_removed = true; 1428 int i; 1429 1430 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1431 * bridge. Don't set standalone ports to fallback mode. 1432 */ 1433 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1434 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1435 MT7530_PORT_FALLBACK_MODE); 1436 1437 mt7530_rmw(priv, MT7530_PVC_P(port), 1438 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1439 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1440 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1441 MT7530_VLAN_ACC_ALL); 1442 1443 /* Set PVID to 0 */ 1444 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1445 G0_PORT_VID_DEF); 1446 1447 for (i = 0; i < priv->ds->num_ports; i++) { 1448 if (dsa_is_user_port(ds, i) && 1449 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1450 all_user_ports_removed = false; 1451 break; 1452 } 1453 } 1454 1455 /* CPU port also does the same thing until all user ports belonging to 1456 * the CPU port get out of VLAN filtering mode. 1457 */ 1458 if (all_user_ports_removed) { 1459 struct dsa_port *dp = dsa_to_port(ds, port); 1460 struct dsa_port *cpu_dp = dp->cpu_dp; 1461 1462 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1463 PCR_MATRIX(dsa_user_ports(priv->ds))); 1464 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1465 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1466 } 1467 } 1468 1469 static void 1470 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1471 { 1472 struct mt7530_priv *priv = ds->priv; 1473 1474 /* Trapped into security mode allows packet forwarding through VLAN 1475 * table lookup. 1476 */ 1477 if (dsa_is_user_port(ds, port)) { 1478 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1479 MT7530_PORT_SECURITY_MODE); 1480 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1481 G0_PORT_VID(priv->ports[port].pvid)); 1482 1483 /* Only accept tagged frames if PVID is not set */ 1484 if (!priv->ports[port].pvid) 1485 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1486 MT7530_VLAN_ACC_TAGGED); 1487 1488 /* Set the port as a user port which is to be able to recognize 1489 * VID from incoming packets before fetching entry within the 1490 * VLAN table. 1491 */ 1492 mt7530_rmw(priv, MT7530_PVC_P(port), 1493 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1494 VLAN_ATTR(MT7530_VLAN_USER) | 1495 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1496 } else { 1497 /* Also set CPU ports to the "user" VLAN port attribute, to 1498 * allow VLAN classification, but keep the EG_TAG attribute as 1499 * "consistent" (i.o.w. don't change its value) for packets 1500 * received by the switch from the CPU, so that tagged packets 1501 * are forwarded to user ports as tagged, and untagged as 1502 * untagged. 1503 */ 1504 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1505 VLAN_ATTR(MT7530_VLAN_USER)); 1506 } 1507 } 1508 1509 static void 1510 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1511 struct dsa_bridge bridge) 1512 { 1513 struct mt7530_priv *priv = ds->priv; 1514 1515 mutex_lock(&priv->reg_mutex); 1516 1517 mt7530_update_port_member(priv, port, bridge.dev, false); 1518 1519 /* When a port is removed from the bridge, the port would be set up 1520 * back to the default as is at initial boot which is a VLAN-unaware 1521 * port. 1522 */ 1523 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1524 MT7530_PORT_MATRIX_MODE); 1525 1526 mutex_unlock(&priv->reg_mutex); 1527 } 1528 1529 static int 1530 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1531 const unsigned char *addr, u16 vid, 1532 struct dsa_db db) 1533 { 1534 struct mt7530_priv *priv = ds->priv; 1535 int ret; 1536 u8 port_mask = BIT(port); 1537 1538 mutex_lock(&priv->reg_mutex); 1539 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1540 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1541 mutex_unlock(&priv->reg_mutex); 1542 1543 return ret; 1544 } 1545 1546 static int 1547 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1548 const unsigned char *addr, u16 vid, 1549 struct dsa_db db) 1550 { 1551 struct mt7530_priv *priv = ds->priv; 1552 int ret; 1553 u8 port_mask = BIT(port); 1554 1555 mutex_lock(&priv->reg_mutex); 1556 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1557 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1558 mutex_unlock(&priv->reg_mutex); 1559 1560 return ret; 1561 } 1562 1563 static int 1564 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1565 dsa_fdb_dump_cb_t *cb, void *data) 1566 { 1567 struct mt7530_priv *priv = ds->priv; 1568 struct mt7530_fdb _fdb = { 0 }; 1569 int cnt = MT7530_NUM_FDB_RECORDS; 1570 int ret = 0; 1571 u32 rsp = 0; 1572 1573 mutex_lock(&priv->reg_mutex); 1574 1575 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1576 if (ret < 0) 1577 goto err; 1578 1579 do { 1580 if (rsp & ATC_SRCH_HIT) { 1581 mt7530_fdb_read(priv, &_fdb); 1582 if (_fdb.port_mask & BIT(port)) { 1583 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1584 data); 1585 if (ret < 0) 1586 break; 1587 } 1588 } 1589 } while (--cnt && 1590 !(rsp & ATC_SRCH_END) && 1591 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1592 err: 1593 mutex_unlock(&priv->reg_mutex); 1594 1595 return 0; 1596 } 1597 1598 static int 1599 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1600 const struct switchdev_obj_port_mdb *mdb, 1601 struct dsa_db db) 1602 { 1603 struct mt7530_priv *priv = ds->priv; 1604 const u8 *addr = mdb->addr; 1605 u16 vid = mdb->vid; 1606 u8 port_mask = 0; 1607 int ret; 1608 1609 mutex_lock(&priv->reg_mutex); 1610 1611 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1612 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1613 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1614 & PORT_MAP_MASK; 1615 1616 port_mask |= BIT(port); 1617 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1618 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1619 1620 mutex_unlock(&priv->reg_mutex); 1621 1622 return ret; 1623 } 1624 1625 static int 1626 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1627 const struct switchdev_obj_port_mdb *mdb, 1628 struct dsa_db db) 1629 { 1630 struct mt7530_priv *priv = ds->priv; 1631 const u8 *addr = mdb->addr; 1632 u16 vid = mdb->vid; 1633 u8 port_mask = 0; 1634 int ret; 1635 1636 mutex_lock(&priv->reg_mutex); 1637 1638 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1639 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1640 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1641 & PORT_MAP_MASK; 1642 1643 port_mask &= ~BIT(port); 1644 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1645 port_mask ? STATIC_ENT : STATIC_EMP); 1646 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1647 1648 mutex_unlock(&priv->reg_mutex); 1649 1650 return ret; 1651 } 1652 1653 static int 1654 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1655 { 1656 struct mt7530_dummy_poll p; 1657 u32 val; 1658 int ret; 1659 1660 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1661 mt7530_write(priv, MT7530_VTCR, val); 1662 1663 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1664 ret = readx_poll_timeout(_mt7530_read, &p, val, 1665 !(val & VTCR_BUSY), 20, 20000); 1666 if (ret < 0) { 1667 dev_err(priv->dev, "poll timeout\n"); 1668 return ret; 1669 } 1670 1671 val = mt7530_read(priv, MT7530_VTCR); 1672 if (val & VTCR_INVALID) { 1673 dev_err(priv->dev, "read VTCR invalid\n"); 1674 return -EINVAL; 1675 } 1676 1677 return 0; 1678 } 1679 1680 static int 1681 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1682 struct netlink_ext_ack *extack) 1683 { 1684 struct dsa_port *dp = dsa_to_port(ds, port); 1685 struct dsa_port *cpu_dp = dp->cpu_dp; 1686 1687 if (vlan_filtering) { 1688 /* The port is being kept as VLAN-unaware port when bridge is 1689 * set up with vlan_filtering not being set, Otherwise, the 1690 * port and the corresponding CPU port is required the setup 1691 * for becoming a VLAN-aware port. 1692 */ 1693 mt7530_port_set_vlan_aware(ds, port); 1694 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1695 } else { 1696 mt7530_port_set_vlan_unaware(ds, port); 1697 } 1698 1699 return 0; 1700 } 1701 1702 static void 1703 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1704 struct mt7530_hw_vlan_entry *entry) 1705 { 1706 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1707 u8 new_members; 1708 u32 val; 1709 1710 new_members = entry->old_members | BIT(entry->port); 1711 1712 /* Validate the entry with independent learning, create egress tag per 1713 * VLAN and joining the port as one of the port members. 1714 */ 1715 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1716 VLAN_VALID; 1717 mt7530_write(priv, MT7530_VAWD1, val); 1718 1719 /* Decide whether adding tag or not for those outgoing packets from the 1720 * port inside the VLAN. 1721 * CPU port is always taken as a tagged port for serving more than one 1722 * VLANs across and also being applied with egress type stack mode for 1723 * that VLAN tags would be appended after hardware special tag used as 1724 * DSA tag. 1725 */ 1726 if (dsa_port_is_cpu(dp)) 1727 val = MT7530_VLAN_EGRESS_STACK; 1728 else if (entry->untagged) 1729 val = MT7530_VLAN_EGRESS_UNTAG; 1730 else 1731 val = MT7530_VLAN_EGRESS_TAG; 1732 mt7530_rmw(priv, MT7530_VAWD2, 1733 ETAG_CTRL_P_MASK(entry->port), 1734 ETAG_CTRL_P(entry->port, val)); 1735 } 1736 1737 static void 1738 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1739 struct mt7530_hw_vlan_entry *entry) 1740 { 1741 u8 new_members; 1742 u32 val; 1743 1744 new_members = entry->old_members & ~BIT(entry->port); 1745 1746 val = mt7530_read(priv, MT7530_VAWD1); 1747 if (!(val & VLAN_VALID)) { 1748 dev_err(priv->dev, 1749 "Cannot be deleted due to invalid entry\n"); 1750 return; 1751 } 1752 1753 if (new_members) { 1754 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1755 VLAN_VALID; 1756 mt7530_write(priv, MT7530_VAWD1, val); 1757 } else { 1758 mt7530_write(priv, MT7530_VAWD1, 0); 1759 mt7530_write(priv, MT7530_VAWD2, 0); 1760 } 1761 } 1762 1763 static void 1764 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1765 struct mt7530_hw_vlan_entry *entry, 1766 mt7530_vlan_op vlan_op) 1767 { 1768 u32 val; 1769 1770 /* Fetch entry */ 1771 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1772 1773 val = mt7530_read(priv, MT7530_VAWD1); 1774 1775 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1776 1777 /* Manipulate entry */ 1778 vlan_op(priv, entry); 1779 1780 /* Flush result to hardware */ 1781 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1782 } 1783 1784 static int 1785 mt7530_setup_vlan0(struct mt7530_priv *priv) 1786 { 1787 u32 val; 1788 1789 /* Validate the entry with independent learning, keep the original 1790 * ingress tag attribute. 1791 */ 1792 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1793 VLAN_VALID; 1794 mt7530_write(priv, MT7530_VAWD1, val); 1795 1796 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1797 } 1798 1799 static int 1800 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1801 const struct switchdev_obj_port_vlan *vlan, 1802 struct netlink_ext_ack *extack) 1803 { 1804 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1805 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1806 struct mt7530_hw_vlan_entry new_entry; 1807 struct mt7530_priv *priv = ds->priv; 1808 1809 mutex_lock(&priv->reg_mutex); 1810 1811 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1812 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1813 1814 if (pvid) { 1815 priv->ports[port].pvid = vlan->vid; 1816 1817 /* Accept all frames if PVID is set */ 1818 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1819 MT7530_VLAN_ACC_ALL); 1820 1821 /* Only configure PVID if VLAN filtering is enabled */ 1822 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1823 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1824 G0_PORT_VID_MASK, 1825 G0_PORT_VID(vlan->vid)); 1826 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1827 /* This VLAN is overwritten without PVID, so unset it */ 1828 priv->ports[port].pvid = G0_PORT_VID_DEF; 1829 1830 /* Only accept tagged frames if the port is VLAN-aware */ 1831 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1832 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1833 MT7530_VLAN_ACC_TAGGED); 1834 1835 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1836 G0_PORT_VID_DEF); 1837 } 1838 1839 mutex_unlock(&priv->reg_mutex); 1840 1841 return 0; 1842 } 1843 1844 static int 1845 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1846 const struct switchdev_obj_port_vlan *vlan) 1847 { 1848 struct mt7530_hw_vlan_entry target_entry; 1849 struct mt7530_priv *priv = ds->priv; 1850 1851 mutex_lock(&priv->reg_mutex); 1852 1853 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1854 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1855 mt7530_hw_vlan_del); 1856 1857 /* PVID is being restored to the default whenever the PVID port 1858 * is being removed from the VLAN. 1859 */ 1860 if (priv->ports[port].pvid == vlan->vid) { 1861 priv->ports[port].pvid = G0_PORT_VID_DEF; 1862 1863 /* Only accept tagged frames if the port is VLAN-aware */ 1864 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1865 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1866 MT7530_VLAN_ACC_TAGGED); 1867 1868 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1869 G0_PORT_VID_DEF); 1870 } 1871 1872 1873 mutex_unlock(&priv->reg_mutex); 1874 1875 return 0; 1876 } 1877 1878 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1879 struct dsa_mall_mirror_tc_entry *mirror, 1880 bool ingress, struct netlink_ext_ack *extack) 1881 { 1882 struct mt7530_priv *priv = ds->priv; 1883 int monitor_port; 1884 u32 val; 1885 1886 /* Check for existent entry */ 1887 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1888 return -EEXIST; 1889 1890 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1891 1892 /* MT7530 only supports one monitor port */ 1893 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 1894 if (val & MT753X_MIRROR_EN(priv->id) && 1895 monitor_port != mirror->to_local_port) 1896 return -EEXIST; 1897 1898 val |= MT753X_MIRROR_EN(priv->id); 1899 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 1900 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 1901 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1902 1903 val = mt7530_read(priv, MT7530_PCR_P(port)); 1904 if (ingress) { 1905 val |= PORT_RX_MIR; 1906 priv->mirror_rx |= BIT(port); 1907 } else { 1908 val |= PORT_TX_MIR; 1909 priv->mirror_tx |= BIT(port); 1910 } 1911 mt7530_write(priv, MT7530_PCR_P(port), val); 1912 1913 return 0; 1914 } 1915 1916 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1917 struct dsa_mall_mirror_tc_entry *mirror) 1918 { 1919 struct mt7530_priv *priv = ds->priv; 1920 u32 val; 1921 1922 val = mt7530_read(priv, MT7530_PCR_P(port)); 1923 if (mirror->ingress) { 1924 val &= ~PORT_RX_MIR; 1925 priv->mirror_rx &= ~BIT(port); 1926 } else { 1927 val &= ~PORT_TX_MIR; 1928 priv->mirror_tx &= ~BIT(port); 1929 } 1930 mt7530_write(priv, MT7530_PCR_P(port), val); 1931 1932 if (!priv->mirror_rx && !priv->mirror_tx) { 1933 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1934 val &= ~MT753X_MIRROR_EN(priv->id); 1935 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1936 } 1937 } 1938 1939 static enum dsa_tag_protocol 1940 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1941 enum dsa_tag_protocol mp) 1942 { 1943 return DSA_TAG_PROTO_MTK; 1944 } 1945 1946 #ifdef CONFIG_GPIOLIB 1947 static inline u32 1948 mt7530_gpio_to_bit(unsigned int offset) 1949 { 1950 /* Map GPIO offset to register bit 1951 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1952 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1953 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1954 * [14:12] port 3 LED 0..2 as GPIO 9..11 1955 * [18:16] port 4 LED 0..2 as GPIO 12..14 1956 */ 1957 return BIT(offset + offset / 3); 1958 } 1959 1960 static int 1961 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1962 { 1963 struct mt7530_priv *priv = gpiochip_get_data(gc); 1964 u32 bit = mt7530_gpio_to_bit(offset); 1965 1966 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1967 } 1968 1969 static void 1970 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1971 { 1972 struct mt7530_priv *priv = gpiochip_get_data(gc); 1973 u32 bit = mt7530_gpio_to_bit(offset); 1974 1975 if (value) 1976 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1977 else 1978 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1979 } 1980 1981 static int 1982 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1983 { 1984 struct mt7530_priv *priv = gpiochip_get_data(gc); 1985 u32 bit = mt7530_gpio_to_bit(offset); 1986 1987 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1988 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1989 } 1990 1991 static int 1992 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1993 { 1994 struct mt7530_priv *priv = gpiochip_get_data(gc); 1995 u32 bit = mt7530_gpio_to_bit(offset); 1996 1997 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1998 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1999 2000 return 0; 2001 } 2002 2003 static int 2004 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2005 { 2006 struct mt7530_priv *priv = gpiochip_get_data(gc); 2007 u32 bit = mt7530_gpio_to_bit(offset); 2008 2009 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2010 2011 if (value) 2012 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2013 else 2014 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2015 2016 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2017 2018 return 0; 2019 } 2020 2021 static int 2022 mt7530_setup_gpio(struct mt7530_priv *priv) 2023 { 2024 struct device *dev = priv->dev; 2025 struct gpio_chip *gc; 2026 2027 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2028 if (!gc) 2029 return -ENOMEM; 2030 2031 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2032 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2033 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2034 2035 gc->label = "mt7530"; 2036 gc->parent = dev; 2037 gc->owner = THIS_MODULE; 2038 gc->get_direction = mt7530_gpio_get_direction; 2039 gc->direction_input = mt7530_gpio_direction_input; 2040 gc->direction_output = mt7530_gpio_direction_output; 2041 gc->get = mt7530_gpio_get; 2042 gc->set = mt7530_gpio_set; 2043 gc->base = -1; 2044 gc->ngpio = 15; 2045 gc->can_sleep = true; 2046 2047 return devm_gpiochip_add_data(dev, gc, priv); 2048 } 2049 #endif /* CONFIG_GPIOLIB */ 2050 2051 static irqreturn_t 2052 mt7530_irq_thread_fn(int irq, void *dev_id) 2053 { 2054 struct mt7530_priv *priv = dev_id; 2055 bool handled = false; 2056 u32 val; 2057 int p; 2058 2059 mt7530_mutex_lock(priv); 2060 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 2061 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 2062 mt7530_mutex_unlock(priv); 2063 2064 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2065 if (BIT(p) & val) { 2066 unsigned int irq; 2067 2068 irq = irq_find_mapping(priv->irq_domain, p); 2069 handle_nested_irq(irq); 2070 handled = true; 2071 } 2072 } 2073 2074 return IRQ_RETVAL(handled); 2075 } 2076 2077 static void 2078 mt7530_irq_mask(struct irq_data *d) 2079 { 2080 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2081 2082 priv->irq_enable &= ~BIT(d->hwirq); 2083 } 2084 2085 static void 2086 mt7530_irq_unmask(struct irq_data *d) 2087 { 2088 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2089 2090 priv->irq_enable |= BIT(d->hwirq); 2091 } 2092 2093 static void 2094 mt7530_irq_bus_lock(struct irq_data *d) 2095 { 2096 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2097 2098 mt7530_mutex_lock(priv); 2099 } 2100 2101 static void 2102 mt7530_irq_bus_sync_unlock(struct irq_data *d) 2103 { 2104 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2105 2106 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2107 mt7530_mutex_unlock(priv); 2108 } 2109 2110 static struct irq_chip mt7530_irq_chip = { 2111 .name = KBUILD_MODNAME, 2112 .irq_mask = mt7530_irq_mask, 2113 .irq_unmask = mt7530_irq_unmask, 2114 .irq_bus_lock = mt7530_irq_bus_lock, 2115 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 2116 }; 2117 2118 static int 2119 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 2120 irq_hw_number_t hwirq) 2121 { 2122 irq_set_chip_data(irq, domain->host_data); 2123 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 2124 irq_set_nested_thread(irq, true); 2125 irq_set_noprobe(irq); 2126 2127 return 0; 2128 } 2129 2130 static const struct irq_domain_ops mt7530_irq_domain_ops = { 2131 .map = mt7530_irq_map, 2132 .xlate = irq_domain_xlate_onecell, 2133 }; 2134 2135 static void 2136 mt7988_irq_mask(struct irq_data *d) 2137 { 2138 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2139 2140 priv->irq_enable &= ~BIT(d->hwirq); 2141 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2142 } 2143 2144 static void 2145 mt7988_irq_unmask(struct irq_data *d) 2146 { 2147 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2148 2149 priv->irq_enable |= BIT(d->hwirq); 2150 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2151 } 2152 2153 static struct irq_chip mt7988_irq_chip = { 2154 .name = KBUILD_MODNAME, 2155 .irq_mask = mt7988_irq_mask, 2156 .irq_unmask = mt7988_irq_unmask, 2157 }; 2158 2159 static int 2160 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2161 irq_hw_number_t hwirq) 2162 { 2163 irq_set_chip_data(irq, domain->host_data); 2164 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2165 irq_set_nested_thread(irq, true); 2166 irq_set_noprobe(irq); 2167 2168 return 0; 2169 } 2170 2171 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2172 .map = mt7988_irq_map, 2173 .xlate = irq_domain_xlate_onecell, 2174 }; 2175 2176 static void 2177 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2178 { 2179 struct dsa_switch *ds = priv->ds; 2180 int p; 2181 2182 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2183 if (BIT(p) & ds->phys_mii_mask) { 2184 unsigned int irq; 2185 2186 irq = irq_create_mapping(priv->irq_domain, p); 2187 ds->user_mii_bus->irq[p] = irq; 2188 } 2189 } 2190 } 2191 2192 static int 2193 mt7530_setup_irq(struct mt7530_priv *priv) 2194 { 2195 struct device *dev = priv->dev; 2196 struct device_node *np = dev->of_node; 2197 int ret; 2198 2199 if (!of_property_read_bool(np, "interrupt-controller")) { 2200 dev_info(dev, "no interrupt support\n"); 2201 return 0; 2202 } 2203 2204 priv->irq = of_irq_get(np, 0); 2205 if (priv->irq <= 0) { 2206 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2207 return priv->irq ? : -EINVAL; 2208 } 2209 2210 if (priv->id == ID_MT7988) 2211 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2212 &mt7988_irq_domain_ops, 2213 priv); 2214 else 2215 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2216 &mt7530_irq_domain_ops, 2217 priv); 2218 2219 if (!priv->irq_domain) { 2220 dev_err(dev, "failed to create IRQ domain\n"); 2221 return -ENOMEM; 2222 } 2223 2224 /* This register must be set for MT7530 to properly fire interrupts */ 2225 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2226 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2227 2228 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2229 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2230 if (ret) { 2231 irq_domain_remove(priv->irq_domain); 2232 dev_err(dev, "failed to request IRQ: %d\n", ret); 2233 return ret; 2234 } 2235 2236 return 0; 2237 } 2238 2239 static void 2240 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2241 { 2242 int p; 2243 2244 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2245 if (BIT(p) & priv->ds->phys_mii_mask) { 2246 unsigned int irq; 2247 2248 irq = irq_find_mapping(priv->irq_domain, p); 2249 irq_dispose_mapping(irq); 2250 } 2251 } 2252 } 2253 2254 static void 2255 mt7530_free_irq_common(struct mt7530_priv *priv) 2256 { 2257 free_irq(priv->irq, priv); 2258 irq_domain_remove(priv->irq_domain); 2259 } 2260 2261 static void 2262 mt7530_free_irq(struct mt7530_priv *priv) 2263 { 2264 struct device_node *mnp, *np = priv->dev->of_node; 2265 2266 mnp = of_get_child_by_name(np, "mdio"); 2267 if (!mnp) 2268 mt7530_free_mdio_irq(priv); 2269 of_node_put(mnp); 2270 2271 mt7530_free_irq_common(priv); 2272 } 2273 2274 static int 2275 mt7530_setup_mdio(struct mt7530_priv *priv) 2276 { 2277 struct device_node *mnp, *np = priv->dev->of_node; 2278 struct dsa_switch *ds = priv->ds; 2279 struct device *dev = priv->dev; 2280 struct mii_bus *bus; 2281 static int idx; 2282 int ret = 0; 2283 2284 mnp = of_get_child_by_name(np, "mdio"); 2285 2286 if (mnp && !of_device_is_available(mnp)) 2287 goto out; 2288 2289 bus = devm_mdiobus_alloc(dev); 2290 if (!bus) { 2291 ret = -ENOMEM; 2292 goto out; 2293 } 2294 2295 if (!mnp) 2296 ds->user_mii_bus = bus; 2297 2298 bus->priv = priv; 2299 bus->name = KBUILD_MODNAME "-mii"; 2300 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2301 bus->read = mt753x_phy_read_c22; 2302 bus->write = mt753x_phy_write_c22; 2303 bus->read_c45 = mt753x_phy_read_c45; 2304 bus->write_c45 = mt753x_phy_write_c45; 2305 bus->parent = dev; 2306 bus->phy_mask = ~ds->phys_mii_mask; 2307 2308 if (priv->irq && !mnp) 2309 mt7530_setup_mdio_irq(priv); 2310 2311 ret = devm_of_mdiobus_register(dev, bus, mnp); 2312 if (ret) { 2313 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2314 if (priv->irq && !mnp) 2315 mt7530_free_mdio_irq(priv); 2316 } 2317 2318 out: 2319 of_node_put(mnp); 2320 return ret; 2321 } 2322 2323 static int 2324 mt7530_setup(struct dsa_switch *ds) 2325 { 2326 struct mt7530_priv *priv = ds->priv; 2327 struct device_node *dn = NULL; 2328 struct device_node *phy_node; 2329 struct device_node *mac_np; 2330 struct mt7530_dummy_poll p; 2331 phy_interface_t interface; 2332 struct dsa_port *cpu_dp; 2333 u32 id, val; 2334 int ret, i; 2335 2336 /* The parent node of conduit netdev which holds the common system 2337 * controller also is the container for two GMACs nodes representing 2338 * as two netdev instances. 2339 */ 2340 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2341 dn = cpu_dp->conduit->dev.of_node->parent; 2342 /* It doesn't matter which CPU port is found first, 2343 * their conduits should share the same parent OF node 2344 */ 2345 break; 2346 } 2347 2348 if (!dn) { 2349 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2350 return -EINVAL; 2351 } 2352 2353 ds->assisted_learning_on_cpu_port = true; 2354 ds->mtu_enforcement_ingress = true; 2355 2356 if (priv->id == ID_MT7530) { 2357 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2358 ret = regulator_enable(priv->core_pwr); 2359 if (ret < 0) { 2360 dev_err(priv->dev, 2361 "Failed to enable core power: %d\n", ret); 2362 return ret; 2363 } 2364 2365 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2366 ret = regulator_enable(priv->io_pwr); 2367 if (ret < 0) { 2368 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2369 ret); 2370 return ret; 2371 } 2372 } 2373 2374 /* Reset whole chip through gpio pin or memory-mapped registers for 2375 * different type of hardware 2376 */ 2377 if (priv->mcm) { 2378 reset_control_assert(priv->rstc); 2379 usleep_range(5000, 5100); 2380 reset_control_deassert(priv->rstc); 2381 } else { 2382 gpiod_set_value_cansleep(priv->reset, 0); 2383 usleep_range(5000, 5100); 2384 gpiod_set_value_cansleep(priv->reset, 1); 2385 } 2386 2387 /* Waiting for MT7530 got to stable */ 2388 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2389 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2390 20, 1000000); 2391 if (ret < 0) { 2392 dev_err(priv->dev, "reset timeout\n"); 2393 return ret; 2394 } 2395 2396 id = mt7530_read(priv, MT7530_CREV); 2397 id >>= CHIP_NAME_SHIFT; 2398 if (id != MT7530_ID) { 2399 dev_err(priv->dev, "chip %x can't be supported\n", id); 2400 return -ENODEV; 2401 } 2402 2403 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2404 dev_err(priv->dev, 2405 "MT7530 with a 20MHz XTAL is not supported!\n"); 2406 return -EINVAL; 2407 } 2408 2409 /* Reset the switch through internal reset */ 2410 mt7530_write(priv, MT7530_SYS_CTRL, 2411 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2412 SYS_CTRL_REG_RST); 2413 2414 /* Lower Tx driving for TRGMII path */ 2415 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2416 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2417 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2418 2419 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2420 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2421 RD_TAP_MASK, RD_TAP(16)); 2422 2423 /* Allow modifying the trap and directly access PHY registers via the 2424 * MDIO bus the switch is on. 2425 */ 2426 mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | 2427 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); 2428 2429 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2430 mt7530_pll_setup(priv); 2431 2432 mt753x_trap_frames(priv); 2433 2434 /* Enable and reset MIB counters */ 2435 mt7530_mib_reset(ds); 2436 2437 for (i = 0; i < priv->ds->num_ports; i++) { 2438 /* Clear link settings and enable force mode to force link down 2439 * on all ports until they're enabled later. 2440 */ 2441 mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | 2442 MT7530_FORCE_MODE, MT7530_FORCE_MODE); 2443 2444 /* Disable forwarding by default on all ports */ 2445 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2446 PCR_MATRIX_CLR); 2447 2448 /* Disable learning by default on all ports */ 2449 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2450 2451 if (dsa_is_cpu_port(ds, i)) { 2452 mt753x_cpu_port_enable(ds, i); 2453 } else { 2454 mt7530_port_disable(ds, i); 2455 2456 /* Set default PVID to 0 on all user ports */ 2457 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2458 G0_PORT_VID_DEF); 2459 } 2460 /* Enable consistent egress tag */ 2461 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2462 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2463 } 2464 2465 /* Allow mirroring frames received on the local port (monitor port). */ 2466 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2467 2468 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2469 ret = mt7530_setup_vlan0(priv); 2470 if (ret) 2471 return ret; 2472 2473 /* Check for PHY muxing on port 5 */ 2474 if (dsa_is_unused_port(ds, 5)) { 2475 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2476 * Set priv->p5_mode to the appropriate value if PHY muxing is 2477 * detected. 2478 */ 2479 for_each_child_of_node(dn, mac_np) { 2480 if (!of_device_is_compatible(mac_np, 2481 "mediatek,eth-mac")) 2482 continue; 2483 2484 ret = of_property_read_u32(mac_np, "reg", &id); 2485 if (ret < 0 || id != 1) 2486 continue; 2487 2488 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2489 if (!phy_node) 2490 continue; 2491 2492 if (phy_node->parent == priv->dev->of_node->parent || 2493 phy_node->parent->parent == priv->dev->of_node) { 2494 ret = of_get_phy_mode(mac_np, &interface); 2495 if (ret && ret != -ENODEV) { 2496 of_node_put(mac_np); 2497 of_node_put(phy_node); 2498 return ret; 2499 } 2500 id = of_mdio_parse_addr(ds->dev, phy_node); 2501 if (id == 0) 2502 priv->p5_mode = MUX_PHY_P0; 2503 if (id == 4) 2504 priv->p5_mode = MUX_PHY_P4; 2505 } 2506 of_node_put(mac_np); 2507 of_node_put(phy_node); 2508 break; 2509 } 2510 2511 if (priv->p5_mode == MUX_PHY_P0 || 2512 priv->p5_mode == MUX_PHY_P4) { 2513 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 2514 mt7530_setup_port5(ds, interface); 2515 } 2516 } 2517 2518 #ifdef CONFIG_GPIOLIB 2519 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2520 ret = mt7530_setup_gpio(priv); 2521 if (ret) 2522 return ret; 2523 } 2524 #endif /* CONFIG_GPIOLIB */ 2525 2526 /* Flush the FDB table */ 2527 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2528 if (ret < 0) 2529 return ret; 2530 2531 return 0; 2532 } 2533 2534 static int 2535 mt7531_setup_common(struct dsa_switch *ds) 2536 { 2537 struct mt7530_priv *priv = ds->priv; 2538 int ret, i; 2539 2540 mt753x_trap_frames(priv); 2541 2542 /* Enable and reset MIB counters */ 2543 mt7530_mib_reset(ds); 2544 2545 /* Disable flooding on all ports */ 2546 mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2547 UNU_FFP_MASK); 2548 2549 for (i = 0; i < priv->ds->num_ports; i++) { 2550 /* Clear link settings and enable force mode to force link down 2551 * on all ports until they're enabled later. 2552 */ 2553 mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK | 2554 MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK); 2555 2556 /* Disable forwarding by default on all ports */ 2557 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2558 PCR_MATRIX_CLR); 2559 2560 /* Disable learning by default on all ports */ 2561 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2562 2563 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2564 2565 if (dsa_is_cpu_port(ds, i)) { 2566 mt753x_cpu_port_enable(ds, i); 2567 } else { 2568 mt7530_port_disable(ds, i); 2569 2570 /* Set default PVID to 0 on all user ports */ 2571 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2572 G0_PORT_VID_DEF); 2573 } 2574 2575 /* Enable consistent egress tag */ 2576 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2577 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2578 } 2579 2580 /* Allow mirroring frames received on the local port (monitor port). */ 2581 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2582 2583 /* Flush the FDB table */ 2584 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2585 if (ret < 0) 2586 return ret; 2587 2588 return 0; 2589 } 2590 2591 static int 2592 mt7531_setup(struct dsa_switch *ds) 2593 { 2594 struct mt7530_priv *priv = ds->priv; 2595 struct mt7530_dummy_poll p; 2596 u32 val, id; 2597 int ret, i; 2598 2599 /* Reset whole chip through gpio pin or memory-mapped registers for 2600 * different type of hardware 2601 */ 2602 if (priv->mcm) { 2603 reset_control_assert(priv->rstc); 2604 usleep_range(5000, 5100); 2605 reset_control_deassert(priv->rstc); 2606 } else { 2607 gpiod_set_value_cansleep(priv->reset, 0); 2608 usleep_range(5000, 5100); 2609 gpiod_set_value_cansleep(priv->reset, 1); 2610 } 2611 2612 /* Waiting for MT7530 got to stable */ 2613 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2614 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2615 20, 1000000); 2616 if (ret < 0) { 2617 dev_err(priv->dev, "reset timeout\n"); 2618 return ret; 2619 } 2620 2621 id = mt7530_read(priv, MT7531_CREV); 2622 id >>= CHIP_NAME_SHIFT; 2623 2624 if (id != MT7531_ID) { 2625 dev_err(priv->dev, "chip %x can't be supported\n", id); 2626 return -ENODEV; 2627 } 2628 2629 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2630 * MT7531BE has got only one SGMII unit which is for port 6. 2631 */ 2632 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2633 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2634 2635 /* Force link down on all ports before internal reset */ 2636 for (i = 0; i < priv->ds->num_ports; i++) 2637 mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); 2638 2639 /* Reset the switch through internal reset */ 2640 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2641 2642 if (!priv->p5_sgmii) { 2643 mt7531_pll_setup(priv); 2644 } else { 2645 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2646 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2647 * to expose the MDIO bus of the switch. 2648 */ 2649 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2650 MT7531_EXT_P_MDC_11); 2651 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2652 MT7531_EXT_P_MDIO_12); 2653 } 2654 2655 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2656 MT7531_GPIO0_INTERRUPT); 2657 2658 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2659 * phy_device has not yet been created provided for 2660 * phy_[read,write]_mmd_indirect is called, we provide our own 2661 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2662 */ 2663 val = mt7531_ind_c45_phy_read(priv, 2664 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2665 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2666 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2667 val &= ~MT7531_PHY_PLL_OFF; 2668 mt7531_ind_c45_phy_write(priv, 2669 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2670 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2671 2672 /* Disable EEE advertisement on the switch PHYs. */ 2673 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2674 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2675 i++) { 2676 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2677 0); 2678 } 2679 2680 ret = mt7531_setup_common(ds); 2681 if (ret) 2682 return ret; 2683 2684 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2685 ret = mt7530_setup_vlan0(priv); 2686 if (ret) 2687 return ret; 2688 2689 ds->assisted_learning_on_cpu_port = true; 2690 ds->mtu_enforcement_ingress = true; 2691 2692 return 0; 2693 } 2694 2695 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2696 struct phylink_config *config) 2697 { 2698 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2699 2700 switch (port) { 2701 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2702 case 0 ... 4: 2703 __set_bit(PHY_INTERFACE_MODE_GMII, 2704 config->supported_interfaces); 2705 break; 2706 2707 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2708 case 5: 2709 phy_interface_set_rgmii(config->supported_interfaces); 2710 __set_bit(PHY_INTERFACE_MODE_MII, 2711 config->supported_interfaces); 2712 __set_bit(PHY_INTERFACE_MODE_GMII, 2713 config->supported_interfaces); 2714 break; 2715 2716 /* Port 6 supports rgmii and trgmii. */ 2717 case 6: 2718 __set_bit(PHY_INTERFACE_MODE_RGMII, 2719 config->supported_interfaces); 2720 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2721 config->supported_interfaces); 2722 break; 2723 } 2724 } 2725 2726 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2727 struct phylink_config *config) 2728 { 2729 struct mt7530_priv *priv = ds->priv; 2730 2731 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2732 2733 switch (port) { 2734 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2735 case 0 ... 4: 2736 __set_bit(PHY_INTERFACE_MODE_GMII, 2737 config->supported_interfaces); 2738 break; 2739 2740 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2741 * MT7531AE. 2742 */ 2743 case 5: 2744 if (!priv->p5_sgmii) { 2745 phy_interface_set_rgmii(config->supported_interfaces); 2746 break; 2747 } 2748 fallthrough; 2749 2750 /* Port 6 supports sgmii/802.3z. */ 2751 case 6: 2752 __set_bit(PHY_INTERFACE_MODE_SGMII, 2753 config->supported_interfaces); 2754 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2755 config->supported_interfaces); 2756 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2757 config->supported_interfaces); 2758 2759 config->mac_capabilities |= MAC_2500FD; 2760 break; 2761 } 2762 } 2763 2764 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2765 struct phylink_config *config) 2766 { 2767 switch (port) { 2768 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2769 case 0 ... 3: 2770 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2771 config->supported_interfaces); 2772 2773 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2774 break; 2775 2776 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2777 case 6: 2778 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2779 config->supported_interfaces); 2780 2781 config->mac_capabilities |= MAC_10000FD; 2782 break; 2783 } 2784 } 2785 2786 static void 2787 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2788 phy_interface_t interface) 2789 { 2790 struct mt7530_priv *priv = ds->priv; 2791 2792 if (port == 5) 2793 mt7530_setup_port5(priv->ds, interface); 2794 else if (port == 6) 2795 mt7530_setup_port6(priv->ds, interface); 2796 } 2797 2798 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2799 phy_interface_t interface, 2800 struct phy_device *phydev) 2801 { 2802 u32 val; 2803 2804 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2805 val |= GP_CLK_EN; 2806 val &= ~GP_MODE_MASK; 2807 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2808 val &= ~CLK_SKEW_IN_MASK; 2809 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2810 val &= ~CLK_SKEW_OUT_MASK; 2811 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2812 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2813 2814 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2815 if (!phydev || phy_driver_is_genphy(phydev)) { 2816 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2817 switch (interface) { 2818 case PHY_INTERFACE_MODE_RGMII: 2819 val |= TXCLK_NO_REVERSE; 2820 val |= RXCLK_NO_DELAY; 2821 break; 2822 case PHY_INTERFACE_MODE_RGMII_RXID: 2823 val |= TXCLK_NO_REVERSE; 2824 break; 2825 case PHY_INTERFACE_MODE_RGMII_TXID: 2826 val |= RXCLK_NO_DELAY; 2827 break; 2828 case PHY_INTERFACE_MODE_RGMII_ID: 2829 break; 2830 default: 2831 break; 2832 } 2833 } 2834 2835 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2836 } 2837 2838 static void 2839 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2840 phy_interface_t interface) 2841 { 2842 struct mt7530_priv *priv = ds->priv; 2843 struct phy_device *phydev; 2844 struct dsa_port *dp; 2845 2846 if (phy_interface_mode_is_rgmii(interface)) { 2847 dp = dsa_to_port(ds, port); 2848 phydev = dp->user->phydev; 2849 mt7531_rgmii_setup(priv, interface, phydev); 2850 } 2851 } 2852 2853 static struct phylink_pcs * 2854 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 2855 phy_interface_t interface) 2856 { 2857 struct dsa_port *dp = dsa_phylink_to_port(config); 2858 struct mt7530_priv *priv = dp->ds->priv; 2859 2860 switch (interface) { 2861 case PHY_INTERFACE_MODE_TRGMII: 2862 return &priv->pcs[dp->index].pcs; 2863 case PHY_INTERFACE_MODE_SGMII: 2864 case PHY_INTERFACE_MODE_1000BASEX: 2865 case PHY_INTERFACE_MODE_2500BASEX: 2866 return priv->ports[dp->index].sgmii_pcs; 2867 default: 2868 return NULL; 2869 } 2870 } 2871 2872 static void 2873 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2874 const struct phylink_link_state *state) 2875 { 2876 struct dsa_port *dp = dsa_phylink_to_port(config); 2877 struct dsa_switch *ds = dp->ds; 2878 struct mt7530_priv *priv; 2879 int port = dp->index; 2880 2881 priv = ds->priv; 2882 2883 if ((port == 5 || port == 6) && priv->info->mac_port_config) 2884 priv->info->mac_port_config(ds, port, mode, state->interface); 2885 2886 /* Are we connected to external phy */ 2887 if (port == 5 && dsa_is_user_port(ds, 5)) 2888 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); 2889 } 2890 2891 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 2892 unsigned int mode, 2893 phy_interface_t interface) 2894 { 2895 struct dsa_port *dp = dsa_phylink_to_port(config); 2896 struct mt7530_priv *priv = dp->ds->priv; 2897 2898 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); 2899 } 2900 2901 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 2902 struct phy_device *phydev, 2903 unsigned int mode, 2904 phy_interface_t interface, 2905 int speed, int duplex, 2906 bool tx_pause, bool rx_pause) 2907 { 2908 struct dsa_port *dp = dsa_phylink_to_port(config); 2909 struct mt7530_priv *priv = dp->ds->priv; 2910 u32 mcr; 2911 2912 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 2913 2914 switch (speed) { 2915 case SPEED_1000: 2916 case SPEED_2500: 2917 case SPEED_10000: 2918 mcr |= PMCR_FORCE_SPEED_1000; 2919 break; 2920 case SPEED_100: 2921 mcr |= PMCR_FORCE_SPEED_100; 2922 break; 2923 } 2924 if (duplex == DUPLEX_FULL) { 2925 mcr |= PMCR_FORCE_FDX; 2926 if (tx_pause) 2927 mcr |= PMCR_FORCE_TX_FC_EN; 2928 if (rx_pause) 2929 mcr |= PMCR_FORCE_RX_FC_EN; 2930 } 2931 2932 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2933 switch (speed) { 2934 case SPEED_1000: 2935 case SPEED_2500: 2936 mcr |= PMCR_FORCE_EEE1G; 2937 break; 2938 case SPEED_100: 2939 mcr |= PMCR_FORCE_EEE100; 2940 break; 2941 } 2942 } 2943 2944 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); 2945 } 2946 2947 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2948 struct phylink_config *config) 2949 { 2950 struct mt7530_priv *priv = ds->priv; 2951 2952 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 2953 2954 priv->info->mac_port_get_caps(ds, port, config); 2955 } 2956 2957 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2958 unsigned long *supported, 2959 const struct phylink_link_state *state) 2960 { 2961 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2962 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2963 phy_interface_mode_is_8023z(state->interface)) 2964 phylink_clear(supported, Autoneg); 2965 2966 return 0; 2967 } 2968 2969 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2970 struct phylink_link_state *state) 2971 { 2972 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2973 int port = pcs_to_mt753x_pcs(pcs)->port; 2974 u32 pmsr; 2975 2976 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2977 2978 state->link = (pmsr & PMSR_LINK); 2979 state->an_complete = state->link; 2980 state->duplex = !!(pmsr & PMSR_DPX); 2981 2982 switch (pmsr & PMSR_SPEED_MASK) { 2983 case PMSR_SPEED_10: 2984 state->speed = SPEED_10; 2985 break; 2986 case PMSR_SPEED_100: 2987 state->speed = SPEED_100; 2988 break; 2989 case PMSR_SPEED_1000: 2990 state->speed = SPEED_1000; 2991 break; 2992 default: 2993 state->speed = SPEED_UNKNOWN; 2994 break; 2995 } 2996 2997 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2998 if (pmsr & PMSR_RX_FC) 2999 state->pause |= MLO_PAUSE_RX; 3000 if (pmsr & PMSR_TX_FC) 3001 state->pause |= MLO_PAUSE_TX; 3002 } 3003 3004 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3005 phy_interface_t interface, 3006 const unsigned long *advertising, 3007 bool permit_pause_to_mac) 3008 { 3009 return 0; 3010 } 3011 3012 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3013 { 3014 } 3015 3016 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3017 .pcs_validate = mt753x_pcs_validate, 3018 .pcs_get_state = mt7530_pcs_get_state, 3019 .pcs_config = mt753x_pcs_config, 3020 .pcs_an_restart = mt7530_pcs_an_restart, 3021 }; 3022 3023 static int 3024 mt753x_setup(struct dsa_switch *ds) 3025 { 3026 struct mt7530_priv *priv = ds->priv; 3027 int ret = priv->info->sw_setup(ds); 3028 int i; 3029 3030 if (ret) 3031 return ret; 3032 3033 ret = mt7530_setup_irq(priv); 3034 if (ret) 3035 return ret; 3036 3037 ret = mt7530_setup_mdio(priv); 3038 if (ret && priv->irq) 3039 mt7530_free_irq_common(priv); 3040 if (ret) 3041 return ret; 3042 3043 /* Initialise the PCS devices */ 3044 for (i = 0; i < priv->ds->num_ports; i++) { 3045 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3046 priv->pcs[i].pcs.neg_mode = true; 3047 priv->pcs[i].priv = priv; 3048 priv->pcs[i].port = i; 3049 } 3050 3051 if (priv->create_sgmii) { 3052 ret = priv->create_sgmii(priv); 3053 if (ret && priv->irq) 3054 mt7530_free_irq(priv); 3055 } 3056 3057 return ret; 3058 } 3059 3060 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3061 struct ethtool_keee *e) 3062 { 3063 struct mt7530_priv *priv = ds->priv; 3064 u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); 3065 3066 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3067 e->tx_lpi_timer = LPI_THRESH_GET(eeecr); 3068 3069 return 0; 3070 } 3071 3072 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3073 struct ethtool_keee *e) 3074 { 3075 struct mt7530_priv *priv = ds->priv; 3076 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3077 3078 if (e->tx_lpi_timer > 0xFFF) 3079 return -EINVAL; 3080 3081 set = LPI_THRESH_SET(e->tx_lpi_timer); 3082 if (!e->tx_lpi_enabled) 3083 /* Force LPI Mode without a delay */ 3084 set |= LPI_MODE_EN; 3085 mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set); 3086 3087 return 0; 3088 } 3089 3090 static void 3091 mt753x_conduit_state_change(struct dsa_switch *ds, 3092 const struct net_device *conduit, 3093 bool operational) 3094 { 3095 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3096 struct mt7530_priv *priv = ds->priv; 3097 int val = 0; 3098 u8 mask; 3099 3100 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3101 * forwarded to the numerically smallest CPU port whose conduit 3102 * interface is up. 3103 */ 3104 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3105 return; 3106 3107 mask = BIT(cpu_dp->index); 3108 3109 if (operational) 3110 priv->active_cpu_ports |= mask; 3111 else 3112 priv->active_cpu_ports &= ~mask; 3113 3114 if (priv->active_cpu_ports) { 3115 val = MT7530_CPU_EN | 3116 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3117 } 3118 3119 mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3120 } 3121 3122 static int mt7988_setup(struct dsa_switch *ds) 3123 { 3124 struct mt7530_priv *priv = ds->priv; 3125 3126 /* Reset the switch */ 3127 reset_control_assert(priv->rstc); 3128 usleep_range(20, 50); 3129 reset_control_deassert(priv->rstc); 3130 usleep_range(20, 50); 3131 3132 /* Reset the switch PHYs */ 3133 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3134 3135 return mt7531_setup_common(ds); 3136 } 3137 3138 const struct dsa_switch_ops mt7530_switch_ops = { 3139 .get_tag_protocol = mtk_get_tag_protocol, 3140 .setup = mt753x_setup, 3141 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3142 .get_strings = mt7530_get_strings, 3143 .get_ethtool_stats = mt7530_get_ethtool_stats, 3144 .get_sset_count = mt7530_get_sset_count, 3145 .set_ageing_time = mt7530_set_ageing_time, 3146 .port_enable = mt7530_port_enable, 3147 .port_disable = mt7530_port_disable, 3148 .port_change_mtu = mt7530_port_change_mtu, 3149 .port_max_mtu = mt7530_port_max_mtu, 3150 .port_stp_state_set = mt7530_stp_state_set, 3151 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3152 .port_bridge_flags = mt7530_port_bridge_flags, 3153 .port_bridge_join = mt7530_port_bridge_join, 3154 .port_bridge_leave = mt7530_port_bridge_leave, 3155 .port_fdb_add = mt7530_port_fdb_add, 3156 .port_fdb_del = mt7530_port_fdb_del, 3157 .port_fdb_dump = mt7530_port_fdb_dump, 3158 .port_mdb_add = mt7530_port_mdb_add, 3159 .port_mdb_del = mt7530_port_mdb_del, 3160 .port_vlan_filtering = mt7530_port_vlan_filtering, 3161 .port_vlan_add = mt7530_port_vlan_add, 3162 .port_vlan_del = mt7530_port_vlan_del, 3163 .port_mirror_add = mt753x_port_mirror_add, 3164 .port_mirror_del = mt753x_port_mirror_del, 3165 .phylink_get_caps = mt753x_phylink_get_caps, 3166 .get_mac_eee = mt753x_get_mac_eee, 3167 .set_mac_eee = mt753x_set_mac_eee, 3168 .conduit_state_change = mt753x_conduit_state_change, 3169 }; 3170 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3171 3172 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3173 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3174 .mac_config = mt753x_phylink_mac_config, 3175 .mac_link_down = mt753x_phylink_mac_link_down, 3176 .mac_link_up = mt753x_phylink_mac_link_up, 3177 }; 3178 3179 const struct mt753x_info mt753x_table[] = { 3180 [ID_MT7621] = { 3181 .id = ID_MT7621, 3182 .pcs_ops = &mt7530_pcs_ops, 3183 .sw_setup = mt7530_setup, 3184 .phy_read_c22 = mt7530_phy_read_c22, 3185 .phy_write_c22 = mt7530_phy_write_c22, 3186 .phy_read_c45 = mt7530_phy_read_c45, 3187 .phy_write_c45 = mt7530_phy_write_c45, 3188 .mac_port_get_caps = mt7530_mac_port_get_caps, 3189 .mac_port_config = mt7530_mac_config, 3190 }, 3191 [ID_MT7530] = { 3192 .id = ID_MT7530, 3193 .pcs_ops = &mt7530_pcs_ops, 3194 .sw_setup = mt7530_setup, 3195 .phy_read_c22 = mt7530_phy_read_c22, 3196 .phy_write_c22 = mt7530_phy_write_c22, 3197 .phy_read_c45 = mt7530_phy_read_c45, 3198 .phy_write_c45 = mt7530_phy_write_c45, 3199 .mac_port_get_caps = mt7530_mac_port_get_caps, 3200 .mac_port_config = mt7530_mac_config, 3201 }, 3202 [ID_MT7531] = { 3203 .id = ID_MT7531, 3204 .pcs_ops = &mt7530_pcs_ops, 3205 .sw_setup = mt7531_setup, 3206 .phy_read_c22 = mt7531_ind_c22_phy_read, 3207 .phy_write_c22 = mt7531_ind_c22_phy_write, 3208 .phy_read_c45 = mt7531_ind_c45_phy_read, 3209 .phy_write_c45 = mt7531_ind_c45_phy_write, 3210 .mac_port_get_caps = mt7531_mac_port_get_caps, 3211 .mac_port_config = mt7531_mac_config, 3212 }, 3213 [ID_MT7988] = { 3214 .id = ID_MT7988, 3215 .pcs_ops = &mt7530_pcs_ops, 3216 .sw_setup = mt7988_setup, 3217 .phy_read_c22 = mt7531_ind_c22_phy_read, 3218 .phy_write_c22 = mt7531_ind_c22_phy_write, 3219 .phy_read_c45 = mt7531_ind_c45_phy_read, 3220 .phy_write_c45 = mt7531_ind_c45_phy_write, 3221 .mac_port_get_caps = mt7988_mac_port_get_caps, 3222 }, 3223 }; 3224 EXPORT_SYMBOL_GPL(mt753x_table); 3225 3226 int 3227 mt7530_probe_common(struct mt7530_priv *priv) 3228 { 3229 struct device *dev = priv->dev; 3230 3231 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3232 if (!priv->ds) 3233 return -ENOMEM; 3234 3235 priv->ds->dev = dev; 3236 priv->ds->num_ports = MT7530_NUM_PORTS; 3237 3238 /* Get the hardware identifier from the devicetree node. 3239 * We will need it for some of the clock and regulator setup. 3240 */ 3241 priv->info = of_device_get_match_data(dev); 3242 if (!priv->info) 3243 return -EINVAL; 3244 3245 priv->id = priv->info->id; 3246 priv->dev = dev; 3247 priv->ds->priv = priv; 3248 priv->ds->ops = &mt7530_switch_ops; 3249 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3250 mutex_init(&priv->reg_mutex); 3251 dev_set_drvdata(dev, priv); 3252 3253 return 0; 3254 } 3255 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3256 3257 void 3258 mt7530_remove_common(struct mt7530_priv *priv) 3259 { 3260 if (priv->irq) 3261 mt7530_free_irq(priv); 3262 3263 dsa_unregister_switch(priv->ds); 3264 3265 mutex_destroy(&priv->reg_mutex); 3266 } 3267 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3268 3269 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3270 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3271 MODULE_LICENSE("GPL"); 3272