1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2020-2021 NXP 4 */ 5 6 #include <linux/init.h> 7 #include <linux/interconnect.h> 8 #include <linux/ioctl.h> 9 #include <linux/list.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/delay.h> 14 #include <linux/rational.h> 15 #include <linux/time64.h> 16 #include <media/videobuf2-v4l2.h> 17 #include <media/videobuf2-dma-contig.h> 18 #include <linux/videodev2.h> 19 #include "vpu.h" 20 #include "vpu_rpc.h" 21 #include "vpu_defs.h" 22 #include "vpu_helpers.h" 23 #include "vpu_v4l2.h" 24 #include "vpu_cmds.h" 25 #include "vpu_imx8q.h" 26 #include "vpu_malone.h" 27 28 #define CMD_SIZE 25600 29 #define MSG_SIZE 25600 30 #define CODEC_SIZE 0x1000 31 #define JPEG_SIZE 0x1000 32 #define SEQ_SIZE 0x1000 33 #define GOP_SIZE 0x1000 34 #define PIC_SIZE 0x1000 35 #define QMETER_SIZE 0x1000 36 #define DBGLOG_SIZE 0x10000 37 #define DEBUG_SIZE 0x80000 38 #define ENG_SIZE 0x1000 39 #define MALONE_SKIPPED_FRAME_ID 0x555 40 41 #define MALONE_ALIGN_MBI 0x800 42 #define MALONE_DCP_CHUNK_BIT 16 43 #define MALONE_DCP_SIZE_MAX 0x3000000 44 #define MALONE_DCP_SIZE_MIN 0x100000 45 #define MALONE_DCP_FIXED_MB_ALLOC 250 46 47 #define CONFIG_SET(val, cfg, pos, mask) \ 48 (*(cfg) |= (((val) << (pos)) & (mask))) 49 //x means source data , y means destination data 50 #define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F) 51 #define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300) 52 #define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400) 53 #define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800) 54 #define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000) 55 #define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000) 56 #define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000) 57 #define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000) 58 #define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000) 59 #define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000) 60 #define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000) 61 #define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000) 62 #define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000) 63 #define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000) 64 #define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000) 65 #define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000) 66 #define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000) 67 #define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000) 68 69 #define MALONE_DEC_FMT_RV_MASK BIT(21) 70 71 enum vpu_malone_stream_input_mode { 72 INVALID_MODE = 0, 73 FRAME_LVL, 74 NON_FRAME_LVL 75 }; 76 77 enum vpu_malone_format { 78 MALONE_FMT_NULL = 0x0, 79 MALONE_FMT_AVC = 0x1, 80 MALONE_FMT_MP2 = 0x2, 81 MALONE_FMT_VC1 = 0x3, 82 MALONE_FMT_AVS = 0x4, 83 MALONE_FMT_ASP = 0x5, 84 MALONE_FMT_JPG = 0x6, 85 MALONE_FMT_RV = 0x7, 86 MALONE_FMT_VP6 = 0x8, 87 MALONE_FMT_SPK = 0x9, 88 MALONE_FMT_VP8 = 0xA, 89 MALONE_FMT_HEVC = 0xB, 90 MALONE_FMT_LAST = MALONE_FMT_HEVC 91 }; 92 93 enum { 94 VID_API_CMD_NULL = 0x00, 95 VID_API_CMD_PARSE_NEXT_SEQ = 0x01, 96 VID_API_CMD_PARSE_NEXT_I = 0x02, 97 VID_API_CMD_PARSE_NEXT_IP = 0x03, 98 VID_API_CMD_PARSE_NEXT_ANY = 0x04, 99 VID_API_CMD_DEC_PIC = 0x05, 100 VID_API_CMD_UPDATE_ES_WR_PTR = 0x06, 101 VID_API_CMD_UPDATE_ES_RD_PTR = 0x07, 102 VID_API_CMD_UPDATE_UDATA = 0x08, 103 VID_API_CMD_GET_FSINFO = 0x09, 104 VID_API_CMD_SKIP_PIC = 0x0a, 105 VID_API_CMD_DEC_CHUNK = 0x0b, 106 VID_API_CMD_START = 0x10, 107 VID_API_CMD_STOP = 0x11, 108 VID_API_CMD_ABORT = 0x12, 109 VID_API_CMD_RST_BUF = 0x13, 110 VID_API_CMD_FS_RELEASE = 0x15, 111 VID_API_CMD_MEM_REGION_ATTACH = 0x16, 112 VID_API_CMD_MEM_REGION_DETACH = 0x17, 113 VID_API_CMD_MVC_VIEW_SELECT = 0x18, 114 VID_API_CMD_FS_ALLOC = 0x19, 115 VID_API_CMD_DBG_GET_STATUS = 0x1C, 116 VID_API_CMD_DBG_START_LOG = 0x1D, 117 VID_API_CMD_DBG_STOP_LOG = 0x1E, 118 VID_API_CMD_DBG_DUMP_LOG = 0x1F, 119 VID_API_CMD_YUV_READY = 0x20, 120 VID_API_CMD_TS = 0x21, 121 122 VID_API_CMD_FIRM_RESET = 0x40, 123 124 VID_API_CMD_SNAPSHOT = 0xAA, 125 VID_API_CMD_ROLL_SNAPSHOT = 0xAB, 126 VID_API_CMD_LOCK_SCHEDULER = 0xAC, 127 VID_API_CMD_UNLOCK_SCHEDULER = 0xAD, 128 VID_API_CMD_CQ_FIFO_DUMP = 0xAE, 129 VID_API_CMD_DBG_FIFO_DUMP = 0xAF, 130 VID_API_CMD_SVC_ILP = 0xBB, 131 VID_API_CMD_FW_STATUS = 0xF0, 132 VID_API_CMD_INVALID = 0xFF 133 }; 134 135 enum { 136 VID_API_EVENT_NULL = 0x00, 137 VID_API_EVENT_RESET_DONE = 0x01, 138 VID_API_EVENT_SEQ_HDR_FOUND = 0x02, 139 VID_API_EVENT_PIC_HDR_FOUND = 0x03, 140 VID_API_EVENT_PIC_DECODED = 0x04, 141 VID_API_EVENT_FIFO_LOW = 0x05, 142 VID_API_EVENT_FIFO_HIGH = 0x06, 143 VID_API_EVENT_FIFO_EMPTY = 0x07, 144 VID_API_EVENT_FIFO_FULL = 0x08, 145 VID_API_EVENT_BS_ERROR = 0x09, 146 VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A, 147 VID_API_EVENT_RES_CHANGE = 0x0B, 148 VID_API_EVENT_FIFO_OVF = 0x0C, 149 VID_API_EVENT_CHUNK_DECODED = 0x0D, 150 VID_API_EVENT_REQ_FRAME_BUFF = 0x10, 151 VID_API_EVENT_FRAME_BUFF_RDY = 0x11, 152 VID_API_EVENT_REL_FRAME_BUFF = 0x12, 153 VID_API_EVENT_STR_BUF_RST = 0x13, 154 VID_API_EVENT_RET_PING = 0x14, 155 VID_API_EVENT_QMETER = 0x15, 156 VID_API_EVENT_STR_FMT_CHANGE = 0x16, 157 VID_API_EVENT_FIRMWARE_XCPT = 0x17, 158 VID_API_EVENT_START_DONE = 0x18, 159 VID_API_EVENT_STOPPED = 0x19, 160 VID_API_EVENT_ABORT_DONE = 0x1A, 161 VID_API_EVENT_FINISHED = 0x1B, 162 VID_API_EVENT_DBG_STAT_UPDATE = 0x1C, 163 VID_API_EVENT_DBG_LOG_STARTED = 0x1D, 164 VID_API_EVENT_DBG_LOG_STOPPED = 0x1E, 165 VID_API_EVENT_DBG_LOG_UPDATED = 0x1F, 166 VID_API_EVENT_DBG_MSG_DEC = 0x20, 167 VID_API_EVENT_DEC_SC_ERR = 0x21, 168 VID_API_EVENT_CQ_FIFO_DUMP = 0x22, 169 VID_API_EVENT_DBG_FIFO_DUMP = 0x23, 170 VID_API_EVENT_DEC_CHECK_RES = 0x24, 171 VID_API_EVENT_DEC_CFG_INFO = 0x25, 172 VID_API_EVENT_UNSUPPORTED_STREAM = 0x26, 173 VID_API_EVENT_PIC_SKIPPED = 0x27, 174 VID_API_EVENT_STR_SUSPENDED = 0x30, 175 VID_API_EVENT_SNAPSHOT_DONE = 0x40, 176 VID_API_EVENT_FW_STATUS = 0xF0, 177 VID_API_EVENT_INVALID = 0xFF 178 }; 179 180 struct vpu_malone_buffer_desc { 181 struct vpu_rpc_buffer_desc buffer; 182 u32 low; 183 u32 high; 184 }; 185 186 struct vpu_malone_str_buffer { 187 u32 wptr; 188 u32 rptr; 189 u32 start; 190 u32 end; 191 u32 lwm; 192 }; 193 194 struct vpu_malone_picth_info { 195 u32 frame_pitch; 196 }; 197 198 struct vpu_malone_table_desc { 199 u32 array_base; 200 u32 size; 201 }; 202 203 struct vpu_malone_dbglog_desc { 204 u32 addr; 205 u32 size; 206 u32 level; 207 u32 reserved; 208 }; 209 210 struct vpu_malone_udata { 211 u32 base; 212 u32 total_size; 213 u32 slot_size; 214 }; 215 216 struct vpu_malone_buffer_info { 217 u32 stream_input_mode; 218 u32 stream_pic_input_count; 219 u32 stream_pic_parsed_count; 220 u32 stream_buffer_threshold; 221 u32 stream_pic_end_flag; 222 }; 223 224 struct vpu_malone_encrypt_info { 225 u32 rec4key[8]; 226 u32 obfusc; 227 }; 228 229 struct malone_iface { 230 u32 exec_base_addr; 231 u32 exec_area_size; 232 struct vpu_malone_buffer_desc cmd_buffer_desc; 233 struct vpu_malone_buffer_desc msg_buffer_desc; 234 u32 cmd_int_enable[VID_API_NUM_STREAMS]; 235 struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS]; 236 u32 stream_config[VID_API_NUM_STREAMS]; 237 struct vpu_malone_table_desc codec_param_tab_desc; 238 struct vpu_malone_table_desc jpeg_param_tab_desc; 239 u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR]; 240 struct vpu_malone_table_desc seq_info_tab_desc; 241 struct vpu_malone_table_desc pic_info_tab_desc; 242 struct vpu_malone_table_desc gop_info_tab_desc; 243 struct vpu_malone_table_desc qmeter_info_tab_desc; 244 u32 stream_error[VID_API_NUM_STREAMS]; 245 u32 fw_version; 246 u32 fw_offset; 247 u32 max_streams; 248 struct vpu_malone_dbglog_desc dbglog_desc; 249 struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS]; 250 struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS]; 251 struct vpu_malone_buffer_desc debug_buffer_desc; 252 struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS]; 253 u32 encrypt_info[VID_API_NUM_STREAMS]; 254 struct vpu_rpc_system_config system_cfg; 255 u32 api_version; 256 struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS]; 257 }; 258 259 struct malone_jpg_params { 260 u32 rotation_angle; 261 u32 horiz_scale_factor; 262 u32 vert_scale_factor; 263 u32 rotation_mode; 264 u32 rgb_mode; 265 u32 chunk_mode; /* 0 ~ 1 */ 266 u32 last_chunk; /* 0 ~ 1 */ 267 u32 chunk_rows; /* 0 ~ 255 */ 268 u32 num_bytes; 269 u32 jpg_crop_x; 270 u32 jpg_crop_y; 271 u32 jpg_crop_width; 272 u32 jpg_crop_height; 273 u32 jpg_mjpeg_mode; 274 u32 jpg_mjpeg_interlaced; 275 }; 276 277 struct malone_codec_params { 278 u32 disp_imm; 279 u32 fourcc; 280 u32 codec_version; 281 u32 frame_rate; 282 u32 dbglog_enable; 283 u32 bsdma_lwm; 284 u32 bbd_coring; 285 u32 bbd_s_thr_row; 286 u32 bbd_p_thr_row; 287 u32 bbd_s_thr_logo_row; 288 u32 bbd_p_thr_logo_row; 289 u32 bbd_s_thr_col; 290 u32 bbd_p_thr_col; 291 u32 bbd_chr_thr_row; 292 u32 bbd_chr_thr_col; 293 u32 bbd_uv_mid_level; 294 u32 bbd_excl_win_mb_left; 295 u32 bbd_excl_win_mb_right; 296 }; 297 298 struct malone_padding_scode { 299 u32 scode_type; 300 u32 pixelformat; 301 u32 data[2]; 302 }; 303 304 struct malone_fmt_mapping { 305 u32 pixelformat; 306 enum vpu_malone_format malone_format; 307 u32 is_disabled; 308 }; 309 310 struct malone_scode_t { 311 struct vpu_inst *inst; 312 struct vb2_buffer *vb; 313 u32 wptr; 314 u32 need_data; 315 }; 316 317 struct malone_scode_handler { 318 u32 pixelformat; 319 int (*insert_scode_seq)(struct malone_scode_t *scode); 320 int (*insert_scode_pic)(struct malone_scode_t *scode); 321 }; 322 323 struct vpu_dec_ctrl { 324 struct malone_codec_params *codec_param; 325 struct malone_jpg_params *jpg; 326 void *seq_mem; 327 void *pic_mem; 328 void *gop_mem; 329 void *qmeter_mem; 330 void *dbglog_mem; 331 struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS]; 332 u32 buf_addr[VID_API_NUM_STREAMS]; 333 }; 334 335 u32 vpu_malone_get_data_size(void) 336 { 337 return sizeof(struct vpu_dec_ctrl); 338 } 339 340 void vpu_malone_init_rpc(struct vpu_shared_addr *shared, 341 struct vpu_buffer *rpc, dma_addr_t boot_addr) 342 { 343 struct malone_iface *iface; 344 struct vpu_dec_ctrl *hc; 345 unsigned long base_phy_addr; 346 unsigned long phy_addr; 347 unsigned long offset; 348 unsigned int i; 349 350 if (rpc->phys < boot_addr) 351 return; 352 353 iface = rpc->virt; 354 base_phy_addr = rpc->phys - boot_addr; 355 hc = shared->priv; 356 357 shared->iface = iface; 358 shared->boot_addr = boot_addr; 359 360 iface->exec_base_addr = base_phy_addr; 361 iface->exec_area_size = rpc->length; 362 363 offset = sizeof(struct malone_iface); 364 phy_addr = base_phy_addr + offset; 365 366 shared->cmd_desc = &iface->cmd_buffer_desc.buffer; 367 shared->cmd_mem_vir = rpc->virt + offset; 368 iface->cmd_buffer_desc.buffer.start = 369 iface->cmd_buffer_desc.buffer.rptr = 370 iface->cmd_buffer_desc.buffer.wptr = phy_addr; 371 iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE; 372 offset += CMD_SIZE; 373 phy_addr = base_phy_addr + offset; 374 375 shared->msg_desc = &iface->msg_buffer_desc.buffer; 376 shared->msg_mem_vir = rpc->virt + offset; 377 iface->msg_buffer_desc.buffer.start = 378 iface->msg_buffer_desc.buffer.wptr = 379 iface->msg_buffer_desc.buffer.rptr = phy_addr; 380 iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE; 381 offset += MSG_SIZE; 382 phy_addr = base_phy_addr + offset; 383 384 iface->codec_param_tab_desc.array_base = phy_addr; 385 hc->codec_param = rpc->virt + offset; 386 offset += CODEC_SIZE; 387 phy_addr = base_phy_addr + offset; 388 389 iface->jpeg_param_tab_desc.array_base = phy_addr; 390 hc->jpg = rpc->virt + offset; 391 offset += JPEG_SIZE; 392 phy_addr = base_phy_addr + offset; 393 394 iface->seq_info_tab_desc.array_base = phy_addr; 395 hc->seq_mem = rpc->virt + offset; 396 offset += SEQ_SIZE; 397 phy_addr = base_phy_addr + offset; 398 399 iface->pic_info_tab_desc.array_base = phy_addr; 400 hc->pic_mem = rpc->virt + offset; 401 offset += PIC_SIZE; 402 phy_addr = base_phy_addr + offset; 403 404 iface->gop_info_tab_desc.array_base = phy_addr; 405 hc->gop_mem = rpc->virt + offset; 406 offset += GOP_SIZE; 407 phy_addr = base_phy_addr + offset; 408 409 iface->qmeter_info_tab_desc.array_base = phy_addr; 410 hc->qmeter_mem = rpc->virt + offset; 411 offset += QMETER_SIZE; 412 phy_addr = base_phy_addr + offset; 413 414 iface->dbglog_desc.addr = phy_addr; 415 iface->dbglog_desc.size = DBGLOG_SIZE; 416 hc->dbglog_mem = rpc->virt + offset; 417 offset += DBGLOG_SIZE; 418 phy_addr = base_phy_addr + offset; 419 420 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 421 iface->eng_access_buff_desc[i].buffer.start = 422 iface->eng_access_buff_desc[i].buffer.wptr = 423 iface->eng_access_buff_desc[i].buffer.rptr = phy_addr; 424 iface->eng_access_buff_desc[i].buffer.end = 425 iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE; 426 offset += ENG_SIZE; 427 phy_addr = base_phy_addr + offset; 428 } 429 430 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 431 iface->encrypt_info[i] = phy_addr; 432 offset += sizeof(struct vpu_malone_encrypt_info); 433 phy_addr = base_phy_addr + offset; 434 } 435 436 rpc->bytesused = offset; 437 } 438 439 void vpu_malone_set_log_buf(struct vpu_shared_addr *shared, 440 struct vpu_buffer *log) 441 { 442 struct malone_iface *iface = shared->iface; 443 444 iface->debug_buffer_desc.buffer.start = 445 iface->debug_buffer_desc.buffer.wptr = 446 iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr; 447 iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length; 448 } 449 450 static u32 get_str_buffer_offset(u32 instance) 451 { 452 return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance; 453 } 454 455 void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared, 456 u32 regs_base, void __iomem *regs, u32 core_id) 457 { 458 struct malone_iface *iface = shared->iface; 459 struct vpu_rpc_system_config *config = &iface->system_cfg; 460 struct vpu_dec_ctrl *hc = shared->priv; 461 int i; 462 463 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id); 464 for (i = 0; i < VID_API_NUM_STREAMS; i++) { 465 u32 offset = get_str_buffer_offset(i); 466 467 hc->buf_addr[i] = regs_base + offset; 468 hc->str_buf[i] = regs + offset; 469 } 470 } 471 472 u32 vpu_malone_get_version(struct vpu_shared_addr *shared) 473 { 474 struct malone_iface *iface = shared->iface; 475 476 vpu_malone_enable_format(V4L2_PIX_FMT_RV30, iface->fw_version & MALONE_DEC_FMT_RV_MASK); 477 vpu_malone_enable_format(V4L2_PIX_FMT_RV40, iface->fw_version & MALONE_DEC_FMT_RV_MASK); 478 479 return iface->fw_version; 480 } 481 482 int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared) 483 { 484 return 0xc00000; 485 } 486 487 int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared, 488 u32 instance, 489 struct vpu_buffer *buf) 490 { 491 struct malone_iface *iface = shared->iface; 492 struct vpu_dec_ctrl *hc = shared->priv; 493 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 494 495 writel(buf->phys, &str_buf->start); 496 writel(buf->phys, &str_buf->rptr); 497 writel(buf->phys, &str_buf->wptr); 498 writel(buf->phys + buf->length, &str_buf->end); 499 writel(0x1, &str_buf->lwm); 500 501 iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance]; 502 503 return 0; 504 } 505 506 int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared, 507 u32 instance, 508 struct vpu_rpc_buffer_desc *desc) 509 { 510 struct vpu_dec_ctrl *hc = shared->priv; 511 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 512 513 if (desc) { 514 desc->wptr = readl(&str_buf->wptr); 515 desc->rptr = readl(&str_buf->rptr); 516 desc->start = readl(&str_buf->start); 517 desc->end = readl(&str_buf->end); 518 } 519 520 return 0; 521 } 522 523 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr) 524 { 525 /*update wptr after data is written*/ 526 mb(); 527 writel(wptr, &str_buf->wptr); 528 } 529 530 static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr) 531 { 532 /*update rptr after data is read*/ 533 mb(); 534 writel(rptr, &str_buf->rptr); 535 } 536 537 int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared, 538 u32 instance, u32 ptr, bool write) 539 { 540 struct vpu_dec_ctrl *hc = shared->priv; 541 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 542 543 if (write) 544 vpu_malone_update_wptr(str_buf, ptr); 545 else 546 vpu_malone_update_rptr(str_buf, ptr); 547 548 return 0; 549 } 550 551 static struct malone_fmt_mapping fmt_mappings[] = { 552 {V4L2_PIX_FMT_H264, MALONE_FMT_AVC}, 553 {V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC}, 554 {V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC}, 555 {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1}, 556 {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1}, 557 {V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2}, 558 {V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP}, 559 {V4L2_PIX_FMT_XVID, MALONE_FMT_ASP}, 560 {V4L2_PIX_FMT_H263, MALONE_FMT_ASP}, 561 {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG}, 562 {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8}, 563 {V4L2_PIX_FMT_SPK, MALONE_FMT_SPK}, 564 {V4L2_PIX_FMT_RV30, MALONE_FMT_RV}, 565 {V4L2_PIX_FMT_RV40, MALONE_FMT_RV}, 566 }; 567 568 void vpu_malone_enable_format(u32 pixelformat, int enable) 569 { 570 u32 i; 571 572 for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { 573 if (pixelformat == fmt_mappings[i].pixelformat) { 574 fmt_mappings[i].is_disabled = enable ? 0 : 1; 575 return; 576 } 577 } 578 } 579 580 static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat) 581 { 582 u32 i; 583 584 for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { 585 if (fmt_mappings[i].is_disabled) 586 continue; 587 if (pixelformat == fmt_mappings[i].pixelformat) 588 return fmt_mappings[i].malone_format; 589 } 590 591 return MALONE_FMT_NULL; 592 } 593 594 bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt) 595 { 596 if (!vpu_imx8q_check_fmt(type, pixelfmt)) 597 return false; 598 599 if (pixelfmt == V4L2_PIX_FMT_NV12_8L128 || pixelfmt == V4L2_PIX_FMT_NV12_10BE_8L128 || 600 pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128) 601 return true; 602 if (vpu_malone_format_remap(pixelfmt) == MALONE_FMT_NULL) 603 return false; 604 605 return true; 606 } 607 608 static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared, 609 u32 instance, 610 enum vpu_malone_format malone_format) 611 { 612 struct malone_iface *iface = shared->iface; 613 u32 *curr_str_cfg = &iface->stream_config[instance]; 614 615 *curr_str_cfg = 0; 616 STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg); 617 STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg); 618 STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg); 619 STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg); 620 STREAM_CONFIG_DERING_SET(0, curr_str_cfg); 621 STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg); 622 STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg); 623 STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg); 624 STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg); 625 STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg); 626 STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg); 627 STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg); 628 STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg); 629 STREAM_CONFIG_MCX_SET(1, curr_str_cfg); 630 STREAM_CONFIG_PES_SET(0, curr_str_cfg); 631 STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg); 632 } 633 634 static int vpu_malone_set_params(struct vpu_shared_addr *shared, 635 u32 instance, 636 struct vpu_decode_params *params) 637 { 638 struct malone_iface *iface = shared->iface; 639 struct vpu_dec_ctrl *hc = shared->priv; 640 enum vpu_malone_format malone_format; 641 642 malone_format = vpu_malone_format_remap(params->codec_format); 643 if (WARN_ON(malone_format == MALONE_FMT_NULL)) 644 return -EINVAL; 645 iface->udata_buffer[instance].base = params->udata.base; 646 iface->udata_buffer[instance].slot_size = params->udata.size; 647 648 vpu_malone_set_stream_cfg(shared, instance, malone_format); 649 650 if (malone_format == MALONE_FMT_JPG) { 651 //1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B 652 hc->jpg[instance].jpg_mjpeg_mode = 1; 653 //0: JPGD_MJPEG_PROGRESSIVE 654 hc->jpg[instance].jpg_mjpeg_interlaced = 0; 655 } 656 657 hc->codec_param[instance].disp_imm = params->display_delay_enable ? 1 : 0; 658 if (malone_format != MALONE_FMT_AVC) 659 hc->codec_param[instance].disp_imm = 0; 660 hc->codec_param[instance].dbglog_enable = 0; 661 iface->dbglog_desc.level = 0; 662 663 if (params->b_non_frame) 664 iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL; 665 else 666 iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL; 667 iface->stream_buff_info[instance].stream_buffer_threshold = 0; 668 iface->stream_buff_info[instance].stream_pic_input_count = 0; 669 670 return 0; 671 } 672 673 static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance) 674 { 675 struct malone_iface *iface = shared->iface; 676 677 if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL) 678 return true; 679 680 return false; 681 } 682 683 static int vpu_malone_update_params(struct vpu_shared_addr *shared, 684 u32 instance, 685 struct vpu_decode_params *params) 686 { 687 struct malone_iface *iface = shared->iface; 688 689 if (params->end_flag) 690 iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag; 691 params->end_flag = 0; 692 693 return 0; 694 } 695 696 int vpu_malone_set_decode_params(struct vpu_shared_addr *shared, 697 u32 instance, 698 struct vpu_decode_params *params, 699 u32 update) 700 { 701 if (!params) 702 return -EINVAL; 703 704 if (!update) 705 return vpu_malone_set_params(shared, instance, params); 706 else 707 return vpu_malone_update_params(shared, instance, params); 708 } 709 710 static struct vpu_pair malone_cmds[] = { 711 {VPU_CMD_ID_NOOP, VID_API_CMD_NULL}, 712 {VPU_CMD_ID_START, VID_API_CMD_START}, 713 {VPU_CMD_ID_STOP, VID_API_CMD_STOP}, 714 {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT}, 715 {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF}, 716 {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT}, 717 {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET}, 718 {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC}, 719 {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE}, 720 {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS}, 721 {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS}, 722 }; 723 724 static struct vpu_pair malone_msgs[] = { 725 {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE}, 726 {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE}, 727 {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED}, 728 {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE}, 729 {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST}, 730 {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED}, 731 {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND}, 732 {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE}, 733 {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND}, 734 {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED}, 735 {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY}, 736 {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF}, 737 {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF}, 738 {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW}, 739 {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR}, 740 {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM}, 741 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT}, 742 {VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED}, 743 {VPU_MSG_ID_DBG_MSG, VID_API_EVENT_DBG_MSG_DEC}, 744 }; 745 746 static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt, 747 struct vpu_fs_info *fs) 748 { 749 const u32 fs_type[] = { 750 [MEM_RES_FRAME] = 0, 751 [MEM_RES_MBI] = 1, 752 [MEM_RES_DCP] = 2, 753 }; 754 755 pkt->hdr.num = 7; 756 pkt->data[0] = fs->id | (fs->tag << 24); 757 pkt->data[1] = fs->luma_addr; 758 if (fs->type == MEM_RES_FRAME) { 759 /* 760 * if luma_addr equal to chroma_addr, 761 * means luma(plane[0]) and chromau(plane[1]) used the 762 * same fd -- usage of NXP codec2. Need to manually 763 * offset chroma addr. 764 */ 765 if (fs->luma_addr == fs->chroma_addr) 766 fs->chroma_addr = fs->luma_addr + fs->luma_size; 767 pkt->data[2] = fs->luma_addr + fs->luma_size / 2; 768 pkt->data[3] = fs->chroma_addr; 769 pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2; 770 pkt->data[5] = fs->bytesperline; 771 } else { 772 pkt->data[2] = fs->luma_size; 773 pkt->data[3] = 0; 774 pkt->data[4] = 0; 775 pkt->data[5] = 0; 776 } 777 pkt->data[6] = fs_type[fs->type]; 778 } 779 780 static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt, 781 struct vpu_fs_info *fs) 782 { 783 pkt->hdr.num = 1; 784 pkt->data[0] = fs->id | (fs->tag << 24); 785 } 786 787 static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt, 788 struct vpu_ts_info *info) 789 { 790 struct timespec64 ts = ns_to_timespec64(info->timestamp); 791 792 pkt->hdr.num = 3; 793 794 pkt->data[0] = ts.tv_sec; 795 pkt->data[1] = ts.tv_nsec; 796 pkt->data[2] = info->size; 797 } 798 799 int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data) 800 { 801 int ret; 802 803 ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id); 804 if (ret < 0) 805 return ret; 806 807 pkt->hdr.id = ret; 808 pkt->hdr.num = 0; 809 pkt->hdr.index = index; 810 811 switch (id) { 812 case VPU_CMD_ID_FS_ALLOC: 813 vpu_malone_pack_fs_alloc(pkt, data); 814 break; 815 case VPU_CMD_ID_FS_RELEASE: 816 vpu_malone_pack_fs_release(pkt, data); 817 break; 818 case VPU_CMD_ID_TIMESTAMP: 819 vpu_malone_pack_timestamp(pkt, data); 820 break; 821 } 822 823 pkt->hdr.index = index; 824 return 0; 825 } 826 827 int vpu_malone_convert_msg_id(u32 id) 828 { 829 return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id); 830 } 831 832 static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info) 833 { 834 u32 interlaced = info->progressive ? 0 : 1; 835 836 info->bytesperline[0] = 0; 837 info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt, 838 info->decoded_width, 839 info->decoded_height, 840 0, 841 info->stride, 842 interlaced, 843 &info->bytesperline[0]); 844 info->bytesperline[1] = 0; 845 info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt, 846 info->decoded_width, 847 info->decoded_height, 848 1, 849 info->stride, 850 interlaced, 851 &info->bytesperline[1]); 852 } 853 854 static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info) 855 { 856 u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT; 857 858 vpu_malone_fill_planes(info); 859 860 info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2; 861 info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI); 862 863 info->dcp_size = MALONE_DCP_SIZE_MAX; 864 if (chunks) { 865 u32 mb_num; 866 u32 mb_w; 867 u32 mb_h; 868 869 mb_w = DIV_ROUND_UP(info->decoded_width, 16); 870 mb_h = DIV_ROUND_UP(info->decoded_height, 16); 871 mb_num = mb_w * mb_h; 872 info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks; 873 info->dcp_size = clamp_t(u32, info->dcp_size, 874 MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX); 875 } 876 } 877 878 static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt, 879 struct vpu_dec_codec_info *info) 880 { 881 info->num_ref_frms = pkt->data[0]; 882 info->num_dpb_frms = pkt->data[1]; 883 info->num_dfe_area = pkt->data[2]; 884 info->progressive = pkt->data[3]; 885 info->width = pkt->data[5]; 886 info->height = pkt->data[4]; 887 info->decoded_width = pkt->data[12]; 888 info->decoded_height = pkt->data[11]; 889 info->frame_rate.numerator = 1000; 890 info->frame_rate.denominator = pkt->data[8]; 891 info->dsp_asp_ratio = pkt->data[9]; 892 info->level_idc = pkt->data[10]; 893 info->bit_depth_luma = pkt->data[13]; 894 info->bit_depth_chroma = pkt->data[14]; 895 info->chroma_fmt = pkt->data[15]; 896 info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]); 897 info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]); 898 info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]); 899 info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]); 900 info->vui_present = pkt->data[20]; 901 info->mvc_num_views = pkt->data[21]; 902 info->offset_x = pkt->data[23]; 903 info->offset_y = pkt->data[25]; 904 info->tag = pkt->data[27]; 905 if (info->bit_depth_luma > 8) 906 info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128; 907 else 908 info->pixfmt = V4L2_PIX_FMT_NV12M_8L128; 909 if (info->frame_rate.numerator && info->frame_rate.denominator) { 910 unsigned long n, d; 911 912 rational_best_approximation(info->frame_rate.numerator, 913 info->frame_rate.denominator, 914 info->frame_rate.numerator, 915 info->frame_rate.denominator, 916 &n, &d); 917 info->frame_rate.numerator = n; 918 info->frame_rate.denominator = d; 919 } 920 vpu_malone_init_seq_hdr(info); 921 } 922 923 static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt, 924 struct vpu_dec_pic_info *info) 925 { 926 info->id = pkt->data[7]; 927 info->luma = pkt->data[0]; 928 info->start = pkt->data[10]; 929 info->end = pkt->data[12]; 930 info->pic_size = pkt->data[11]; 931 info->stride = pkt->data[5]; 932 info->consumed_count = pkt->data[13]; 933 if (info->id == MALONE_SKIPPED_FRAME_ID) 934 info->skipped = 1; 935 else 936 info->skipped = 0; 937 } 938 939 static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt, 940 struct vpu_fs_info *info) 941 { 942 info->type = pkt->data[1]; 943 } 944 945 static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt, 946 struct vpu_fs_info *info) 947 { 948 info->id = pkt->data[0]; 949 info->type = pkt->data[1]; 950 info->not_displayed = pkt->data[2]; 951 } 952 953 static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt, 954 struct vpu_dec_pic_info *info) 955 { 956 struct timespec64 ts = { pkt->data[9], pkt->data[10] }; 957 958 info->id = pkt->data[0]; 959 info->luma = pkt->data[1]; 960 info->stride = pkt->data[3]; 961 if (info->id == MALONE_SKIPPED_FRAME_ID) 962 info->skipped = 1; 963 else 964 info->skipped = 0; 965 966 info->timestamp = timespec64_to_ns(&ts); 967 } 968 969 int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data) 970 { 971 if (!pkt || !data) 972 return -EINVAL; 973 974 switch (pkt->hdr.id) { 975 case VID_API_EVENT_SEQ_HDR_FOUND: 976 vpu_malone_unpack_seq_hdr(pkt, data); 977 break; 978 case VID_API_EVENT_PIC_DECODED: 979 vpu_malone_unpack_pic_info(pkt, data); 980 break; 981 case VID_API_EVENT_REQ_FRAME_BUFF: 982 vpu_malone_unpack_req_frame(pkt, data); 983 break; 984 case VID_API_EVENT_REL_FRAME_BUFF: 985 vpu_malone_unpack_rel_frame(pkt, data); 986 break; 987 case VID_API_EVENT_FRAME_BUFF_RDY: 988 vpu_malone_unpack_buff_rdy(pkt, data); 989 break; 990 } 991 992 return 0; 993 } 994 995 static const struct malone_padding_scode padding_scodes[] = { 996 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, 997 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, 998 {SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, 999 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, 1000 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, 1001 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}}, 1002 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, 1003 {SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, 1004 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, 1005 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, 1006 {SCODE_PADDING_EOS, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}}, 1007 {SCODE_PADDING_EOS, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}}, 1008 {SCODE_PADDING_EOS, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}}, 1009 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}}, 1010 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, 1011 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, 1012 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}}, 1013 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}}, 1014 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}}, 1015 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}}, 1016 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}}, 1017 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}}, 1018 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, 1019 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, 1020 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}}, 1021 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}}, 1022 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}}, 1023 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}}, 1024 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}}, 1025 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}}, 1026 }; 1027 1028 static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0}; 1029 1030 static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt) 1031 { 1032 const struct malone_padding_scode *s; 1033 int i; 1034 1035 for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) { 1036 s = &padding_scodes[i]; 1037 1038 if (s->scode_type == type && s->pixelformat == fmt) 1039 return s; 1040 } 1041 1042 if (type != SCODE_PADDING_BUFFLUSH) 1043 return &padding_scode_dft; 1044 1045 return NULL; 1046 } 1047 1048 static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer, 1049 struct vpu_malone_str_buffer __iomem *str_buf, 1050 u32 pixelformat, u32 scode_type) 1051 { 1052 u32 wptr; 1053 int size; 1054 int total_size = 0; 1055 const struct malone_padding_scode *ps; 1056 const u32 padding_size = 4096; 1057 int ret; 1058 1059 ps = get_padding_scode(scode_type, pixelformat); 1060 if (!ps) 1061 return -EINVAL; 1062 1063 wptr = readl(&str_buf->wptr); 1064 if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length) 1065 return -EINVAL; 1066 if (wptr == stream_buffer->phys + stream_buffer->length) 1067 wptr = stream_buffer->phys; 1068 size = ALIGN(wptr, 4) - wptr; 1069 if (size) 1070 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); 1071 total_size += size; 1072 1073 size = sizeof(ps->data); 1074 ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data); 1075 if (ret < 0) 1076 return -EINVAL; 1077 total_size += size; 1078 1079 size = padding_size - sizeof(ps->data); 1080 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size); 1081 total_size += size; 1082 1083 vpu_malone_update_wptr(str_buf, wptr); 1084 return total_size; 1085 } 1086 1087 int vpu_malone_add_scode(struct vpu_shared_addr *shared, 1088 u32 instance, 1089 struct vpu_buffer *stream_buffer, 1090 u32 pixelformat, 1091 u32 scode_type) 1092 { 1093 struct vpu_dec_ctrl *hc = shared->priv; 1094 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance]; 1095 int ret = -EINVAL; 1096 1097 switch (scode_type) { 1098 case SCODE_PADDING_EOS: 1099 case SCODE_PADDING_ABORT: 1100 case SCODE_PADDING_BUFFLUSH: 1101 ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type); 1102 break; 1103 default: 1104 break; 1105 } 1106 1107 return ret; 1108 } 1109 1110 #define MALONE_PAYLOAD_HEADER_SIZE 16 1111 #define MALONE_CODEC_VERSION_ID 0x1 1112 #define MALONE_CODEC_ID_VC1_SIMPLE 0x10 1113 #define MALONE_CODEC_ID_VC1_MAIN 0x11 1114 #define MALONE_CODEC_ID_ARV8 0x28 1115 #define MALONE_CODEC_ID_ARV9 0x29 1116 #define MALONE_CODEC_ID_VP6 0x36 1117 #define MALONE_CODEC_ID_VP8 0x36 1118 #define MALONE_CODEC_ID_DIVX3 0x38 1119 #define MALONE_CODEC_ID_SPK 0x39 1120 1121 #define MALONE_VP8_IVF_SEQ_HEADER_LEN 32 1122 #define MALONE_VP8_IVF_FRAME_HEADER_LEN 8 1123 1124 #define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85 1125 #define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5 1126 #define MALONE_VC1_RCV_NUM_FRAMES 0xFF 1127 #define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4 1128 #define MALONE_VC1_RCV_SEQ_HEADER_LEN 20 1129 #define MALONE_VC1_RCV_PIC_HEADER_LEN 4 1130 #define MALONE_VC1_NAL_HEADER_LEN 4 1131 #define MALONE_VC1_CONTAIN_NAL(data) (((data) & 0x00FFFFFF) == 0x00010000) 1132 1133 static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id, 1134 u32 buffer_size, u32 width, u32 height) 1135 { 1136 unsigned int payload_size; 1137 /* payload_size = buffer_size + itself_size(16) - start_code(4) */ 1138 payload_size = buffer_size + 12; 1139 1140 dst[0] = 0x00; 1141 dst[1] = 0x00; 1142 dst[2] = 0x01; 1143 dst[3] = scd_type; 1144 1145 /* length */ 1146 dst[4] = ((payload_size >> 16) & 0xff); 1147 dst[5] = ((payload_size >> 8) & 0xff); 1148 dst[6] = 0x4e; 1149 dst[7] = ((payload_size >> 0) & 0xff); 1150 1151 /* Codec ID and Version */ 1152 dst[8] = codec_id; 1153 dst[9] = MALONE_CODEC_VERSION_ID; 1154 1155 /* width */ 1156 dst[10] = ((width >> 8) & 0xff); 1157 dst[11] = ((width >> 0) & 0xff); 1158 dst[12] = 0x58; 1159 1160 /* height */ 1161 dst[13] = ((height >> 8) & 0xff); 1162 dst[14] = ((height >> 0) & 0xff); 1163 dst[15] = 0x50; 1164 } 1165 1166 static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height) 1167 { 1168 /* 0-3byte signature "DKIF" */ 1169 dst[0] = 0x44; 1170 dst[1] = 0x4b; 1171 dst[2] = 0x49; 1172 dst[3] = 0x46; 1173 /* 4-5byte version: should be 0*/ 1174 dst[4] = 0x00; 1175 dst[5] = 0x00; 1176 /* 6-7 length of Header */ 1177 dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN; 1178 dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8; 1179 /* 8-11 VP8 fourcc */ 1180 dst[8] = 0x56; 1181 dst[9] = 0x50; 1182 dst[10] = 0x38; 1183 dst[11] = 0x30; 1184 /* 12-13 width in pixels */ 1185 dst[12] = width; 1186 dst[13] = width >> 8; 1187 /* 14-15 height in pixels */ 1188 dst[14] = height; 1189 dst[15] = height >> 8; 1190 /* 16-19 frame rate */ 1191 dst[16] = 0xe8; 1192 dst[17] = 0x03; 1193 dst[18] = 0x00; 1194 dst[19] = 0x00; 1195 /* 20-23 time scale */ 1196 dst[20] = 0x01; 1197 dst[21] = 0x00; 1198 dst[22] = 0x00; 1199 dst[23] = 0x00; 1200 /* 24-27 number frames */ 1201 dst[24] = 0xdf; 1202 dst[25] = 0xf9; 1203 dst[26] = 0x09; 1204 dst[27] = 0x00; 1205 /* 28-31 reserved */ 1206 } 1207 1208 static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size) 1209 { 1210 /* 1211 * firmware just parse 64-bit timestamp(8 bytes). 1212 * As not transfer timestamp to firmware, use default value(ZERO). 1213 * No need to do anything here 1214 */ 1215 } 1216 1217 static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height) 1218 { 1219 u32 frames = MALONE_VC1_RCV_NUM_FRAMES; 1220 u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE; 1221 1222 /* 0-2 Number of frames, used default value 0xFF */ 1223 dst[0] = frames; 1224 dst[1] = frames >> 8; 1225 dst[2] = frames >> 16; 1226 1227 /* 3 RCV version, used V1 */ 1228 dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION; 1229 1230 /* 4-7 extension data size */ 1231 dst[4] = ext_data_size; 1232 dst[5] = ext_data_size >> 8; 1233 dst[6] = ext_data_size >> 16; 1234 dst[7] = ext_data_size >> 24; 1235 /* 8-11 extension data */ 1236 dst[8] = src[0]; 1237 dst[9] = src[1]; 1238 dst[10] = src[2]; 1239 dst[11] = src[3]; 1240 1241 /* height */ 1242 dst[12] = height; 1243 dst[13] = (height >> 8) & 0xff; 1244 dst[14] = (height >> 16) & 0xff; 1245 dst[15] = (height >> 24) & 0xff; 1246 /* width */ 1247 dst[16] = width; 1248 dst[17] = (width >> 8) & 0xff; 1249 dst[18] = (width >> 16) & 0xff; 1250 dst[19] = (width >> 24) & 0xff; 1251 } 1252 1253 static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size) 1254 { 1255 dst[0] = buffer_size; 1256 dst[1] = buffer_size >> 8; 1257 dst[2] = buffer_size >> 16; 1258 dst[3] = buffer_size >> 24; 1259 } 1260 1261 static void create_vc1_nal_pichdr(u8 *dst) 1262 { 1263 /* need insert nal header: special ID */ 1264 dst[0] = 0x0; 1265 dst[1] = 0x0; 1266 dst[2] = 0x01; 1267 dst[3] = 0x0D; 1268 } 1269 1270 static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) 1271 { 1272 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; 1273 int ret; 1274 1275 set_payload_hdr(hdr, 1276 SCODE_SEQUENCE, 1277 codec_id, 1278 ext_size, 1279 scode->inst->out_format.width, 1280 scode->inst->out_format.height); 1281 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1282 &scode->wptr, 1283 sizeof(hdr), 1284 hdr); 1285 if (ret < 0) 1286 return ret; 1287 return sizeof(hdr); 1288 } 1289 1290 static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size) 1291 { 1292 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE]; 1293 int ret; 1294 1295 set_payload_hdr(hdr, 1296 SCODE_PICTURE, 1297 codec_id, 1298 ext_size + vb2_get_plane_payload(scode->vb, 0), 1299 scode->inst->out_format.width, 1300 scode->inst->out_format.height); 1301 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1302 &scode->wptr, 1303 sizeof(hdr), 1304 hdr); 1305 if (ret < 0) 1306 return ret; 1307 return sizeof(hdr); 1308 } 1309 1310 static int vpu_malone_insert_scode_vc1_g_seq(struct malone_scode_t *scode) 1311 { 1312 if (!scode->inst->total_input_count) 1313 return 0; 1314 if (vpu_vb_is_codecconfig(to_vb2_v4l2_buffer(scode->vb))) 1315 scode->need_data = 0; 1316 return 0; 1317 } 1318 1319 static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode) 1320 { 1321 struct vb2_v4l2_buffer *vbuf; 1322 u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN]; 1323 u32 *data = NULL; 1324 int ret; 1325 1326 vbuf = to_vb2_v4l2_buffer(scode->vb); 1327 data = vb2_plane_vaddr(scode->vb, 0); 1328 1329 if (scode->inst->total_input_count == 0 || vpu_vb_is_codecconfig(vbuf)) 1330 return 0; 1331 if (MALONE_VC1_CONTAIN_NAL(*data)) 1332 return 0; 1333 1334 create_vc1_nal_pichdr(nal_hdr); 1335 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1336 &scode->wptr, 1337 sizeof(nal_hdr), 1338 nal_hdr); 1339 if (ret < 0) 1340 return ret; 1341 return sizeof(nal_hdr); 1342 } 1343 1344 static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode) 1345 { 1346 int ret; 1347 int size = 0; 1348 u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN]; 1349 1350 if (vpu_vb_is_codecconfig(to_vb2_v4l2_buffer(scode->vb))) 1351 scode->need_data = 0; 1352 if (scode->inst->total_input_count) 1353 return 0; 1354 scode->need_data = 0; 1355 1356 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr)); 1357 if (ret < 0) 1358 return ret; 1359 size = ret; 1360 1361 set_vc1_rcv_seqhdr(rcv_seqhdr, 1362 vb2_plane_vaddr(scode->vb, 0), 1363 scode->inst->out_format.width, 1364 scode->inst->out_format.height); 1365 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1366 &scode->wptr, 1367 sizeof(rcv_seqhdr), 1368 rcv_seqhdr); 1369 1370 if (ret < 0) 1371 return ret; 1372 size += sizeof(rcv_seqhdr); 1373 return size; 1374 } 1375 1376 static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode) 1377 { 1378 int ret; 1379 int size = 0; 1380 u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN]; 1381 1382 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE, 1383 sizeof(rcv_pichdr)); 1384 if (ret < 0) 1385 return ret; 1386 size = ret; 1387 1388 set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0)); 1389 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1390 &scode->wptr, 1391 sizeof(rcv_pichdr), 1392 rcv_pichdr); 1393 if (ret < 0) 1394 return ret; 1395 size += sizeof(rcv_pichdr); 1396 return size; 1397 } 1398 1399 static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode) 1400 { 1401 int ret; 1402 int size = 0; 1403 u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN]; 1404 1405 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); 1406 if (ret < 0) 1407 return ret; 1408 size = ret; 1409 1410 set_vp8_ivf_seqhdr(ivf_hdr, 1411 scode->inst->out_format.width, 1412 scode->inst->out_format.height); 1413 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1414 &scode->wptr, 1415 sizeof(ivf_hdr), 1416 ivf_hdr); 1417 if (ret < 0) 1418 return ret; 1419 size += sizeof(ivf_hdr); 1420 1421 return size; 1422 } 1423 1424 static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode) 1425 { 1426 int ret; 1427 int size = 0; 1428 u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0}; 1429 1430 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr)); 1431 if (ret < 0) 1432 return ret; 1433 size = ret; 1434 1435 set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0)); 1436 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer, 1437 &scode->wptr, 1438 sizeof(ivf_hdr), 1439 ivf_hdr); 1440 if (ret < 0) 1441 return ret; 1442 size += sizeof(ivf_hdr); 1443 1444 return size; 1445 } 1446 1447 static int vpu_malone_insert_scode_spk_seq(struct malone_scode_t *scode) 1448 { 1449 return vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_SPK, 0); 1450 } 1451 1452 static int vpu_malone_insert_scode_spk_pic(struct malone_scode_t *scode) 1453 { 1454 return vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_SPK, 0); 1455 } 1456 1457 static const struct malone_scode_handler scode_handlers[] = { 1458 { 1459 /* fix me, need to swap return operation after gstreamer swap */ 1460 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L, 1461 .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq, 1462 .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic, 1463 }, 1464 { 1465 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G, 1466 .insert_scode_seq = vpu_malone_insert_scode_vc1_g_seq, 1467 .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic, 1468 }, 1469 { 1470 .pixelformat = V4L2_PIX_FMT_VP8, 1471 .insert_scode_seq = vpu_malone_insert_scode_vp8_seq, 1472 .insert_scode_pic = vpu_malone_insert_scode_vp8_pic, 1473 }, 1474 { 1475 .pixelformat = V4L2_PIX_FMT_SPK, 1476 .insert_scode_seq = vpu_malone_insert_scode_spk_seq, 1477 .insert_scode_pic = vpu_malone_insert_scode_spk_pic, 1478 }, 1479 }; 1480 1481 static const struct malone_scode_handler *get_scode_handler(u32 pixelformat) 1482 { 1483 int i; 1484 1485 for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) { 1486 if (scode_handlers[i].pixelformat == pixelformat) 1487 return &scode_handlers[i]; 1488 } 1489 1490 return NULL; 1491 } 1492 1493 static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type) 1494 { 1495 const struct malone_scode_handler *handler; 1496 int ret = 0; 1497 1498 if (!scode || !scode->inst || !scode->vb) 1499 return 0; 1500 1501 scode->need_data = 1; 1502 handler = get_scode_handler(scode->inst->out_format.pixfmt); 1503 if (!handler) 1504 return 0; 1505 1506 switch (type) { 1507 case SCODE_SEQUENCE: 1508 if (handler->insert_scode_seq) 1509 ret = handler->insert_scode_seq(scode); 1510 break; 1511 case SCODE_PICTURE: 1512 if (handler->insert_scode_pic) 1513 ret = handler->insert_scode_pic(scode); 1514 break; 1515 default: 1516 break; 1517 } 1518 1519 return ret; 1520 } 1521 1522 static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf, 1523 struct vpu_inst *inst, struct vb2_buffer *vb, 1524 u32 disp_imm) 1525 { 1526 struct malone_scode_t scode; 1527 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1528 u32 wptr = readl(&str_buf->wptr); 1529 int size = 0; 1530 int ret = 0; 1531 1532 /*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/ 1533 scode.inst = inst; 1534 scode.vb = vb; 1535 scode.wptr = wptr; 1536 scode.need_data = 1; 1537 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf)) 1538 ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE); 1539 1540 if (ret < 0) 1541 return -ENOMEM; 1542 size += ret; 1543 wptr = scode.wptr; 1544 if (!scode.need_data) { 1545 vpu_malone_update_wptr(str_buf, wptr); 1546 return size; 1547 } 1548 1549 ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE); 1550 if (ret < 0) 1551 return -ENOMEM; 1552 size += ret; 1553 wptr = scode.wptr; 1554 1555 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, 1556 &wptr, 1557 vb2_get_plane_payload(vb, 0), 1558 vb2_plane_vaddr(vb, 0)); 1559 if (ret < 0) 1560 return -ENOMEM; 1561 size += vb2_get_plane_payload(vb, 0); 1562 1563 vpu_malone_update_wptr(str_buf, wptr); 1564 1565 if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) { 1566 ret = vpu_malone_add_scode(inst->core->iface, 1567 inst->id, 1568 &inst->stream_buffer, 1569 inst->out_format.pixfmt, 1570 SCODE_PADDING_BUFFLUSH); 1571 if (ret < 0) 1572 return ret; 1573 size += ret; 1574 } 1575 1576 return size; 1577 } 1578 1579 static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf, 1580 struct vpu_inst *inst, struct vb2_buffer *vb) 1581 { 1582 u32 wptr = readl(&str_buf->wptr); 1583 int ret = 0; 1584 1585 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer, 1586 &wptr, 1587 vb2_get_plane_payload(vb, 0), 1588 vb2_plane_vaddr(vb, 0)); 1589 if (ret < 0) 1590 return -ENOMEM; 1591 1592 vpu_malone_update_wptr(str_buf, wptr); 1593 1594 return ret; 1595 } 1596 1597 static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size) 1598 { 1599 struct vpu_ts_info info; 1600 1601 memset(&info, 0, sizeof(info)); 1602 info.timestamp = timestamp; 1603 info.size = size; 1604 1605 return vpu_session_fill_timestamp(inst, &info); 1606 } 1607 1608 int vpu_malone_input_frame(struct vpu_shared_addr *shared, 1609 struct vpu_inst *inst, struct vb2_buffer *vb) 1610 { 1611 struct vpu_dec_ctrl *hc = shared->priv; 1612 struct vb2_v4l2_buffer *vbuf; 1613 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id]; 1614 u32 disp_imm = hc->codec_param[inst->id].disp_imm; 1615 u32 size; 1616 int ret; 1617 1618 if (vpu_malone_is_non_frame_mode(shared, inst->id)) 1619 ret = vpu_malone_input_stream_data(str_buf, inst, vb); 1620 else 1621 ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm); 1622 if (ret < 0) 1623 return ret; 1624 size = ret; 1625 1626 /* 1627 * if buffer only contain codec data, and the timestamp is invalid, 1628 * don't put the invalid timestamp to resync 1629 * merge the data to next frame 1630 */ 1631 vbuf = to_vb2_v4l2_buffer(vb); 1632 if (vpu_vb_is_codecconfig(vbuf)) { 1633 inst->extra_size += size; 1634 return 0; 1635 } 1636 if (inst->extra_size) { 1637 size += inst->extra_size; 1638 inst->extra_size = 0; 1639 } 1640 1641 ret = vpu_malone_input_ts(inst, vb->timestamp, size); 1642 if (ret) 1643 return ret; 1644 1645 return 0; 1646 } 1647 1648 static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance) 1649 { 1650 struct malone_iface *iface = shared->iface; 1651 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1652 u32 size = desc->end - desc->start; 1653 u32 rptr = desc->rptr; 1654 u32 wptr = desc->wptr; 1655 u32 used; 1656 1657 if (!size) 1658 return true; 1659 1660 used = (wptr + size - rptr) % size; 1661 if (used < (size / 2)) 1662 return true; 1663 1664 return false; 1665 } 1666 1667 bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance) 1668 { 1669 u32 cnt = 0; 1670 1671 while (!vpu_malone_check_ready(shared, instance)) { 1672 if (cnt > 30) 1673 return false; 1674 mdelay(1); 1675 cnt++; 1676 } 1677 return true; 1678 } 1679 1680 int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance) 1681 { 1682 if (!vpu_malone_is_ready(shared, instance)) 1683 return -EINVAL; 1684 1685 return 0; 1686 } 1687 1688 int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance) 1689 { 1690 struct malone_iface *iface = shared->iface; 1691 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1692 1693 desc->wptr++; 1694 if (desc->wptr == desc->end) 1695 desc->wptr = desc->start; 1696 1697 return 0; 1698 } 1699 1700 int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance) 1701 { 1702 struct malone_iface *iface = shared->iface; 1703 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance]; 1704 1705 desc->wptr = desc->rptr; 1706 if (desc->wptr == desc->end) 1707 desc->wptr = desc->start; 1708 1709 return 0; 1710 } 1711 1712 u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared) 1713 { 1714 struct malone_iface *iface = shared->iface; 1715 1716 return iface->max_streams; 1717 } 1718