xref: /linux/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml (revision c7546e2c3cb739a3c1a2f5acaf9bb629d401afe5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on IPQ5332
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on IPQ5332.
15
16  See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
17
18allOf:
19  - $ref: qcom,gcc.yaml#
20
21properties:
22  compatible:
23    const: qcom,ipq5332-gcc
24
25  clocks:
26    items:
27      - description: Board XO clock source
28      - description: Sleep clock source
29      - description: PCIE 2lane PHY pipe clock source
30      - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
31      - description: USB PCIE wrapper pipe clock source
32
33  '#power-domain-cells': false
34  '#interconnect-cells':
35    const: 1
36
37required:
38  - compatible
39  - clocks
40
41unevaluatedProperties: false
42
43examples:
44  - |
45    clock-controller@1800000 {
46      compatible = "qcom,ipq5332-gcc";
47      reg = <0x01800000 0x80000>;
48      clocks = <&xo_board>,
49               <&sleep_clk>,
50               <&pcie_2lane_phy_pipe_clk>,
51               <&pcie_2lane_phy_pipe_clk_x1>,
52               <&usb_pcie_wrapper_pipe_clk>;
53      #clock-cells = <1>;
54      #reset-cells = <1>;
55    };
56...
57