xref: /linux/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi (revision c7546e2c3cb739a3c1a2f5acaf9bb629d401afe5) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SMARC SOM common parts
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/ {
13	aliases {
14		ethernet0 = &eth0;
15		ethernet1 = &eth1;
16	};
17
18	chosen {
19		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
20	};
21
22	memory@48000000 {
23		device_type = "memory";
24		/* first 128MB is reserved for secure area. */
25		reg = <0x0 0x48000000 0x0 0x38000000>;
26	};
27
28	reg_1p8v: regulator-1p8v {
29		compatible = "regulator-fixed";
30		regulator-name = "fixed-1.8V";
31		regulator-min-microvolt = <1800000>;
32		regulator-max-microvolt = <1800000>;
33		regulator-boot-on;
34		regulator-always-on;
35	};
36
37	reg_3p3v: regulator-3p3v {
38		compatible = "regulator-fixed";
39		regulator-name = "fixed-3.3V";
40		regulator-min-microvolt = <3300000>;
41		regulator-max-microvolt = <3300000>;
42		regulator-boot-on;
43		regulator-always-on;
44	};
45
46#if !(SW_SW0_DEV_SEL)
47	vccq_sdhi0: regulator-vccq-sdhi0 {
48		compatible = "regulator-gpio";
49
50		regulator-name = "SDHI0 VccQ";
51		regulator-min-microvolt = <1800000>;
52		regulator-max-microvolt = <3300000>;
53		states = <3300000 1>, <1800000 0>;
54		regulator-boot-on;
55		gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
56		regulator-always-on;
57	};
58#endif
59};
60
61#if (SW_SW0_DEV_SEL)
62&adc {
63	pinctrl-0 = <&adc_pins>;
64	pinctrl-names = "default";
65	status = "okay";
66};
67#endif
68
69#if (!SW_ET0_EN_N)
70&eth0 {
71	pinctrl-0 = <&eth0_pins>;
72	pinctrl-names = "default";
73	phy-handle = <&phy0>;
74	phy-mode = "rgmii-id";
75	status = "okay";
76
77	phy0: ethernet-phy@7 {
78		compatible = "ethernet-phy-id0022.1640",
79			     "ethernet-phy-ieee802.3-c22";
80		reg = <7>;
81		interrupt-parent = <&irqc>;
82		interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
83		rxc-skew-psec = <2400>;
84		txc-skew-psec = <2400>;
85		rxdv-skew-psec = <0>;
86		txen-skew-psec = <0>;
87		rxd0-skew-psec = <0>;
88		rxd1-skew-psec = <0>;
89		rxd2-skew-psec = <0>;
90		rxd3-skew-psec = <0>;
91		txd0-skew-psec = <0>;
92		txd1-skew-psec = <0>;
93		txd2-skew-psec = <0>;
94		txd3-skew-psec = <0>;
95	};
96};
97#endif
98
99&eth1 {
100	pinctrl-0 = <&eth1_pins>;
101	pinctrl-names = "default";
102	phy-handle = <&phy1>;
103	phy-mode = "rgmii-id";
104	status = "okay";
105
106	phy1: ethernet-phy@7 {
107		compatible = "ethernet-phy-id0022.1640",
108			     "ethernet-phy-ieee802.3-c22";
109		reg = <7>;
110		interrupt-parent = <&irqc>;
111		interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
112		rxc-skew-psec = <2400>;
113		txc-skew-psec = <2400>;
114		rxdv-skew-psec = <0>;
115		txen-skew-psec = <0>;
116		rxd0-skew-psec = <0>;
117		rxd1-skew-psec = <0>;
118		rxd2-skew-psec = <0>;
119		rxd3-skew-psec = <0>;
120		txd0-skew-psec = <0>;
121		txd1-skew-psec = <0>;
122		txd2-skew-psec = <0>;
123		txd3-skew-psec = <0>;
124	};
125};
126
127&extal_clk {
128	clock-frequency = <24000000>;
129};
130
131&ostm1 {
132	status = "okay";
133};
134
135&ostm2 {
136	status = "okay";
137};
138
139&pinctrl {
140	adc_pins: adc {
141		pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */
142	};
143
144	eth0_pins: eth0 {
145		txc {
146			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
147			power-source = <1800>;
148			output-enable;
149		};
150
151		mux {
152			pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
153				 <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
154				 <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
155				 <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
156				 <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
157				 <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
158				 <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
159				 <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
160				 <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
161				 <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
162				 <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
163				 <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
164				 <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
165				 <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
166			power-source = <1800>;
167		};
168
169		irq {
170			pinmux = <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
171		};
172	};
173
174	eth1_pins: eth1 {
175		txc {
176			pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
177			power-source = <1800>;
178			output-enable;
179		};
180
181		mux {
182			pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
183				 <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
184				 <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
185				 <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
186				 <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
187				 <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
188				 <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
189				 <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
190				 <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
191				 <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
192				 <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
193				 <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
194				 <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
195				 <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
196			power-source = <1800>;
197		};
198
199		irq {
200			pinmux = <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
201		};
202	};
203
204	sdhi0_emmc_pins: sd0emmc {
205		sd0_emmc_data {
206			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
207			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
208			power-source = <1800>;
209		};
210
211		sd0_emmc_ctrl {
212			pins = "SD0_CLK", "SD0_CMD";
213			power-source = <1800>;
214		};
215
216		sd0_emmc_rst {
217			pins = "SD0_RST#";
218			power-source = <1800>;
219		};
220	};
221
222	sdhi0_pins: sd0 {
223		sd0_data {
224			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
225			power-source = <3300>;
226		};
227
228		sd0_ctrl {
229			pins = "SD0_CLK", "SD0_CMD";
230			power-source = <3300>;
231		};
232
233		sd0_mux {
234			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
235		};
236	};
237
238	sdhi0_pins_uhs: sd0_uhs {
239		sd0_data_uhs {
240			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
241			power-source = <1800>;
242		};
243
244		sd0_ctrl_uhs {
245			pins = "SD0_CLK", "SD0_CMD";
246			power-source = <1800>;
247		};
248
249		sd0_mux_uhs {
250			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
251		};
252	};
253};
254
255#if (SW_SW0_DEV_SEL)
256&sdhi0 {
257	pinctrl-0 = <&sdhi0_emmc_pins>;
258	pinctrl-1 = <&sdhi0_emmc_pins>;
259	pinctrl-names = "default", "state_uhs";
260
261	vmmc-supply = <&reg_3p3v>;
262	vqmmc-supply = <&reg_1p8v>;
263	bus-width = <8>;
264	mmc-hs200-1_8v;
265	non-removable;
266	fixed-emmc-driver-type = <1>;
267	status = "okay";
268};
269#else
270&sdhi0 {
271	pinctrl-0 = <&sdhi0_pins>;
272	pinctrl-1 = <&sdhi0_pins_uhs>;
273	pinctrl-names = "default", "state_uhs";
274
275	vmmc-supply = <&reg_3p3v>;
276	vqmmc-supply = <&vccq_sdhi0>;
277	bus-width = <4>;
278	sd-uhs-sdr50;
279	sd-uhs-sdr104;
280	status = "okay";
281};
282#endif
283
284&wdt0 {
285	status = "okay";
286	timeout-sec = <60>;
287};
288