xref: /linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision c7546e2c3cb739a3c1a2f5acaf9bb629d401afe5) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Paul Walmsley  <paul.walmsley@sifive.com>
49  - Palmer Dabbelt <palmer@dabbelt.com>
50
51properties:
52  compatible:
53    oneOf:
54      - items:
55          - enum:
56              - renesas,r9a07g043-plic
57          - const: andestech,nceplic100
58      - items:
59          - enum:
60              - canaan,k210-plic
61              - sifive,fu540-c000-plic
62              - starfive,jh7100-plic
63              - starfive,jh7110-plic
64          - const: sifive,plic-1.0.0
65      - items:
66          - enum:
67              - allwinner,sun20i-d1-plic
68              - sophgo,cv1800b-plic
69              - sophgo,cv1812h-plic
70              - sophgo,sg2002-plic
71              - sophgo,sg2042-plic
72              - thead,th1520-plic
73          - const: thead,c900-plic
74      - items:
75          - const: sifive,plic-1.0.0
76          - const: riscv,plic0
77        deprecated: true
78        description: For the QEMU virt machine only
79
80  reg:
81    maxItems: 1
82
83  '#address-cells':
84    const: 0
85
86  '#interrupt-cells': true
87
88  interrupt-controller: true
89
90  interrupts-extended:
91    minItems: 1
92    maxItems: 15872
93    description:
94      Specifies which contexts are connected to the PLIC, with "-1" specifying
95      that a context is not present. Each node pointed to should be a
96      riscv,cpu-intc node, which has a riscv node as parent.
97
98  riscv,ndev:
99    $ref: /schemas/types.yaml#/definitions/uint32
100    description:
101      Specifies how many external interrupts are supported by this controller.
102
103  clocks: true
104
105  power-domains: true
106
107  resets: true
108
109required:
110  - compatible
111  - '#address-cells'
112  - '#interrupt-cells'
113  - interrupt-controller
114  - reg
115  - interrupts-extended
116  - riscv,ndev
117
118allOf:
119  - if:
120      properties:
121        compatible:
122          contains:
123            enum:
124              - andestech,nceplic100
125              - thead,c900-plic
126
127    then:
128      properties:
129        '#interrupt-cells':
130          const: 2
131
132    else:
133      properties:
134        '#interrupt-cells':
135          const: 1
136
137  - if:
138      properties:
139        compatible:
140          contains:
141            const: renesas,r9a07g043-plic
142
143    then:
144      properties:
145        clocks:
146          maxItems: 1
147
148        power-domains:
149          maxItems: 1
150
151        resets:
152          maxItems: 1
153
154      required:
155        - clocks
156        - power-domains
157        - resets
158
159additionalProperties: false
160
161examples:
162  - |
163    plic: interrupt-controller@c000000 {
164      #address-cells = <0>;
165      #interrupt-cells = <1>;
166      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
167      interrupt-controller;
168      interrupts-extended = <&cpu0_intc 11>,
169                            <&cpu1_intc 11>, <&cpu1_intc 9>,
170                            <&cpu2_intc 11>, <&cpu2_intc 9>,
171                            <&cpu3_intc 11>, <&cpu3_intc 9>,
172                            <&cpu4_intc 11>, <&cpu4_intc 9>;
173      reg = <0xc000000 0x4000000>;
174      riscv,ndev = <10>;
175    };
176