1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 22 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 23 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 24 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 #interrupt-cells = <3>; 29 interrupt-controller; 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: bus@100000 { 46 compatible = "simple-bus"; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x00 0x00 0x00100000 0x20000>; 50 51 phy_gmii_sel: phy@4044 { 52 compatible = "ti,am654-phy-gmii-sel"; 53 reg = <0x4044 0x8>; 54 #phy-cells = <1>; 55 }; 56 57 epwm_tbclk: clock-controller@4130 { 58 compatible = "ti,am62-epwm-tbclk"; 59 reg = <0x4130 0x4>; 60 #clock-cells = <1>; 61 }; 62 63 audio_refclk0: clock-controller@82e0 { 64 compatible = "ti,am62-audio-refclk"; 65 reg = <0x82e0 0x4>; 66 clocks = <&k3_clks 157 0>; 67 assigned-clocks = <&k3_clks 157 0>; 68 assigned-clock-parents = <&k3_clks 157 8>; 69 #clock-cells = <0>; 70 }; 71 72 audio_refclk1: clock-controller@82e4 { 73 compatible = "ti,am62-audio-refclk"; 74 reg = <0x82e4 0x4>; 75 clocks = <&k3_clks 157 10>; 76 assigned-clocks = <&k3_clks 157 10>; 77 assigned-clock-parents = <&k3_clks 157 18>; 78 #clock-cells = <0>; 79 }; 80 }; 81 82 dmss: bus@48000000 { 83 compatible = "simple-bus"; 84 #address-cells = <2>; 85 #size-cells = <2>; 86 dma-ranges; 87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 88 89 ti,sci-dev-id = <25>; 90 91 secure_proxy_main: mailbox@4d000000 { 92 compatible = "ti,am654-secure-proxy"; 93 reg = <0x00 0x4d000000 0x00 0x80000>, 94 <0x00 0x4a600000 0x00 0x80000>, 95 <0x00 0x4a400000 0x00 0x80000>; 96 reg-names = "target_data", "rt", "scfg"; 97 #mbox-cells = <1>; 98 interrupt-names = "rx_012"; 99 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 100 }; 101 102 inta_main_dmss: interrupt-controller@48000000 { 103 compatible = "ti,sci-inta"; 104 reg = <0x00 0x48000000 0x00 0x100000>; 105 #interrupt-cells = <0>; 106 interrupt-controller; 107 interrupt-parent = <&gic500>; 108 msi-controller; 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <28>; 111 ti,interrupt-ranges = <6 70 34>; 112 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 113 }; 114 115 main_bcdma: dma-controller@485c0100 { 116 compatible = "ti,am64-dmss-bcdma"; 117 reg = <0x00 0x485c0100 0x00 0x100>, 118 <0x00 0x4c000000 0x00 0x20000>, 119 <0x00 0x4a820000 0x00 0x20000>, 120 <0x00 0x4aa40000 0x00 0x20000>, 121 <0x00 0x4bc00000 0x00 0x100000>, 122 <0x00 0x48600000 0x00 0x8000>, 123 <0x00 0x484a4000 0x00 0x2000>, 124 <0x00 0x484c2000 0x00 0x2000>, 125 <0x00 0x48420000 0x00 0x2000>; 126 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 127 "ring", "tchan", "rchan", "bchan"; 128 msi-parent = <&inta_main_dmss>; 129 #dma-cells = <3>; 130 ti,sci = <&dmsc>; 131 ti,sci-dev-id = <26>; 132 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 133 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 134 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 135 }; 136 137 main_pktdma: dma-controller@485c0000 { 138 compatible = "ti,am64-dmss-pktdma"; 139 reg = <0x00 0x485c0000 0x00 0x100>, 140 <0x00 0x4a800000 0x00 0x20000>, 141 <0x00 0x4aa00000 0x00 0x20000>, 142 <0x00 0x4b800000 0x00 0x200000>, 143 <0x00 0x485e0000 0x00 0x10000>, 144 <0x00 0x484a0000 0x00 0x2000>, 145 <0x00 0x484c0000 0x00 0x2000>, 146 <0x00 0x48430000 0x00 0x1000>; 147 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 148 "ring", "tchan", "rchan", "rflow"; 149 msi-parent = <&inta_main_dmss>; 150 #dma-cells = <2>; 151 ti,sci = <&dmsc>; 152 ti,sci-dev-id = <30>; 153 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 154 <0x24>, /* CPSW_TX_CHAN */ 155 <0x25>, /* SAUL_TX_0_CHAN */ 156 <0x26>; /* SAUL_TX_1_CHAN */ 157 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 158 <0x11>, /* RING_CPSW_TX_CHAN */ 159 <0x12>, /* RING_SAUL_TX_0_CHAN */ 160 <0x13>; /* RING_SAUL_TX_1_CHAN */ 161 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 162 <0x2b>, /* CPSW_RX_CHAN */ 163 <0x2d>, /* SAUL_RX_0_CHAN */ 164 <0x2f>, /* SAUL_RX_1_CHAN */ 165 <0x31>, /* SAUL_RX_2_CHAN */ 166 <0x33>; /* SAUL_RX_3_CHAN */ 167 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 168 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 169 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 170 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 171 }; 172 }; 173 174 dmss_csi: bus@4e000000 { 175 compatible = "simple-bus"; 176 #address-cells = <2>; 177 #size-cells = <2>; 178 dma-ranges; 179 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>; 180 181 ti,sci-dev-id = <198>; 182 183 inta_main_dmss_csi: interrupt-controller@4e0a0000 { 184 compatible = "ti,sci-inta"; 185 reg = <0x00 0x4e0a0000 0x00 0x8000>; 186 #interrupt-cells = <0>; 187 interrupt-controller; 188 interrupt-parent = <&gic500>; 189 msi-controller; 190 ti,sci = <&dmsc>; 191 ti,sci-dev-id = <200>; 192 ti,interrupt-ranges = <0 237 8>; 193 ti,unmapped-event-sources = <&main_bcdma_csi>; 194 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 195 }; 196 197 main_bcdma_csi: dma-controller@4e230000 { 198 compatible = "ti,am62a-dmss-bcdma-csirx"; 199 reg = <0x00 0x4e230000 0x00 0x100>, 200 <0x00 0x4e180000 0x00 0x8000>, 201 <0x00 0x4e100000 0x00 0x10000>; 202 reg-names = "gcfg", "rchanrt", "ringrt"; 203 msi-parent = <&inta_main_dmss_csi>; 204 #dma-cells = <3>; 205 ti,sci = <&dmsc>; 206 ti,sci-dev-id = <199>; 207 ti,sci-rm-range-rchan = <0x21>; 208 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 209 }; 210 }; 211 212 dmsc: system-controller@44043000 { 213 compatible = "ti,k2g-sci"; 214 reg = <0x00 0x44043000 0x00 0xfe0>; 215 reg-names = "debug_messages"; 216 ti,host-id = <12>; 217 mbox-names = "rx", "tx"; 218 mboxes = <&secure_proxy_main 12>, 219 <&secure_proxy_main 13>; 220 221 k3_pds: power-controller { 222 compatible = "ti,sci-pm-domain"; 223 #power-domain-cells = <2>; 224 }; 225 226 k3_clks: clock-controller { 227 compatible = "ti,k2g-sci-clk"; 228 #clock-cells = <2>; 229 }; 230 231 k3_reset: reset-controller { 232 compatible = "ti,sci-reset"; 233 #reset-cells = <2>; 234 }; 235 }; 236 237 crypto: crypto@40900000 { 238 compatible = "ti,am62-sa3ul"; 239 reg = <0x00 0x40900000 0x00 0x1200>; 240 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 241 <&main_pktdma 0x7507 0>; 242 dma-names = "tx", "rx1", "rx2"; 243 }; 244 245 secure_proxy_sa3: mailbox@43600000 { 246 compatible = "ti,am654-secure-proxy"; 247 #mbox-cells = <1>; 248 reg-names = "target_data", "rt", "scfg"; 249 reg = <0x00 0x43600000 0x00 0x10000>, 250 <0x00 0x44880000 0x00 0x20000>, 251 <0x00 0x44860000 0x00 0x20000>; 252 /* 253 * Marked Disabled: 254 * Node is incomplete as it is meant for bootloaders and 255 * firmware on non-MPU processors 256 */ 257 status = "disabled"; 258 }; 259 260 main_pmx0: pinctrl@f4000 { 261 compatible = "pinctrl-single"; 262 reg = <0x00 0xf4000 0x00 0x2ac>; 263 #pinctrl-cells = <1>; 264 pinctrl-single,register-width = <32>; 265 pinctrl-single,function-mask = <0xffffffff>; 266 }; 267 268 main_timer0: timer@2400000 { 269 compatible = "ti,am654-timer"; 270 reg = <0x00 0x2400000 0x00 0x400>; 271 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&k3_clks 36 2>; 273 clock-names = "fck"; 274 assigned-clocks = <&k3_clks 36 2>; 275 assigned-clock-parents = <&k3_clks 36 3>; 276 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 277 ti,timer-pwm; 278 }; 279 280 main_timer1: timer@2410000 { 281 compatible = "ti,am654-timer"; 282 reg = <0x00 0x2410000 0x00 0x400>; 283 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&k3_clks 37 2>; 285 clock-names = "fck"; 286 assigned-clocks = <&k3_clks 37 2>; 287 assigned-clock-parents = <&k3_clks 37 3>; 288 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 289 ti,timer-pwm; 290 }; 291 292 main_timer2: timer@2420000 { 293 compatible = "ti,am654-timer"; 294 reg = <0x00 0x2420000 0x00 0x400>; 295 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&k3_clks 38 2>; 297 clock-names = "fck"; 298 assigned-clocks = <&k3_clks 38 2>; 299 assigned-clock-parents = <&k3_clks 38 3>; 300 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 301 ti,timer-pwm; 302 }; 303 304 main_timer3: timer@2430000 { 305 compatible = "ti,am654-timer"; 306 reg = <0x00 0x2430000 0x00 0x400>; 307 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&k3_clks 39 2>; 309 clock-names = "fck"; 310 assigned-clocks = <&k3_clks 39 2>; 311 assigned-clock-parents = <&k3_clks 39 3>; 312 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 313 ti,timer-pwm; 314 }; 315 316 main_timer4: timer@2440000 { 317 compatible = "ti,am654-timer"; 318 reg = <0x00 0x2440000 0x00 0x400>; 319 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&k3_clks 40 2>; 321 clock-names = "fck"; 322 assigned-clocks = <&k3_clks 40 2>; 323 assigned-clock-parents = <&k3_clks 40 3>; 324 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 325 ti,timer-pwm; 326 }; 327 328 main_timer5: timer@2450000 { 329 compatible = "ti,am654-timer"; 330 reg = <0x00 0x2450000 0x00 0x400>; 331 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&k3_clks 41 2>; 333 clock-names = "fck"; 334 assigned-clocks = <&k3_clks 41 2>; 335 assigned-clock-parents = <&k3_clks 41 3>; 336 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 337 ti,timer-pwm; 338 }; 339 340 main_timer6: timer@2460000 { 341 compatible = "ti,am654-timer"; 342 reg = <0x00 0x2460000 0x00 0x400>; 343 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&k3_clks 42 2>; 345 clock-names = "fck"; 346 assigned-clocks = <&k3_clks 42 2>; 347 assigned-clock-parents = <&k3_clks 42 3>; 348 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 349 ti,timer-pwm; 350 }; 351 352 main_timer7: timer@2470000 { 353 compatible = "ti,am654-timer"; 354 reg = <0x00 0x2470000 0x00 0x400>; 355 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&k3_clks 43 2>; 357 clock-names = "fck"; 358 assigned-clocks = <&k3_clks 43 2>; 359 assigned-clock-parents = <&k3_clks 43 3>; 360 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 361 ti,timer-pwm; 362 }; 363 364 main_uart0: serial@2800000 { 365 compatible = "ti,am64-uart", "ti,am654-uart"; 366 reg = <0x00 0x02800000 0x00 0x100>; 367 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 368 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 369 clocks = <&k3_clks 146 0>; 370 clock-names = "fclk"; 371 status = "disabled"; 372 }; 373 374 main_uart1: serial@2810000 { 375 compatible = "ti,am64-uart", "ti,am654-uart"; 376 reg = <0x00 0x02810000 0x00 0x100>; 377 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 378 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 379 clocks = <&k3_clks 152 0>; 380 clock-names = "fclk"; 381 status = "disabled"; 382 }; 383 384 main_uart2: serial@2820000 { 385 compatible = "ti,am64-uart", "ti,am654-uart"; 386 reg = <0x00 0x02820000 0x00 0x100>; 387 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 388 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 389 clocks = <&k3_clks 153 0>; 390 clock-names = "fclk"; 391 status = "disabled"; 392 }; 393 394 main_uart3: serial@2830000 { 395 compatible = "ti,am64-uart", "ti,am654-uart"; 396 reg = <0x00 0x02830000 0x00 0x100>; 397 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 398 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 399 clocks = <&k3_clks 154 0>; 400 clock-names = "fclk"; 401 status = "disabled"; 402 }; 403 404 main_uart4: serial@2840000 { 405 compatible = "ti,am64-uart", "ti,am654-uart"; 406 reg = <0x00 0x02840000 0x00 0x100>; 407 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 408 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 409 clocks = <&k3_clks 155 0>; 410 clock-names = "fclk"; 411 status = "disabled"; 412 }; 413 414 main_uart5: serial@2850000 { 415 compatible = "ti,am64-uart", "ti,am654-uart"; 416 reg = <0x00 0x02850000 0x00 0x100>; 417 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 418 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 419 clocks = <&k3_clks 156 0>; 420 clock-names = "fclk"; 421 status = "disabled"; 422 }; 423 424 main_uart6: serial@2860000 { 425 compatible = "ti,am64-uart", "ti,am654-uart"; 426 reg = <0x00 0x02860000 0x00 0x100>; 427 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 428 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 429 clocks = <&k3_clks 158 0>; 430 clock-names = "fclk"; 431 status = "disabled"; 432 }; 433 434 main_i2c0: i2c@20000000 { 435 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 436 reg = <0x00 0x20000000 0x00 0x100>; 437 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 441 clocks = <&k3_clks 102 2>; 442 clock-names = "fck"; 443 status = "disabled"; 444 }; 445 446 main_i2c1: i2c@20010000 { 447 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 448 reg = <0x00 0x20010000 0x00 0x100>; 449 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 453 clocks = <&k3_clks 103 2>; 454 clock-names = "fck"; 455 status = "disabled"; 456 }; 457 458 main_i2c2: i2c@20020000 { 459 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 460 reg = <0x00 0x20020000 0x00 0x100>; 461 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 465 clocks = <&k3_clks 104 2>; 466 clock-names = "fck"; 467 status = "disabled"; 468 }; 469 470 main_i2c3: i2c@20030000 { 471 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 472 reg = <0x00 0x20030000 0x00 0x100>; 473 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 477 clocks = <&k3_clks 105 2>; 478 clock-names = "fck"; 479 status = "disabled"; 480 }; 481 482 main_spi0: spi@20100000 { 483 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 484 reg = <0x00 0x20100000 0x00 0x400>; 485 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 489 clocks = <&k3_clks 141 0>; 490 status = "disabled"; 491 }; 492 493 main_spi1: spi@20110000 { 494 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 495 reg = <0x00 0x20110000 0x00 0x400>; 496 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 500 clocks = <&k3_clks 142 0>; 501 status = "disabled"; 502 }; 503 504 main_spi2: spi@20120000 { 505 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 506 reg = <0x00 0x20120000 0x00 0x400>; 507 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 511 clocks = <&k3_clks 143 0>; 512 status = "disabled"; 513 }; 514 515 main_gpio_intr: interrupt-controller@a00000 { 516 compatible = "ti,sci-intr"; 517 reg = <0x00 0x00a00000 0x00 0x800>; 518 ti,intr-trigger-type = <1>; 519 interrupt-controller; 520 interrupt-parent = <&gic500>; 521 #interrupt-cells = <1>; 522 ti,sci = <&dmsc>; 523 ti,sci-dev-id = <3>; 524 ti,interrupt-ranges = <0 32 16>; 525 status = "disabled"; 526 }; 527 528 main_gpio0: gpio@600000 { 529 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 530 reg = <0x00 0x00600000 0x0 0x100>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 interrupt-parent = <&main_gpio_intr>; 534 interrupts = <190>, <191>, <192>, 535 <193>, <194>, <195>; 536 interrupt-controller; 537 #interrupt-cells = <2>; 538 ti,ngpio = <92>; 539 ti,davinci-gpio-unbanked = <0>; 540 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 541 clocks = <&k3_clks 77 0>; 542 clock-names = "gpio"; 543 status = "disabled"; 544 }; 545 546 main_gpio1: gpio@601000 { 547 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 548 reg = <0x00 0x00601000 0x0 0x100>; 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-parent = <&main_gpio_intr>; 552 interrupts = <180>, <181>, <182>, 553 <183>, <184>, <185>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 ti,ngpio = <52>; 557 ti,davinci-gpio-unbanked = <0>; 558 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 559 clocks = <&k3_clks 78 0>; 560 clock-names = "gpio"; 561 status = "disabled"; 562 }; 563 564 sdhci0: mmc@fa10000 { 565 compatible = "ti,am62-sdhci"; 566 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 567 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 568 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 569 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 570 clock-names = "clk_ahb", "clk_xin"; 571 assigned-clocks = <&k3_clks 57 6>; 572 assigned-clock-parents = <&k3_clks 57 8>; 573 bus-width = <8>; 574 mmc-hs200-1_8v; 575 ti,clkbuf-sel = <0x7>; 576 ti,otap-del-sel-legacy = <0x0>; 577 ti,otap-del-sel-mmc-hs = <0x0>; 578 ti,otap-del-sel-hs200 = <0x6>; 579 status = "disabled"; 580 }; 581 582 sdhci1: mmc@fa00000 { 583 compatible = "ti,am62-sdhci"; 584 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 585 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 586 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 587 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 588 clock-names = "clk_ahb", "clk_xin"; 589 bus-width = <4>; 590 ti,clkbuf-sel = <0x7>; 591 ti,otap-del-sel-legacy = <0x0>; 592 ti,otap-del-sel-sd-hs = <0x0>; 593 ti,otap-del-sel-sdr12 = <0xf>; 594 ti,otap-del-sel-sdr25 = <0xf>; 595 ti,otap-del-sel-sdr50 = <0xc>; 596 ti,otap-del-sel-sdr104 = <0x6>; 597 ti,otap-del-sel-ddr50 = <0x9>; 598 ti,itap-del-sel-legacy = <0x0>; 599 ti,itap-del-sel-sd-hs = <0x0>; 600 ti,itap-del-sel-sdr12 = <0x0>; 601 ti,itap-del-sel-sdr25 = <0x0>; 602 status = "disabled"; 603 }; 604 605 sdhci2: mmc@fa20000 { 606 compatible = "ti,am62-sdhci"; 607 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; 608 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 609 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 610 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 611 clock-names = "clk_ahb", "clk_xin"; 612 bus-width = <4>; 613 ti,clkbuf-sel = <0x7>; 614 ti,otap-del-sel-legacy = <0x0>; 615 ti,otap-del-sel-sd-hs = <0x0>; 616 ti,otap-del-sel-sdr12 = <0xf>; 617 ti,otap-del-sel-sdr25 = <0xf>; 618 ti,otap-del-sel-sdr50 = <0xc>; 619 ti,otap-del-sel-sdr104 = <0x6>; 620 ti,otap-del-sel-ddr50 = <0x9>; 621 ti,itap-del-sel-legacy = <0x0>; 622 ti,itap-del-sel-sd-hs = <0x0>; 623 ti,itap-del-sel-sdr12 = <0x0>; 624 ti,itap-del-sel-sdr25 = <0x0>; 625 status = "disabled"; 626 }; 627 628 usbss0: dwc3-usb@f900000 { 629 compatible = "ti,am62-usb"; 630 reg = <0x00 0x0f900000 0x00 0x800>, 631 <0x00 0x0f908000 0x00 0x400>; 632 clocks = <&k3_clks 161 3>; 633 clock-names = "ref"; 634 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 635 #address-cells = <2>; 636 #size-cells = <2>; 637 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 638 ranges; 639 status = "disabled"; 640 641 usb0: usb@31000000 { 642 compatible = "snps,dwc3"; 643 reg = <0x00 0x31000000 0x00 0x50000>; 644 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 645 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 646 interrupt-names = "host", "peripheral"; 647 maximum-speed = "high-speed"; 648 dr_mode = "otg"; 649 snps,usb2-gadget-lpm-disable; 650 snps,usb2-lpm-disable; 651 }; 652 }; 653 654 usbss1: dwc3-usb@f910000 { 655 compatible = "ti,am62-usb"; 656 reg = <0x00 0x0f910000 0x00 0x800>, 657 <0x00 0x0f918000 0x00 0x400>; 658 clocks = <&k3_clks 162 3>; 659 clock-names = "ref"; 660 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; 661 #address-cells = <2>; 662 #size-cells = <2>; 663 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 664 ranges; 665 status = "disabled"; 666 667 usb1: usb@31100000 { 668 compatible = "snps,dwc3"; 669 reg = <0x00 0x31100000 0x00 0x50000>; 670 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 671 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 672 interrupt-names = "host", "peripheral"; 673 maximum-speed = "high-speed"; 674 dr_mode = "otg"; 675 snps,usb2-gadget-lpm-disable; 676 snps,usb2-lpm-disable; 677 }; 678 }; 679 680 fss: bus@fc00000 { 681 compatible = "simple-bus"; 682 reg = <0x00 0x0fc00000 0x00 0x70000>; 683 #address-cells = <2>; 684 #size-cells = <2>; 685 ranges; 686 status = "disabled"; 687 688 ospi0: spi@fc40000 { 689 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 690 reg = <0x00 0x0fc40000 0x00 0x100>, 691 <0x05 0x00000000 0x01 0x00000000>; 692 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 693 cdns,fifo-depth = <256>; 694 cdns,fifo-width = <4>; 695 cdns,trigger-address = <0x0>; 696 clocks = <&k3_clks 75 7>; 697 assigned-clocks = <&k3_clks 75 7>; 698 assigned-clock-parents = <&k3_clks 75 8>; 699 assigned-clock-rates = <166666666>; 700 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 }; 704 }; 705 706 cpsw3g: ethernet@8000000 { 707 compatible = "ti,am642-cpsw-nuss"; 708 #address-cells = <2>; 709 #size-cells = <2>; 710 reg = <0x0 0x8000000 0x0 0x200000>; 711 reg-names = "cpsw_nuss"; 712 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 713 clocks = <&k3_clks 13 0>; 714 assigned-clocks = <&k3_clks 13 3>; 715 assigned-clock-parents = <&k3_clks 13 11>; 716 clock-names = "fck"; 717 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 718 status = "disabled"; 719 720 dmas = <&main_pktdma 0xc600 15>, 721 <&main_pktdma 0xc601 15>, 722 <&main_pktdma 0xc602 15>, 723 <&main_pktdma 0xc603 15>, 724 <&main_pktdma 0xc604 15>, 725 <&main_pktdma 0xc605 15>, 726 <&main_pktdma 0xc606 15>, 727 <&main_pktdma 0xc607 15>, 728 <&main_pktdma 0x4600 15>; 729 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 730 "tx7", "rx"; 731 732 ethernet-ports { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 736 cpsw_port1: port@1 { 737 reg = <1>; 738 ti,mac-only; 739 label = "port1"; 740 phys = <&phy_gmii_sel 1>; 741 mac-address = [00 00 00 00 00 00]; 742 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 743 }; 744 745 cpsw_port2: port@2 { 746 reg = <2>; 747 ti,mac-only; 748 label = "port2"; 749 phys = <&phy_gmii_sel 2>; 750 mac-address = [00 00 00 00 00 00]; 751 }; 752 }; 753 754 cpsw3g_mdio: mdio@f00 { 755 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 756 reg = <0x0 0xf00 0x0 0x100>; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 clocks = <&k3_clks 13 0>; 760 clock-names = "fck"; 761 bus_freq = <1000000>; 762 }; 763 764 cpts@3d000 { 765 compatible = "ti,j721e-cpts"; 766 reg = <0x0 0x3d000 0x0 0x400>; 767 clocks = <&k3_clks 13 3>; 768 clock-names = "cpts"; 769 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 770 interrupt-names = "cpts"; 771 ti,cpts-ext-ts-inputs = <4>; 772 ti,cpts-periodic-outputs = <2>; 773 }; 774 }; 775 776 hwspinlock: spinlock@2a000000 { 777 compatible = "ti,am64-hwspinlock"; 778 reg = <0x00 0x2a000000 0x00 0x1000>; 779 #hwlock-cells = <1>; 780 }; 781 782 mailbox0_cluster0: mailbox@29000000 { 783 compatible = "ti,am64-mailbox"; 784 reg = <0x00 0x29000000 0x00 0x200>; 785 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 786 #mbox-cells = <1>; 787 ti,mbox-num-users = <4>; 788 ti,mbox-num-fifos = <16>; 789 }; 790 791 mailbox0_cluster1: mailbox@29010000 { 792 compatible = "ti,am64-mailbox"; 793 reg = <0x00 0x29010000 0x00 0x200>; 794 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 795 #mbox-cells = <1>; 796 ti,mbox-num-users = <4>; 797 ti,mbox-num-fifos = <16>; 798 }; 799 800 mailbox0_cluster2: mailbox@29020000 { 801 compatible = "ti,am64-mailbox"; 802 reg = <0x00 0x29020000 0x00 0x200>; 803 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 804 #mbox-cells = <1>; 805 ti,mbox-num-users = <4>; 806 ti,mbox-num-fifos = <16>; 807 }; 808 809 mailbox0_cluster3: mailbox@29030000 { 810 compatible = "ti,am64-mailbox"; 811 reg = <0x00 0x29030000 0x00 0x200>; 812 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 813 #mbox-cells = <1>; 814 ti,mbox-num-users = <4>; 815 ti,mbox-num-fifos = <16>; 816 }; 817 818 main_mcan0: can@20701000 { 819 compatible = "bosch,m_can"; 820 reg = <0x00 0x20701000 0x00 0x200>, 821 <0x00 0x20708000 0x00 0x8000>; 822 reg-names = "m_can", "message_ram"; 823 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 824 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 825 clock-names = "hclk", "cclk"; 826 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 828 interrupt-names = "int0", "int1"; 829 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 830 status = "disabled"; 831 }; 832 833 main_rti0: watchdog@e000000 { 834 compatible = "ti,j7-rti-wdt"; 835 reg = <0x00 0x0e000000 0x00 0x100>; 836 clocks = <&k3_clks 125 0>; 837 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 838 assigned-clocks = <&k3_clks 125 0>; 839 assigned-clock-parents = <&k3_clks 125 2>; 840 }; 841 842 main_rti1: watchdog@e010000 { 843 compatible = "ti,j7-rti-wdt"; 844 reg = <0x00 0x0e010000 0x00 0x100>; 845 clocks = <&k3_clks 126 0>; 846 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 847 assigned-clocks = <&k3_clks 126 0>; 848 assigned-clock-parents = <&k3_clks 126 2>; 849 }; 850 851 main_rti2: watchdog@e020000 { 852 compatible = "ti,j7-rti-wdt"; 853 reg = <0x00 0x0e020000 0x00 0x100>; 854 clocks = <&k3_clks 127 0>; 855 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 856 assigned-clocks = <&k3_clks 127 0>; 857 assigned-clock-parents = <&k3_clks 127 2>; 858 }; 859 860 main_rti3: watchdog@e030000 { 861 compatible = "ti,j7-rti-wdt"; 862 reg = <0x00 0x0e030000 0x00 0x100>; 863 clocks = <&k3_clks 128 0>; 864 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 865 assigned-clocks = <&k3_clks 128 0>; 866 assigned-clock-parents = <&k3_clks 128 2>; 867 }; 868 869 main_rti4: watchdog@e040000 { 870 compatible = "ti,j7-rti-wdt"; 871 reg = <0x00 0x0e040000 0x00 0x100>; 872 clocks = <&k3_clks 205 0>; 873 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; 874 assigned-clocks = <&k3_clks 205 0>; 875 assigned-clock-parents = <&k3_clks 205 2>; 876 }; 877 878 epwm0: pwm@23000000 { 879 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 880 #pwm-cells = <3>; 881 reg = <0x00 0x23000000 0x00 0x100>; 882 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 883 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 884 clock-names = "tbclk", "fck"; 885 status = "disabled"; 886 }; 887 888 epwm1: pwm@23010000 { 889 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 890 #pwm-cells = <3>; 891 reg = <0x00 0x23010000 0x00 0x100>; 892 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 893 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 894 clock-names = "tbclk", "fck"; 895 status = "disabled"; 896 }; 897 898 epwm2: pwm@23020000 { 899 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 900 #pwm-cells = <3>; 901 reg = <0x00 0x23020000 0x00 0x100>; 902 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 903 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 904 clock-names = "tbclk", "fck"; 905 status = "disabled"; 906 }; 907 908 ecap0: pwm@23100000 { 909 compatible = "ti,am3352-ecap"; 910 #pwm-cells = <3>; 911 reg = <0x00 0x23100000 0x00 0x100>; 912 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 913 clocks = <&k3_clks 51 0>; 914 clock-names = "fck"; 915 status = "disabled"; 916 }; 917 918 ecap1: pwm@23110000 { 919 compatible = "ti,am3352-ecap"; 920 #pwm-cells = <3>; 921 reg = <0x00 0x23110000 0x00 0x100>; 922 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 923 clocks = <&k3_clks 52 0>; 924 clock-names = "fck"; 925 status = "disabled"; 926 }; 927 928 ecap2: pwm@23120000 { 929 compatible = "ti,am3352-ecap"; 930 #pwm-cells = <3>; 931 reg = <0x00 0x23120000 0x00 0x100>; 932 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 933 clocks = <&k3_clks 53 0>; 934 clock-names = "fck"; 935 status = "disabled"; 936 }; 937 938 mcasp0: audio-controller@2b00000 { 939 compatible = "ti,am33xx-mcasp-audio"; 940 reg = <0x00 0x02b00000 0x00 0x2000>, 941 <0x00 0x02b08000 0x00 0x400>; 942 reg-names = "mpu", "dat"; 943 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "tx", "rx"; 946 947 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 948 dma-names = "tx", "rx"; 949 950 clocks = <&k3_clks 190 0>; 951 clock-names = "fck"; 952 assigned-clocks = <&k3_clks 190 0>; 953 assigned-clock-parents = <&k3_clks 190 2>; 954 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 955 status = "disabled"; 956 }; 957 958 mcasp1: audio-controller@2b10000 { 959 compatible = "ti,am33xx-mcasp-audio"; 960 reg = <0x00 0x02b10000 0x00 0x2000>, 961 <0x00 0x02b18000 0x00 0x400>; 962 reg-names = "mpu", "dat"; 963 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 965 interrupt-names = "tx", "rx"; 966 967 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 968 dma-names = "tx", "rx"; 969 970 clocks = <&k3_clks 191 0>; 971 clock-names = "fck"; 972 assigned-clocks = <&k3_clks 191 0>; 973 assigned-clock-parents = <&k3_clks 191 2>; 974 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 975 status = "disabled"; 976 }; 977 978 mcasp2: audio-controller@2b20000 { 979 compatible = "ti,am33xx-mcasp-audio"; 980 reg = <0x00 0x02b20000 0x00 0x2000>, 981 <0x00 0x02b28000 0x00 0x400>; 982 reg-names = "mpu", "dat"; 983 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 985 interrupt-names = "tx", "rx"; 986 987 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 988 dma-names = "tx", "rx"; 989 990 clocks = <&k3_clks 192 0>; 991 clock-names = "fck"; 992 assigned-clocks = <&k3_clks 192 0>; 993 assigned-clock-parents = <&k3_clks 192 2>; 994 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 995 status = "disabled"; 996 }; 997 998 ti_csi2rx0: ticsi2rx@30102000 { 999 compatible = "ti,j721e-csi2rx-shim"; 1000 dmas = <&main_bcdma_csi 0 0x5000 0>; 1001 dma-names = "rx0"; 1002 reg = <0x00 0x30102000 0x00 0x1000>; 1003 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1004 #address-cells = <2>; 1005 #size-cells = <2>; 1006 ranges; 1007 status = "disabled"; 1008 1009 cdns_csi2rx0: csi-bridge@30101000 { 1010 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1011 reg = <0x00 0x30101000 0x00 0x1000>; 1012 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1013 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1014 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1015 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1016 phys = <&dphy0>; 1017 phy-names = "dphy"; 1018 1019 ports { 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 1023 csi0_port0: port@0 { 1024 reg = <0>; 1025 status = "disabled"; 1026 }; 1027 1028 csi0_port1: port@1 { 1029 reg = <1>; 1030 status = "disabled"; 1031 }; 1032 1033 csi0_port2: port@2 { 1034 reg = <2>; 1035 status = "disabled"; 1036 }; 1037 1038 csi0_port3: port@3 { 1039 reg = <3>; 1040 status = "disabled"; 1041 }; 1042 1043 csi0_port4: port@4 { 1044 reg = <4>; 1045 status = "disabled"; 1046 }; 1047 }; 1048 }; 1049 }; 1050 1051 dphy0: phy@30110000 { 1052 compatible = "cdns,dphy-rx"; 1053 reg = <0x00 0x30110000 0x00 0x1100>; 1054 #phy-cells = <0>; 1055 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1056 status = "disabled"; 1057 }; 1058 1059 dss: dss@30200000 { 1060 compatible = "ti,am62a7-dss"; 1061 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 1062 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 1063 <0x00 0x30206000 0x00 0x1000>, /* vid */ 1064 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 1065 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 1066 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ 1067 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 1068 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 1069 reg-names = "common", "vidl1", "vid", 1070 "ovr1", "ovr2", "vp1", "vp2", "common1"; 1071 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1072 clocks = <&k3_clks 186 6>, 1073 <&k3_clks 186 0>, 1074 <&k3_clks 186 2>; 1075 clock-names = "fck", "vp1", "vp2"; 1076 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1077 status = "disabled"; 1078 1079 dss_ports: ports { 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 }; 1083 }; 1084 1085 vpu: video-codec@30210000 { 1086 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1087 reg = <0x00 0x30210000 0x00 0x10000>; 1088 clocks = <&k3_clks 204 2>; 1089 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1090 }; 1091}; 1092