1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_MCU_H 5 #define __MT76_CONNAC_MCU_H 6 7 #include "mt76_connac.h" 8 9 #define FW_FEATURE_SET_ENCRYPT BIT(0) 10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 11 #define FW_FEATURE_ENCRY_MODE BIT(4) 12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5) 13 #define FW_FEATURE_NON_DL BIT(6) 14 15 #define DL_MODE_ENCRYPT BIT(0) 16 #define DL_MODE_KEY_IDX GENMASK(2, 1) 17 #define DL_MODE_RESET_SEC_IV BIT(3) 18 #define DL_MODE_WORKING_PDA_CR4 BIT(4) 19 #define DL_MODE_VALID_RAM_ENTRY BIT(5) 20 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6) 21 #define DL_MODE_NEED_RSP BIT(31) 22 23 #define FW_START_OVERRIDE BIT(0) 24 #define FW_START_WORKING_PDA_CR4 BIT(2) 25 #define FW_START_WORKING_PDA_DSP BIT(3) 26 27 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0) 28 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0) 29 #define PATCH_SEC_TYPE_INFO 0x2 30 31 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24) 32 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00 33 #define PATCH_SEC_ENC_TYPE_AES 0x01 34 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02 35 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0) 36 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0) 37 38 enum { 39 FW_TYPE_DEFAULT = 0, 40 FW_TYPE_CLC = 2, 41 FW_TYPE_MAX_NUM = 255 42 }; 43 44 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 45 #define MCU_PKT_ID 0xa0 46 47 struct mt76_connac2_mcu_txd { 48 __le32 txd[8]; 49 50 __le16 len; 51 __le16 pq_id; 52 53 u8 cid; 54 u8 pkt_type; 55 u8 set_query; /* FW don't care */ 56 u8 seq; 57 58 u8 uc_d2b0_rev; 59 u8 ext_cid; 60 u8 s2d_index; 61 u8 ext_cid_ack; 62 63 u32 rsv[5]; 64 } __packed __aligned(4); 65 66 /** 67 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3 68 * @txd: hardware descriptor 69 * @len: total length not including txd 70 * @cid: command identifier 71 * @pkt_type: must be 0xa0 (cmd packet by long format) 72 * @frag_n: fragment number 73 * @seq: sequence number 74 * @checksum: 0 mean there is no checksum 75 * @s2d_index: index for command source and destination 76 * Definition | value | note 77 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 78 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 79 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 80 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 81 * 82 * @option: command option 83 * BIT[0]: UNI_CMD_OPT_BIT_ACK 84 * set to 1 to request a fw reply 85 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 86 * is set, mcu firmware will send response event EID = 0x01 87 * (UNI_EVENT_ID_CMD_RESULT) to the host. 88 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 89 * 0: original command 90 * 1: unified command 91 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 92 * 0: QUERY command 93 * 1: SET command 94 */ 95 struct mt76_connac2_mcu_uni_txd { 96 __le32 txd[8]; 97 98 /* DW1 */ 99 __le16 len; 100 __le16 cid; 101 102 /* DW2 */ 103 u8 rsv; 104 u8 pkt_type; 105 u8 frag_n; 106 u8 seq; 107 108 /* DW3 */ 109 __le16 checksum; 110 u8 s2d_index; 111 u8 option; 112 113 /* DW4 */ 114 u8 rsv1[4]; 115 } __packed __aligned(4); 116 117 struct mt76_connac2_mcu_rxd { 118 __le32 rxd[6]; 119 120 __le16 len; 121 __le16 pkt_type_id; 122 123 u8 eid; 124 u8 seq; 125 u8 option; 126 u8 rsv; 127 u8 ext_eid; 128 u8 rsv1[2]; 129 u8 s2d_index; 130 131 u8 tlv[]; 132 }; 133 134 struct mt76_connac2_patch_hdr { 135 char build_date[16]; 136 char platform[4]; 137 __be32 hw_sw_ver; 138 __be32 patch_ver; 139 __be16 checksum; 140 u16 rsv; 141 struct { 142 __be32 patch_ver; 143 __be32 subsys; 144 __be32 feature; 145 __be32 n_region; 146 __be32 crc; 147 u32 rsv[11]; 148 } desc; 149 } __packed; 150 151 struct mt76_connac2_patch_sec { 152 __be32 type; 153 __be32 offs; 154 __be32 size; 155 union { 156 __be32 spec[13]; 157 struct { 158 __be32 addr; 159 __be32 len; 160 __be32 sec_key_idx; 161 __be32 align_len; 162 u32 rsv[9]; 163 } info; 164 }; 165 } __packed; 166 167 struct mt76_connac2_fw_trailer { 168 u8 chip_id; 169 u8 eco_code; 170 u8 n_region; 171 u8 format_ver; 172 u8 format_flag; 173 u8 rsv[2]; 174 char fw_ver[10]; 175 char build_date[15]; 176 __le32 crc; 177 } __packed; 178 179 struct mt76_connac2_fw_region { 180 __le32 decomp_crc; 181 __le32 decomp_len; 182 __le32 decomp_blk_sz; 183 u8 rsv[4]; 184 __le32 addr; 185 __le32 len; 186 u8 feature_set; 187 u8 type; 188 u8 rsv1[14]; 189 } __packed; 190 191 struct tlv { 192 __le16 tag; 193 __le16 len; 194 u8 data[]; 195 } __packed; 196 197 struct bss_info_omac { 198 __le16 tag; 199 __le16 len; 200 u8 hw_bss_idx; 201 u8 omac_idx; 202 u8 band_idx; 203 u8 rsv0; 204 __le32 conn_type; 205 u32 rsv1; 206 } __packed; 207 208 struct bss_info_basic { 209 __le16 tag; 210 __le16 len; 211 __le32 network_type; 212 u8 active; 213 u8 rsv0; 214 __le16 bcn_interval; 215 u8 bssid[ETH_ALEN]; 216 u8 wmm_idx; 217 u8 dtim_period; 218 u8 bmc_wcid_lo; 219 u8 cipher; 220 u8 phy_mode; 221 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 222 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 223 u8 bmc_wcid_hi; /* high Byte and version */ 224 u8 rsv[2]; 225 } __packed; 226 227 struct bss_info_rf_ch { 228 __le16 tag; 229 __le16 len; 230 u8 pri_ch; 231 u8 center_ch0; 232 u8 center_ch1; 233 u8 bw; 234 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 235 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 236 u8 rsv[2]; 237 } __packed; 238 239 struct bss_info_ext_bss { 240 __le16 tag; 241 __le16 len; 242 __le32 mbss_tsf_offset; /* in unit of us */ 243 u8 rsv[8]; 244 } __packed; 245 246 enum { 247 BSS_INFO_OMAC, 248 BSS_INFO_BASIC, 249 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 250 BSS_INFO_PM, /* sta only */ 251 BSS_INFO_UAPSD, /* sta only */ 252 BSS_INFO_ROAM_DETECT, /* obsoleted */ 253 BSS_INFO_LQ_RM, /* obsoleted */ 254 BSS_INFO_EXT_BSS, 255 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 256 BSS_INFO_SYNC_MODE, /* obsoleted */ 257 BSS_INFO_RA, 258 BSS_INFO_HW_AMSDU, 259 BSS_INFO_BSS_COLOR, 260 BSS_INFO_HE_BASIC, 261 BSS_INFO_PROTECT_INFO, 262 BSS_INFO_OFFLOAD, 263 BSS_INFO_11V_MBSSID, 264 BSS_INFO_MAX_NUM 265 }; 266 267 /* sta_rec */ 268 269 struct sta_ntlv_hdr { 270 u8 rsv[2]; 271 __le16 tlv_num; 272 } __packed; 273 274 struct sta_req_hdr { 275 u8 bss_idx; 276 u8 wlan_idx_lo; 277 __le16 tlv_num; 278 u8 is_tlv_append; 279 u8 muar_idx; 280 u8 wlan_idx_hi; 281 u8 rsv; 282 } __packed; 283 284 struct sta_rec_basic { 285 __le16 tag; 286 __le16 len; 287 __le32 conn_type; 288 u8 conn_state; 289 u8 qos; 290 __le16 aid; 291 u8 peer_addr[ETH_ALEN]; 292 #define EXTRA_INFO_VER BIT(0) 293 #define EXTRA_INFO_NEW BIT(1) 294 __le16 extra_info; 295 } __packed; 296 297 struct sta_rec_ht { 298 __le16 tag; 299 __le16 len; 300 __le16 ht_cap; 301 u16 rsv; 302 } __packed; 303 304 struct sta_rec_vht { 305 __le16 tag; 306 __le16 len; 307 __le32 vht_cap; 308 __le16 vht_rx_mcs_map; 309 __le16 vht_tx_mcs_map; 310 /* mt7915 - mt7921 */ 311 u8 rts_bw_sig; 312 u8 rsv[3]; 313 } __packed; 314 315 struct sta_rec_uapsd { 316 __le16 tag; 317 __le16 len; 318 u8 dac_map; 319 u8 tac_map; 320 u8 max_sp; 321 u8 rsv0; 322 __le16 listen_interval; 323 u8 rsv1[2]; 324 } __packed; 325 326 struct sta_rec_ba { 327 __le16 tag; 328 __le16 len; 329 u8 tid; 330 u8 ba_type; 331 u8 amsdu; 332 u8 ba_en; 333 __le16 ssn; 334 __le16 winsize; 335 } __packed; 336 337 struct sta_rec_he { 338 __le16 tag; 339 __le16 len; 340 341 __le32 he_cap; 342 343 u8 t_frame_dur; 344 u8 max_ampdu_exp; 345 u8 bw_set; 346 u8 device_class; 347 u8 dcm_tx_mode; 348 u8 dcm_tx_max_nss; 349 u8 dcm_rx_mode; 350 u8 dcm_rx_max_nss; 351 u8 dcm_max_ru; 352 u8 punc_pream_rx; 353 u8 pkt_ext; 354 u8 rsv1; 355 356 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 357 358 u8 rsv2[2]; 359 } __packed; 360 361 struct sta_rec_he_v2 { 362 __le16 tag; 363 __le16 len; 364 u8 he_mac_cap[6]; 365 u8 he_phy_cap[11]; 366 u8 pkt_ext; 367 /* 0: BW80, 1: BW160, 2: BW8080 */ 368 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 369 } __packed; 370 371 struct sta_rec_amsdu { 372 __le16 tag; 373 __le16 len; 374 u8 max_amsdu_num; 375 u8 max_mpdu_size; 376 u8 amsdu_en; 377 u8 rsv; 378 } __packed; 379 380 struct sta_rec_state { 381 __le16 tag; 382 __le16 len; 383 __le32 flags; 384 u8 state; 385 u8 vht_opmode; 386 u8 action; 387 u8 rsv[1]; 388 } __packed; 389 390 #define RA_LEGACY_OFDM GENMASK(13, 6) 391 #define RA_LEGACY_CCK GENMASK(3, 0) 392 #define HT_MCS_MASK_NUM 10 393 struct sta_rec_ra_info { 394 __le16 tag; 395 __le16 len; 396 __le16 legacy; 397 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 398 } __packed; 399 400 struct sta_rec_phy { 401 __le16 tag; 402 __le16 len; 403 __le16 basic_rate; 404 u8 phy_type; 405 u8 ampdu; 406 u8 rts_policy; 407 u8 rcpi; 408 u8 max_ampdu_len; /* connac3 */ 409 u8 rsv[1]; 410 } __packed; 411 412 struct sta_rec_he_6g_capa { 413 __le16 tag; 414 __le16 len; 415 __le16 capa; 416 u8 rsv[2]; 417 } __packed; 418 419 struct sta_rec_pn_info { 420 __le16 tag; 421 __le16 len; 422 u8 pn[6]; 423 u8 tsc_type; 424 u8 rsv; 425 } __packed; 426 427 struct sec_key { 428 u8 cipher_id; 429 u8 cipher_len; 430 u8 key_id; 431 u8 key_len; 432 u8 key[32]; 433 } __packed; 434 435 struct sta_rec_sec { 436 __le16 tag; 437 __le16 len; 438 u8 add; 439 u8 n_cipher; 440 u8 rsv[2]; 441 442 struct sec_key key[2]; 443 } __packed; 444 445 struct sta_rec_bf { 446 __le16 tag; 447 __le16 len; 448 449 __le16 pfmu; /* 0xffff: no access right for PFMU */ 450 bool su_mu; /* 0: SU, 1: MU */ 451 u8 bf_cap; /* 0: iBF, 1: eBF */ 452 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 453 u8 ndpa_rate; 454 u8 ndp_rate; 455 u8 rept_poll_rate; 456 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 457 u8 ncol; 458 u8 nrow; 459 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 460 461 u8 mem_total; 462 u8 mem_20m; 463 struct { 464 u8 row; 465 u8 col: 6, row_msb: 2; 466 } mem[4]; 467 468 __le16 smart_ant; 469 u8 se_idx; 470 u8 auto_sounding; /* b7: low traffic indicator 471 * b6: Stop sounding for this entry 472 * b5 ~ b0: postpone sounding 473 */ 474 u8 ibf_timeout; 475 u8 ibf_dbw; 476 u8 ibf_ncol; 477 u8 ibf_nrow; 478 u8 nrow_gt_bw80; 479 u8 ncol_gt_bw80; 480 u8 ru_start_idx; 481 u8 ru_end_idx; 482 483 bool trigger_su; 484 bool trigger_mu; 485 bool ng16_su; 486 bool ng16_mu; 487 bool codebook42_su; 488 bool codebook75_mu; 489 490 u8 he_ltf; 491 u8 rsv[3]; 492 } __packed; 493 494 struct sta_rec_bfee { 495 __le16 tag; 496 __le16 len; 497 bool fb_identity_matrix; /* 1: feedback identity matrix */ 498 bool ignore_feedback; /* 1: ignore */ 499 u8 rsv[2]; 500 } __packed; 501 502 struct sta_rec_muru { 503 __le16 tag; 504 __le16 len; 505 506 struct { 507 bool ofdma_dl_en; 508 bool ofdma_ul_en; 509 bool mimo_dl_en; 510 bool mimo_ul_en; 511 u8 rsv[4]; 512 } cfg; 513 514 struct { 515 u8 punc_pream_rx; 516 bool he_20m_in_40m_2g; 517 bool he_20m_in_160m; 518 bool he_80m_in_160m; 519 bool lt16_sigb; 520 bool rx_su_comp_sigb; 521 bool rx_su_non_comp_sigb; 522 u8 rsv; 523 } ofdma_dl; 524 525 struct { 526 u8 t_frame_dur; 527 u8 mu_cascading; 528 u8 uo_ra; 529 u8 he_2x996_tone; 530 u8 rx_t_frame_11ac; 531 u8 rx_ctrl_frame_to_mbss; 532 u8 rsv[2]; 533 } ofdma_ul; 534 535 struct { 536 bool vht_mu_bfee; 537 bool partial_bw_dl_mimo; 538 u8 rsv[2]; 539 } mimo_dl; 540 541 struct { 542 bool full_ul_mimo; 543 bool partial_ul_mimo; 544 u8 rsv[2]; 545 } mimo_ul; 546 } __packed; 547 548 struct sta_rec_remove { 549 __le16 tag; 550 __le16 len; 551 u8 action; 552 u8 pad[3]; 553 } __packed; 554 555 struct sta_phy { 556 u8 type; 557 u8 flag; 558 u8 stbc; 559 u8 sgi; 560 u8 bw; 561 u8 ldpc; 562 u8 mcs; 563 u8 nss; 564 u8 he_ltf; 565 }; 566 567 struct sta_rec_ra { 568 __le16 tag; 569 __le16 len; 570 571 u8 valid; 572 u8 auto_rate; 573 u8 phy_mode; 574 u8 channel; 575 u8 bw; 576 u8 disable_cck; 577 u8 ht_mcs32; 578 u8 ht_gf; 579 u8 ht_mcs[4]; 580 u8 mmps_mode; 581 u8 gband_256; 582 u8 af; 583 u8 auth_wapi_mode; 584 u8 rate_len; 585 586 u8 supp_mode; 587 u8 supp_cck_rate; 588 u8 supp_ofdm_rate; 589 __le32 supp_ht_mcs; 590 __le16 supp_vht_mcs[4]; 591 592 u8 op_mode; 593 u8 op_vht_chan_width; 594 u8 op_vht_rx_nss; 595 u8 op_vht_rx_nss_type; 596 597 __le32 sta_cap; 598 599 struct sta_phy phy; 600 } __packed; 601 602 struct sta_rec_ra_fixed { 603 __le16 tag; 604 __le16 len; 605 606 __le32 field; 607 u8 op_mode; 608 u8 op_vht_chan_width; 609 u8 op_vht_rx_nss; 610 u8 op_vht_rx_nss_type; 611 612 struct sta_phy phy; 613 614 u8 spe_idx; 615 u8 short_preamble; 616 u8 is_5g; 617 u8 mmps_mode; 618 } __packed; 619 620 struct sta_rec_tx_proc { 621 __le16 tag; 622 __le16 len; 623 __le32 flag; 624 } __packed; 625 626 /* wtbl_rec */ 627 628 struct wtbl_req_hdr { 629 u8 wlan_idx_lo; 630 u8 operation; 631 __le16 tlv_num; 632 u8 wlan_idx_hi; 633 u8 rsv[3]; 634 } __packed; 635 636 struct wtbl_generic { 637 __le16 tag; 638 __le16 len; 639 u8 peer_addr[ETH_ALEN]; 640 u8 muar_idx; 641 u8 skip_tx; 642 u8 cf_ack; 643 u8 qos; 644 u8 mesh; 645 u8 adm; 646 __le16 partial_aid; 647 u8 baf_en; 648 u8 aad_om; 649 } __packed; 650 651 struct wtbl_rx { 652 __le16 tag; 653 __le16 len; 654 u8 rcid; 655 u8 rca1; 656 u8 rca2; 657 u8 rv; 658 u8 rsv[4]; 659 } __packed; 660 661 struct wtbl_ht { 662 __le16 tag; 663 __le16 len; 664 u8 ht; 665 u8 ldpc; 666 u8 af; 667 u8 mm; 668 u8 rsv[4]; 669 } __packed; 670 671 struct wtbl_vht { 672 __le16 tag; 673 __le16 len; 674 u8 ldpc; 675 u8 dyn_bw; 676 u8 vht; 677 u8 txop_ps; 678 u8 rsv[4]; 679 } __packed; 680 681 struct wtbl_tx_ps { 682 __le16 tag; 683 __le16 len; 684 u8 txps; 685 u8 rsv[3]; 686 } __packed; 687 688 struct wtbl_hdr_trans { 689 __le16 tag; 690 __le16 len; 691 u8 to_ds; 692 u8 from_ds; 693 u8 no_rx_trans; 694 u8 rsv; 695 } __packed; 696 697 struct wtbl_ba { 698 __le16 tag; 699 __le16 len; 700 /* common */ 701 u8 tid; 702 u8 ba_type; 703 u8 rsv0[2]; 704 /* originator only */ 705 __le16 sn; 706 u8 ba_en; 707 u8 ba_winsize_idx; 708 /* originator & recipient */ 709 __le16 ba_winsize; 710 /* recipient only */ 711 u8 peer_addr[ETH_ALEN]; 712 u8 rst_ba_tid; 713 u8 rst_ba_sel; 714 u8 rst_ba_sb; 715 u8 band_idx; 716 u8 rsv1[4]; 717 } __packed; 718 719 struct wtbl_smps { 720 __le16 tag; 721 __le16 len; 722 u8 smps; 723 u8 rsv[3]; 724 } __packed; 725 726 /* mt7615 only */ 727 728 struct wtbl_bf { 729 __le16 tag; 730 __le16 len; 731 u8 ibf; 732 u8 ebf; 733 u8 ibf_vht; 734 u8 ebf_vht; 735 u8 gid; 736 u8 pfmu_idx; 737 u8 rsv[2]; 738 } __packed; 739 740 struct wtbl_pn { 741 __le16 tag; 742 __le16 len; 743 u8 pn[6]; 744 u8 rsv[2]; 745 } __packed; 746 747 struct wtbl_spe { 748 __le16 tag; 749 __le16 len; 750 u8 spe_idx; 751 u8 rsv[3]; 752 } __packed; 753 754 struct wtbl_raw { 755 __le16 tag; 756 __le16 len; 757 u8 wtbl_idx; 758 u8 dw; 759 u8 rsv[2]; 760 __le32 msk; 761 __le32 val; 762 } __packed; 763 764 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 765 sizeof(struct wtbl_generic) + \ 766 sizeof(struct wtbl_rx) + \ 767 sizeof(struct wtbl_ht) + \ 768 sizeof(struct wtbl_vht) + \ 769 sizeof(struct wtbl_tx_ps) + \ 770 sizeof(struct wtbl_hdr_trans) +\ 771 sizeof(struct wtbl_ba) + \ 772 sizeof(struct wtbl_bf) + \ 773 sizeof(struct wtbl_smps) + \ 774 sizeof(struct wtbl_pn) + \ 775 sizeof(struct wtbl_spe)) 776 777 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 778 sizeof(struct sta_rec_basic) + \ 779 sizeof(struct sta_rec_bf) + \ 780 sizeof(struct sta_rec_ht) + \ 781 sizeof(struct sta_rec_he) + \ 782 sizeof(struct sta_rec_ba) + \ 783 sizeof(struct sta_rec_vht) + \ 784 sizeof(struct sta_rec_uapsd) + \ 785 sizeof(struct sta_rec_amsdu) + \ 786 sizeof(struct sta_rec_muru) + \ 787 sizeof(struct sta_rec_bfee) + \ 788 sizeof(struct sta_rec_ra) + \ 789 sizeof(struct sta_rec_sec) + \ 790 sizeof(struct sta_rec_ra_fixed) + \ 791 sizeof(struct sta_rec_he_6g_capa) + \ 792 sizeof(struct sta_rec_pn_info) + \ 793 sizeof(struct sta_rec_tx_proc) + \ 794 sizeof(struct tlv) + \ 795 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 796 797 enum { 798 STA_REC_BASIC, 799 STA_REC_RA, 800 STA_REC_RA_CMM_INFO, 801 STA_REC_RA_UPDATE, 802 STA_REC_BF, 803 STA_REC_AMSDU, 804 STA_REC_BA, 805 STA_REC_STATE, 806 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 807 STA_REC_HT, 808 STA_REC_VHT, 809 STA_REC_APPS, 810 STA_REC_KEY, 811 STA_REC_WTBL, 812 STA_REC_HE, 813 STA_REC_HW_AMSDU, 814 STA_REC_WTBL_AADOM, 815 STA_REC_KEY_V2, 816 STA_REC_MURU, 817 STA_REC_MUEDCA, 818 STA_REC_BFEE, 819 STA_REC_PHY = 0x15, 820 STA_REC_HE_6G = 0x17, 821 STA_REC_HE_V2 = 0x19, 822 STA_REC_MLD = 0x20, 823 STA_REC_EHT_MLD = 0x21, 824 STA_REC_EHT = 0x22, 825 STA_REC_MLD_OFF = 0x23, 826 STA_REC_REMOVE = 0x25, 827 STA_REC_PN_INFO = 0x26, 828 STA_REC_KEY_V3 = 0x27, 829 STA_REC_HDRT = 0x28, 830 STA_REC_HDR_TRANS = 0x2B, 831 STA_REC_MAX_NUM 832 }; 833 834 enum { 835 WTBL_GENERIC, 836 WTBL_RX, 837 WTBL_HT, 838 WTBL_VHT, 839 WTBL_PEER_PS, /* not used */ 840 WTBL_TX_PS, 841 WTBL_HDR_TRANS, 842 WTBL_SEC_KEY, 843 WTBL_BA, 844 WTBL_RDG, /* obsoleted */ 845 WTBL_PROTECT, /* not used */ 846 WTBL_CLEAR, /* not used */ 847 WTBL_BF, 848 WTBL_SMPS, 849 WTBL_RAW_DATA, /* debug only */ 850 WTBL_PN, 851 WTBL_SPE, 852 WTBL_MAX_NUM 853 }; 854 855 #define STA_TYPE_STA BIT(0) 856 #define STA_TYPE_AP BIT(1) 857 #define STA_TYPE_ADHOC BIT(2) 858 #define STA_TYPE_WDS BIT(4) 859 #define STA_TYPE_BC BIT(5) 860 861 #define NETWORK_INFRA BIT(16) 862 #define NETWORK_P2P BIT(17) 863 #define NETWORK_IBSS BIT(18) 864 #define NETWORK_WDS BIT(21) 865 866 #define SCAN_FUNC_RANDOM_MAC BIT(0) 867 #define SCAN_FUNC_SPLIT_SCAN BIT(5) 868 869 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 870 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 871 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 872 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 873 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 874 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 875 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 876 877 #define CONN_STATE_DISCONNECT 0 878 #define CONN_STATE_CONNECT 1 879 #define CONN_STATE_PORT_SECURE 2 880 881 /* HE MAC */ 882 #define STA_REC_HE_CAP_HTC BIT(0) 883 #define STA_REC_HE_CAP_BQR BIT(1) 884 #define STA_REC_HE_CAP_BSR BIT(2) 885 #define STA_REC_HE_CAP_OM BIT(3) 886 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 887 /* HE PHY */ 888 #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 889 #define STA_REC_HE_CAP_LDPC BIT(6) 890 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 891 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 892 /* STBC */ 893 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 894 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 895 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 896 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 897 /* GI */ 898 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 899 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 900 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 901 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 902 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 903 /* 242 TONE */ 904 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 905 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 906 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 907 908 #define PHY_MODE_A BIT(0) 909 #define PHY_MODE_B BIT(1) 910 #define PHY_MODE_G BIT(2) 911 #define PHY_MODE_GN BIT(3) 912 #define PHY_MODE_AN BIT(4) 913 #define PHY_MODE_AC BIT(5) 914 #define PHY_MODE_AX_24G BIT(6) 915 #define PHY_MODE_AX_5G BIT(7) 916 917 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 918 #define PHY_MODE_BE_24G BIT(1) 919 #define PHY_MODE_BE_5G BIT(2) 920 #define PHY_MODE_BE_6G BIT(3) 921 922 #define MODE_CCK BIT(0) 923 #define MODE_OFDM BIT(1) 924 #define MODE_HT BIT(2) 925 #define MODE_VHT BIT(3) 926 #define MODE_HE BIT(4) 927 #define MODE_EHT BIT(5) 928 929 #define STA_CAP_WMM BIT(0) 930 #define STA_CAP_SGI_20 BIT(4) 931 #define STA_CAP_SGI_40 BIT(5) 932 #define STA_CAP_TX_STBC BIT(6) 933 #define STA_CAP_RX_STBC BIT(7) 934 #define STA_CAP_VHT_SGI_80 BIT(16) 935 #define STA_CAP_VHT_SGI_160 BIT(17) 936 #define STA_CAP_VHT_TX_STBC BIT(18) 937 #define STA_CAP_VHT_RX_STBC BIT(19) 938 #define STA_CAP_VHT_LDPC BIT(23) 939 #define STA_CAP_LDPC BIT(24) 940 #define STA_CAP_HT BIT(26) 941 #define STA_CAP_VHT BIT(27) 942 #define STA_CAP_HE BIT(28) 943 944 enum { 945 PHY_TYPE_HR_DSSS_INDEX = 0, 946 PHY_TYPE_ERP_INDEX, 947 PHY_TYPE_ERP_P2P_INDEX, 948 PHY_TYPE_OFDM_INDEX, 949 PHY_TYPE_HT_INDEX, 950 PHY_TYPE_VHT_INDEX, 951 PHY_TYPE_HE_INDEX, 952 PHY_TYPE_BE_INDEX, 953 PHY_TYPE_INDEX_NUM 954 }; 955 956 #define HR_DSSS_ERP_BASIC_RATE GENMASK(3, 0) 957 #define OFDM_BASIC_RATE (BIT(6) | BIT(8) | BIT(10)) 958 959 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 960 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 961 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 962 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 963 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 964 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 965 #define PHY_TYPE_BIT_BE BIT(PHY_TYPE_BE_INDEX) 966 967 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 968 #define MT_WTBL_RATE_MCS GENMASK(5, 0) 969 #define MT_WTBL_RATE_NSS GENMASK(12, 10) 970 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 971 #define MT_WTBL_RATE_GI GENMASK(3, 0) 972 973 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 974 #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 975 #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 976 #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 977 #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 978 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 979 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 980 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 981 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 982 983 enum { 984 WTBL_RESET_AND_SET = 1, 985 WTBL_SET, 986 WTBL_QUERY, 987 WTBL_RESET_ALL 988 }; 989 990 enum { 991 MT_BA_TYPE_INVALID, 992 MT_BA_TYPE_ORIGINATOR, 993 MT_BA_TYPE_RECIPIENT 994 }; 995 996 enum { 997 RST_BA_MAC_TID_MATCH, 998 RST_BA_MAC_MATCH, 999 RST_BA_NO_MATCH 1000 }; 1001 1002 enum { 1003 DEV_INFO_ACTIVE, 1004 DEV_INFO_MAX_NUM 1005 }; 1006 1007 /* event table */ 1008 enum { 1009 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 1010 MCU_EVENT_FW_START = 0x01, 1011 MCU_EVENT_GENERIC = 0x01, 1012 MCU_EVENT_ACCESS_REG = 0x02, 1013 MCU_EVENT_MT_PATCH_SEM = 0x04, 1014 MCU_EVENT_REG_ACCESS = 0x05, 1015 MCU_EVENT_LP_INFO = 0x07, 1016 MCU_EVENT_SCAN_DONE = 0x0d, 1017 MCU_EVENT_TX_DONE = 0x0f, 1018 MCU_EVENT_ROC = 0x10, 1019 MCU_EVENT_BSS_ABSENCE = 0x11, 1020 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 1021 MCU_EVENT_CH_PRIVILEGE = 0x18, 1022 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 1023 MCU_EVENT_DBG_MSG = 0x27, 1024 MCU_EVENT_RSSI_NOTIFY = 0x96, 1025 MCU_EVENT_TXPWR = 0xd0, 1026 MCU_EVENT_EXT = 0xed, 1027 MCU_EVENT_RESTART_DL = 0xef, 1028 MCU_EVENT_COREDUMP = 0xf0, 1029 }; 1030 1031 /* ext event table */ 1032 enum { 1033 MCU_EXT_EVENT_PS_SYNC = 0x5, 1034 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 1035 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 1036 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 1037 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 1038 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 1039 MCU_EXT_EVENT_WA_TX_STAT = 0x74, 1040 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 1041 MCU_EXT_EVENT_MURU_CTRL = 0x9f, 1042 }; 1043 1044 /* unified event table */ 1045 enum { 1046 MCU_UNI_EVENT_RESULT = 0x01, 1047 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04, 1048 MCU_UNI_EVENT_ACCESS_REG = 0x6, 1049 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09, 1050 MCU_UNI_EVENT_COREDUMP = 0x0a, 1051 MCU_UNI_EVENT_BSS_BEACON_LOSS = 0x0c, 1052 MCU_UNI_EVENT_SCAN_DONE = 0x0e, 1053 MCU_UNI_EVENT_RDD_REPORT = 0x11, 1054 MCU_UNI_EVENT_ROC = 0x27, 1055 MCU_UNI_EVENT_TX_DONE = 0x2d, 1056 MCU_UNI_EVENT_THERMAL = 0x35, 1057 MCU_UNI_EVENT_NIC_CAPAB = 0x43, 1058 MCU_UNI_EVENT_WED_RRO = 0x57, 1059 MCU_UNI_EVENT_PER_STA_INFO = 0x6d, 1060 MCU_UNI_EVENT_ALL_STA_INFO = 0x6e, 1061 }; 1062 1063 #define MCU_UNI_CMD_EVENT BIT(1) 1064 #define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2) 1065 1066 enum { 1067 MCU_Q_QUERY, 1068 MCU_Q_SET, 1069 MCU_Q_RESERVED, 1070 MCU_Q_NA 1071 }; 1072 1073 enum { 1074 MCU_S2D_H2N, 1075 MCU_S2D_C2N, 1076 MCU_S2D_H2C, 1077 MCU_S2D_H2CN 1078 }; 1079 1080 enum { 1081 PATCH_NOT_DL_SEM_FAIL, 1082 PATCH_IS_DL, 1083 PATCH_NOT_DL_SEM_SUCCESS, 1084 PATCH_REL_SEM_SUCCESS 1085 }; 1086 1087 enum { 1088 FW_STATE_INITIAL, 1089 FW_STATE_FW_DOWNLOAD, 1090 FW_STATE_NORMAL_OPERATION, 1091 FW_STATE_NORMAL_TRX, 1092 FW_STATE_RDY = 7 1093 }; 1094 1095 enum { 1096 CH_SWITCH_NORMAL = 0, 1097 CH_SWITCH_SCAN = 3, 1098 CH_SWITCH_MCC = 4, 1099 CH_SWITCH_DFS = 5, 1100 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1101 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1102 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1103 CH_SWITCH_SCAN_BYPASS_DPD = 9 1104 }; 1105 1106 enum { 1107 THERMAL_SENSOR_TEMP_QUERY, 1108 THERMAL_SENSOR_MANUAL_CTRL, 1109 THERMAL_SENSOR_INFO_QUERY, 1110 THERMAL_SENSOR_TASK_CTRL, 1111 }; 1112 1113 enum mcu_cipher_type { 1114 MCU_CIPHER_NONE = 0, 1115 MCU_CIPHER_WEP40, 1116 MCU_CIPHER_WEP104, 1117 MCU_CIPHER_WEP128, 1118 MCU_CIPHER_TKIP, 1119 MCU_CIPHER_AES_CCMP, 1120 MCU_CIPHER_CCMP_256, 1121 MCU_CIPHER_GCMP, 1122 MCU_CIPHER_GCMP_256, 1123 MCU_CIPHER_WAPI, 1124 MCU_CIPHER_BIP_CMAC_128, 1125 MCU_CIPHER_BIP_CMAC_256, 1126 MCU_CIPHER_BCN_PROT_CMAC_128, 1127 MCU_CIPHER_BCN_PROT_CMAC_256, 1128 MCU_CIPHER_BCN_PROT_GMAC_128, 1129 MCU_CIPHER_BCN_PROT_GMAC_256, 1130 MCU_CIPHER_BIP_GMAC_128, 1131 MCU_CIPHER_BIP_GMAC_256, 1132 }; 1133 1134 enum { 1135 EE_MODE_EFUSE, 1136 EE_MODE_BUFFER, 1137 }; 1138 1139 enum { 1140 EE_FORMAT_BIN, 1141 EE_FORMAT_WHOLE, 1142 EE_FORMAT_MULTIPLE, 1143 }; 1144 1145 enum { 1146 MCU_PHY_STATE_TX_RATE, 1147 MCU_PHY_STATE_RX_RATE, 1148 MCU_PHY_STATE_RSSI, 1149 MCU_PHY_STATE_CONTENTION_RX_RATE, 1150 MCU_PHY_STATE_OFDMLQ_CNINFO, 1151 }; 1152 1153 #define MCU_CMD_ACK BIT(0) 1154 #define MCU_CMD_UNI BIT(1) 1155 #define MCU_CMD_SET BIT(2) 1156 1157 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 1158 MCU_CMD_SET) 1159 #define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI) 1160 1161 #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 1162 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 1163 #define __MCU_CMD_FIELD_QUERY BIT(16) 1164 #define __MCU_CMD_FIELD_UNI BIT(17) 1165 #define __MCU_CMD_FIELD_CE BIT(18) 1166 #define __MCU_CMD_FIELD_WA BIT(19) 1167 #define __MCU_CMD_FIELD_WM BIT(20) 1168 1169 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1170 MCU_CMD_##_t) 1171 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 1172 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1173 MCU_EXT_CMD_##_t)) 1174 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1175 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 1176 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1177 MCU_UNI_CMD_##_t)) 1178 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ 1179 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1180 MCU_CE_CMD_##_t)) 1181 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1182 1183 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 1184 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 1185 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 1186 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1187 MCU_WA_PARAM_CMD_##_t)) 1188 1189 #define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ 1190 __MCU_CMD_FIELD_WM) 1191 #define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \ 1192 __MCU_CMD_FIELD_QUERY | \ 1193 __MCU_CMD_FIELD_WM) 1194 #define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ 1195 __MCU_CMD_FIELD_WA) 1196 #define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \ 1197 __MCU_CMD_FIELD_WA) 1198 1199 enum { 1200 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 1201 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 1202 MCU_EXT_CMD_RF_TEST = 0x04, 1203 MCU_EXT_CMD_ID_RADIO_ON_OFF_CTRL = 0x05, 1204 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 1205 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 1206 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 1207 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 1208 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 1209 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 1210 MCU_EXT_CMD_THERMAL_PROT = 0x23, 1211 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 1212 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 1213 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 1214 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 1215 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 1216 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 1217 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 1218 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 1219 MCU_EXT_CMD_ATE_CTRL = 0x3d, 1220 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 1221 MCU_EXT_CMD_DBDC_CTRL = 0x45, 1222 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 1223 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 1224 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 1225 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 1226 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 1227 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 1228 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 1229 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 1230 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 1231 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 1232 MCU_EXT_CMD_TXDPD_CAL = 0x60, 1233 MCU_EXT_CMD_CAL_CACHE = 0x67, 1234 MCU_EXT_CMD_RED_ENABLE = 0x68, 1235 MCU_EXT_CMD_CP_SUPPORT = 0x75, 1236 MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 1237 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 1238 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 1239 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 1240 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 1241 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 1242 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, 1243 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 1244 MCU_EXT_CMD_MURU_CTRL = 0x9f, 1245 MCU_EXT_CMD_SET_SPR = 0xa8, 1246 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 1247 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 1248 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 1249 }; 1250 1251 enum { 1252 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 1253 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 1254 MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 1255 MCU_UNI_CMD_EDCA_UPDATE = 0x04, 1256 MCU_UNI_CMD_SUSPEND = 0x05, 1257 MCU_UNI_CMD_OFFLOAD = 0x06, 1258 MCU_UNI_CMD_HIF_CTRL = 0x07, 1259 MCU_UNI_CMD_BAND_CONFIG = 0x08, 1260 MCU_UNI_CMD_REPT_MUAR = 0x09, 1261 MCU_UNI_CMD_WSYS_CONFIG = 0x0b, 1262 MCU_UNI_CMD_REG_ACCESS = 0x0d, 1263 MCU_UNI_CMD_CHIP_CONFIG = 0x0e, 1264 MCU_UNI_CMD_POWER_CTRL = 0x0f, 1265 MCU_UNI_CMD_RX_HDR_TRANS = 0x12, 1266 MCU_UNI_CMD_SER = 0x13, 1267 MCU_UNI_CMD_TWT = 0x14, 1268 MCU_UNI_CMD_SET_DOMAIN_INFO = 0x15, 1269 MCU_UNI_CMD_SCAN_REQ = 0x16, 1270 MCU_UNI_CMD_RDD_CTRL = 0x19, 1271 MCU_UNI_CMD_GET_MIB_INFO = 0x22, 1272 MCU_UNI_CMD_GET_STAT_INFO = 0x23, 1273 MCU_UNI_CMD_SNIFFER = 0x24, 1274 MCU_UNI_CMD_SR = 0x25, 1275 MCU_UNI_CMD_ROC = 0x27, 1276 MCU_UNI_CMD_SET_DBDC_PARMS = 0x28, 1277 MCU_UNI_CMD_TXPOWER = 0x2b, 1278 MCU_UNI_CMD_SET_POWER_LIMIT = 0x2c, 1279 MCU_UNI_CMD_EFUSE_CTRL = 0x2d, 1280 MCU_UNI_CMD_RA = 0x2f, 1281 MCU_UNI_CMD_MURU = 0x31, 1282 MCU_UNI_CMD_BF = 0x33, 1283 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34, 1284 MCU_UNI_CMD_THERMAL = 0x35, 1285 MCU_UNI_CMD_VOW = 0x37, 1286 MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40, 1287 MCU_UNI_CMD_RRO = 0x57, 1288 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58, 1289 MCU_UNI_CMD_PER_STA_INFO = 0x6d, 1290 MCU_UNI_CMD_ALL_STA_INFO = 0x6e, 1291 MCU_UNI_CMD_ASSERT_DUMP = 0x6f, 1292 }; 1293 1294 enum { 1295 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 1296 MCU_CMD_FW_START_REQ = 0x02, 1297 MCU_CMD_INIT_ACCESS_REG = 0x3, 1298 MCU_CMD_NIC_POWER_CTRL = 0x4, 1299 MCU_CMD_PATCH_START_REQ = 0x05, 1300 MCU_CMD_PATCH_FINISH_REQ = 0x07, 1301 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 1302 MCU_CMD_WA_PARAM = 0xc4, 1303 MCU_CMD_EXT_CID = 0xed, 1304 MCU_CMD_FW_SCATTER = 0xee, 1305 MCU_CMD_RESTART_DL_REQ = 0xef, 1306 }; 1307 1308 /* offload mcu commands */ 1309 enum { 1310 MCU_CE_CMD_TEST_CTRL = 0x01, 1311 MCU_CE_CMD_START_HW_SCAN = 0x03, 1312 MCU_CE_CMD_SET_PS_PROFILE = 0x05, 1313 MCU_CE_CMD_SET_RX_FILTER = 0x0a, 1314 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, 1315 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, 1316 MCU_CE_CMD_SET_BSS_ABORT = 0x17, 1317 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, 1318 MCU_CE_CMD_SET_ROC = 0x1c, 1319 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d, 1320 MCU_CE_CMD_SET_P2P_OPPPS = 0x33, 1321 MCU_CE_CMD_SET_CLC = 0x5c, 1322 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, 1323 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, 1324 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, 1325 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, 1326 MCU_CE_CMD_RSSI_MONITOR = 0xa1, 1327 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, 1328 MCU_CE_CMD_REG_WRITE = 0xc0, 1329 MCU_CE_CMD_REG_READ = 0xc0, 1330 MCU_CE_CMD_CHIP_CONFIG = 0xca, 1331 MCU_CE_CMD_FWLOG_2_HOST = 0xc5, 1332 MCU_CE_CMD_GET_WTBL = 0xcd, 1333 MCU_CE_CMD_GET_TXPWR = 0xd0, 1334 }; 1335 1336 enum { 1337 PATCH_SEM_RELEASE, 1338 PATCH_SEM_GET 1339 }; 1340 1341 enum { 1342 UNI_BSS_INFO_BASIC = 0, 1343 UNI_BSS_INFO_RA = 1, 1344 UNI_BSS_INFO_RLM = 2, 1345 UNI_BSS_INFO_BSS_COLOR = 4, 1346 UNI_BSS_INFO_HE_BASIC = 5, 1347 UNI_BSS_INFO_11V_MBSSID = 6, 1348 UNI_BSS_INFO_BCN_CONTENT = 7, 1349 UNI_BSS_INFO_BCN_CSA = 8, 1350 UNI_BSS_INFO_BCN_BCC = 9, 1351 UNI_BSS_INFO_BCN_MBSSID = 10, 1352 UNI_BSS_INFO_RATE = 11, 1353 UNI_BSS_INFO_QBSS = 15, 1354 UNI_BSS_INFO_SEC = 16, 1355 UNI_BSS_INFO_BCN_PROT = 17, 1356 UNI_BSS_INFO_TXCMD = 18, 1357 UNI_BSS_INFO_UAPSD = 19, 1358 UNI_BSS_INFO_PS = 21, 1359 UNI_BSS_INFO_BCNFT = 22, 1360 UNI_BSS_INFO_IFS_TIME = 23, 1361 UNI_BSS_INFO_OFFLOAD = 25, 1362 UNI_BSS_INFO_MLD = 26, 1363 UNI_BSS_INFO_PM_DISABLE = 27, 1364 }; 1365 1366 enum { 1367 UNI_OFFLOAD_OFFLOAD_ARP, 1368 UNI_OFFLOAD_OFFLOAD_ND, 1369 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 1370 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 1371 }; 1372 1373 enum UNI_ALL_STA_INFO_TAG { 1374 UNI_ALL_STA_TXRX_RATE, 1375 UNI_ALL_STA_TX_STAT, 1376 UNI_ALL_STA_TXRX_ADM_STAT, 1377 UNI_ALL_STA_TXRX_AIR_TIME, 1378 UNI_ALL_STA_DATA_TX_RETRY_COUNT, 1379 UNI_ALL_STA_GI_MODE, 1380 UNI_ALL_STA_TXRX_MSDU_COUNT, 1381 UNI_ALL_STA_MAX_NUM 1382 }; 1383 1384 enum { 1385 MT_NIC_CAP_TX_RESOURCE, 1386 MT_NIC_CAP_TX_EFUSE_ADDR, 1387 MT_NIC_CAP_COEX, 1388 MT_NIC_CAP_SINGLE_SKU, 1389 MT_NIC_CAP_CSUM_OFFLOAD, 1390 MT_NIC_CAP_HW_VER, 1391 MT_NIC_CAP_SW_VER, 1392 MT_NIC_CAP_MAC_ADDR, 1393 MT_NIC_CAP_PHY, 1394 MT_NIC_CAP_MAC, 1395 MT_NIC_CAP_FRAME_BUF, 1396 MT_NIC_CAP_BEAM_FORM, 1397 MT_NIC_CAP_LOCATION, 1398 MT_NIC_CAP_MUMIMO, 1399 MT_NIC_CAP_BUFFER_MODE_INFO, 1400 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 1401 MT_NIC_CAP_ANTSWP = 0x16, 1402 MT_NIC_CAP_WFDMA_REALLOC, 1403 MT_NIC_CAP_6G, 1404 MT_NIC_CAP_CHIP_CAP = 0x20, 1405 MT_NIC_CAP_EML_CAP = 0x22, 1406 }; 1407 1408 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 1409 #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 1410 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 1411 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 1412 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 1413 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 1414 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 1415 1416 enum { 1417 UNI_SUSPEND_MODE_SETTING, 1418 UNI_SUSPEND_WOW_CTRL, 1419 UNI_SUSPEND_WOW_GPIO_PARAM, 1420 UNI_SUSPEND_WOW_WAKEUP_PORT, 1421 UNI_SUSPEND_WOW_PATTERN, 1422 }; 1423 1424 enum { 1425 WOW_USB = 1, 1426 WOW_PCIE = 2, 1427 WOW_GPIO = 3, 1428 }; 1429 1430 struct mt76_connac_bss_basic_tlv { 1431 __le16 tag; 1432 __le16 len; 1433 u8 active; 1434 u8 omac_idx; 1435 u8 hw_bss_idx; 1436 u8 band_idx; 1437 __le32 conn_type; 1438 u8 conn_state; 1439 u8 wmm_idx; 1440 u8 bssid[ETH_ALEN]; 1441 __le16 bmc_tx_wlan_idx; 1442 __le16 bcn_interval; 1443 u8 dtim_period; 1444 u8 phymode; /* bit(0): A 1445 * bit(1): B 1446 * bit(2): G 1447 * bit(3): GN 1448 * bit(4): AN 1449 * bit(5): AC 1450 * bit(6): AX2 1451 * bit(7): AX5 1452 * bit(8): AX6 1453 */ 1454 __le16 sta_idx; 1455 __le16 nonht_basic_phy; 1456 u8 phymode_ext; /* bit(0) AX_6G */ 1457 u8 link_idx; 1458 } __packed; 1459 1460 struct mt76_connac_bss_qos_tlv { 1461 __le16 tag; 1462 __le16 len; 1463 u8 qos; 1464 u8 pad[3]; 1465 } __packed; 1466 1467 struct mt76_connac_beacon_loss_event { 1468 u8 bss_idx; 1469 u8 reason; 1470 u8 pad[2]; 1471 } __packed; 1472 1473 struct mt76_connac_rssi_notify_event { 1474 __le32 rssi[4]; 1475 } __packed; 1476 1477 struct mt76_connac_mcu_bss_event { 1478 u8 bss_idx; 1479 u8 is_absent; 1480 u8 free_quota; 1481 u8 pad; 1482 } __packed; 1483 1484 struct mt76_connac_mcu_scan_ssid { 1485 __le32 ssid_len; 1486 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1487 } __packed; 1488 1489 struct mt76_connac_mcu_scan_channel { 1490 u8 band; /* 1: 2.4GHz 1491 * 2: 5.0GHz 1492 * Others: Reserved 1493 */ 1494 u8 channel_num; 1495 } __packed; 1496 1497 struct mt76_connac_mcu_scan_match { 1498 __le32 rssi_th; 1499 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1500 u8 ssid_len; 1501 u8 rsv[3]; 1502 } __packed; 1503 1504 struct mt76_connac_hw_scan_req { 1505 u8 seq_num; 1506 u8 bss_idx; 1507 u8 scan_type; /* 0: PASSIVE SCAN 1508 * 1: ACTIVE SCAN 1509 */ 1510 u8 ssid_type; /* BIT(0) wildcard SSID 1511 * BIT(1) P2P wildcard SSID 1512 * BIT(2) specified SSID + wildcard SSID 1513 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 1514 */ 1515 u8 ssids_num; 1516 u8 probe_req_num; /* Number of probe request for each SSID */ 1517 u8 scan_func; /* BIT(0) Enable random MAC scan 1518 * BIT(1) Disable DBDC scan type 1~3. 1519 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 1520 */ 1521 u8 version; /* 0: Not support fields after ies. 1522 * 1: Support fields after ies. 1523 */ 1524 struct mt76_connac_mcu_scan_ssid ssids[4]; 1525 __le16 probe_delay_time; 1526 __le16 channel_dwell_time; /* channel Dwell interval */ 1527 __le16 timeout_value; 1528 u8 channel_type; /* 0: Full channels 1529 * 1: Only 2.4GHz channels 1530 * 2: Only 5GHz channels 1531 * 3: P2P social channel only (channel #1, #6 and #11) 1532 * 4: Specified channels 1533 * Others: Reserved 1534 */ 1535 u8 channels_num; /* valid when channel_type is 4 */ 1536 /* valid when channels_num is set */ 1537 struct mt76_connac_mcu_scan_channel channels[32]; 1538 __le16 ies_len; 1539 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 1540 /* following fields are valid if version > 0 */ 1541 u8 ext_channels_num; 1542 u8 ext_ssids_num; 1543 __le16 channel_min_dwell_time; 1544 struct mt76_connac_mcu_scan_channel ext_channels[32]; 1545 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 1546 u8 bssid[ETH_ALEN]; 1547 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 1548 u8 pad[63]; 1549 u8 ssid_type_ext; 1550 } __packed; 1551 1552 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 1553 1554 struct mt76_connac_hw_scan_done { 1555 u8 seq_num; 1556 u8 sparse_channel_num; 1557 struct mt76_connac_mcu_scan_channel sparse_channel; 1558 u8 complete_channel_num; 1559 u8 current_state; 1560 u8 version; 1561 u8 pad; 1562 __le32 beacon_scan_num; 1563 u8 pno_enabled; 1564 u8 pad2[3]; 1565 u8 sparse_channel_valid_num; 1566 u8 pad3[3]; 1567 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1568 /* idle format for channel_idle_time 1569 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 1570 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 1571 * 2: dwell time (16us) 1572 */ 1573 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1574 /* beacon and probe response count */ 1575 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1576 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1577 __le32 beacon_2g_num; 1578 __le32 beacon_5g_num; 1579 } __packed; 1580 1581 struct mt76_connac_sched_scan_req { 1582 u8 version; 1583 u8 seq_num; 1584 u8 stop_on_match; 1585 u8 ssids_num; 1586 u8 match_num; 1587 u8 pad; 1588 __le16 ie_len; 1589 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 1590 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 1591 u8 channel_type; 1592 u8 channels_num; 1593 u8 intervals_num; 1594 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 1595 struct mt76_connac_mcu_scan_channel channels[64]; 1596 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 1597 union { 1598 struct { 1599 u8 random_mac[ETH_ALEN]; 1600 u8 pad2[58]; 1601 } mt7663; 1602 struct { 1603 u8 bss_idx; 1604 u8 pad1[3]; 1605 __le32 delay; 1606 u8 pad2[12]; 1607 u8 random_mac[ETH_ALEN]; 1608 u8 pad3[38]; 1609 } mt7921; 1610 }; 1611 } __packed; 1612 1613 struct mt76_connac_sched_scan_done { 1614 u8 seq_num; 1615 u8 status; /* 0: ssid found */ 1616 __le16 pad; 1617 } __packed; 1618 1619 struct bss_info_uni_bss_color { 1620 __le16 tag; 1621 __le16 len; 1622 u8 enable; 1623 u8 bss_color; 1624 u8 rsv[2]; 1625 } __packed; 1626 1627 struct bss_info_uni_he { 1628 __le16 tag; 1629 __le16 len; 1630 __le16 he_rts_thres; 1631 u8 he_pe_duration; 1632 u8 su_disable; 1633 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 1634 u8 rsv[2]; 1635 } __packed; 1636 1637 struct bss_info_uni_mbssid { 1638 __le16 tag; 1639 __le16 len; 1640 u8 max_indicator; 1641 u8 mbss_idx; 1642 u8 tx_bss_omac_idx; 1643 u8 rsv; 1644 } __packed; 1645 1646 struct mt76_connac_gtk_rekey_tlv { 1647 __le16 tag; 1648 __le16 len; 1649 u8 kek[NL80211_KEK_LEN]; 1650 u8 kck[NL80211_KCK_LEN]; 1651 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 1652 u8 rekey_mode; /* 0: rekey offload enable 1653 * 1: rekey offload disable 1654 * 2: rekey update 1655 */ 1656 u8 keyid; 1657 u8 option; /* 1: rekey data update without enabling offload */ 1658 u8 pad[1]; 1659 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 1660 __le32 pairwise_cipher; 1661 __le32 group_cipher; 1662 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 1663 __le32 mgmt_group_cipher; 1664 u8 reserverd[4]; 1665 } __packed; 1666 1667 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 1668 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 1669 1670 struct mt76_connac_wow_pattern_tlv { 1671 __le16 tag; 1672 __le16 len; 1673 u8 index; /* pattern index */ 1674 u8 enable; /* 0: disable 1675 * 1: enable 1676 */ 1677 u8 data_len; /* pattern length */ 1678 u8 pad; 1679 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 1680 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 1681 u8 rsv[4]; 1682 } __packed; 1683 1684 struct mt76_connac_wow_ctrl_tlv { 1685 __le16 tag; 1686 __le16 len; 1687 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 1688 * 0x2: PM_WOWLAN_REQ_STOP 1689 * 0x3: PM_WOWLAN_PARAM_CLEAR 1690 */ 1691 u8 trigger; /* 0: NONE 1692 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 1693 * BIT(1): NL80211_WOWLAN_TRIG_ANY 1694 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 1695 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 1696 * BIT(4): BEACON_LOST 1697 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 1698 */ 1699 u8 wakeup_hif; /* 0x0: HIF_SDIO 1700 * 0x1: HIF_USB 1701 * 0x2: HIF_PCIE 1702 * 0x3: HIF_GPIO 1703 */ 1704 u8 pad; 1705 u8 rsv[4]; 1706 } __packed; 1707 1708 struct mt76_connac_wow_gpio_param_tlv { 1709 __le16 tag; 1710 __le16 len; 1711 u8 gpio_pin; 1712 u8 trigger_lvl; 1713 u8 pad[2]; 1714 __le32 gpio_interval; 1715 u8 rsv[4]; 1716 } __packed; 1717 1718 struct mt76_connac_arpns_tlv { 1719 __le16 tag; 1720 __le16 len; 1721 u8 mode; 1722 u8 ips_num; 1723 u8 option; 1724 u8 pad[1]; 1725 } __packed; 1726 1727 struct mt76_connac_suspend_tlv { 1728 __le16 tag; 1729 __le16 len; 1730 u8 enable; /* 0: suspend mode disabled 1731 * 1: suspend mode enabled 1732 */ 1733 u8 mdtim; /* LP parameter */ 1734 u8 wow_suspend; /* 0: update by origin policy 1735 * 1: update by wow dtim 1736 */ 1737 u8 pad[5]; 1738 } __packed; 1739 1740 enum mt76_sta_info_state { 1741 MT76_STA_INFO_STATE_NONE, 1742 MT76_STA_INFO_STATE_AUTH, 1743 MT76_STA_INFO_STATE_ASSOC 1744 }; 1745 1746 struct mt76_sta_cmd_info { 1747 union { 1748 struct ieee80211_sta *sta; 1749 struct ieee80211_link_sta *link_sta; 1750 }; 1751 struct mt76_wcid *wcid; 1752 1753 struct ieee80211_vif *vif; 1754 1755 bool offload_fw; 1756 bool enable; 1757 bool newly; 1758 int cmd; 1759 u8 rcpi; 1760 u8 state; 1761 }; 1762 1763 #define MT_SKU_POWER_LIMIT 161 1764 1765 struct mt76_connac_sku_tlv { 1766 u8 channel; 1767 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 1768 } __packed; 1769 1770 struct mt76_connac_tx_power_limit_tlv { 1771 /* DW0 - common info*/ 1772 u8 ver; 1773 u8 pad0; 1774 __le16 len; 1775 /* DW1 - cmd hint */ 1776 u8 n_chan; /* # channel */ 1777 u8 band; /* 2.4GHz - 5GHz - 6GHz */ 1778 u8 last_msg; 1779 u8 pad1; 1780 /* DW3 */ 1781 u8 alpha2[4]; /* regulatory_request.alpha2 */ 1782 u8 pad2[32]; 1783 } __packed; 1784 1785 struct mt76_connac_config { 1786 __le16 id; 1787 u8 type; 1788 u8 resp_type; 1789 __le16 data_size; 1790 __le16 resv; 1791 u8 data[320]; 1792 } __packed; 1793 1794 struct mt76_connac_mcu_uni_event { 1795 u8 cid; 1796 u8 pad[3]; 1797 __le32 status; /* 0: success, others: fail */ 1798 } __packed; 1799 1800 struct mt76_connac_mcu_reg_event { 1801 __le32 reg; 1802 __le32 val; 1803 } __packed; 1804 1805 static inline enum mcu_cipher_type 1806 mt76_connac_mcu_get_cipher(int cipher) 1807 { 1808 switch (cipher) { 1809 case WLAN_CIPHER_SUITE_WEP40: 1810 return MCU_CIPHER_WEP40; 1811 case WLAN_CIPHER_SUITE_WEP104: 1812 return MCU_CIPHER_WEP104; 1813 case WLAN_CIPHER_SUITE_TKIP: 1814 return MCU_CIPHER_TKIP; 1815 case WLAN_CIPHER_SUITE_AES_CMAC: 1816 return MCU_CIPHER_BIP_CMAC_128; 1817 case WLAN_CIPHER_SUITE_CCMP: 1818 return MCU_CIPHER_AES_CCMP; 1819 case WLAN_CIPHER_SUITE_CCMP_256: 1820 return MCU_CIPHER_CCMP_256; 1821 case WLAN_CIPHER_SUITE_GCMP: 1822 return MCU_CIPHER_GCMP; 1823 case WLAN_CIPHER_SUITE_GCMP_256: 1824 return MCU_CIPHER_GCMP_256; 1825 case WLAN_CIPHER_SUITE_BIP_GMAC_128: 1826 return MCU_CIPHER_BIP_GMAC_128; 1827 case WLAN_CIPHER_SUITE_BIP_GMAC_256: 1828 return MCU_CIPHER_BIP_GMAC_256; 1829 case WLAN_CIPHER_SUITE_BIP_CMAC_256: 1830 return MCU_CIPHER_BIP_CMAC_256; 1831 case WLAN_CIPHER_SUITE_SMS4: 1832 return MCU_CIPHER_WAPI; 1833 default: 1834 return MCU_CIPHER_NONE; 1835 } 1836 } 1837 1838 static inline u32 1839 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa) 1840 { 1841 u32 ret = 0; 1842 1843 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ? 1844 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0; 1845 if (is_mt7921(dev) || is_mt7925(dev)) 1846 ret |= feature_set & FW_FEATURE_ENCRY_MODE ? 1847 DL_CONFIG_ENCRY_MODE_SEL : 0; 1848 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 1849 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 1850 ret |= DL_MODE_NEED_RSP; 1851 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0; 1852 1853 return ret; 1854 } 1855 1856 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 1857 #define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id) 1858 1859 static inline void 1860 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 1861 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 1862 { 1863 *wlan_idx_hi = 0; 1864 1865 if (!is_connac_v1(dev)) { 1866 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 1867 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 1868 } else { 1869 *wlan_idx_lo = wcid ? wcid->idx : 0; 1870 } 1871 } 1872 1873 struct sk_buff * 1874 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1875 struct mt76_wcid *wcid, int len); 1876 static inline struct sk_buff * 1877 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1878 struct mt76_wcid *wcid) 1879 { 1880 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid, 1881 MT76_CONNAC_STA_UPDATE_MAX_SIZE); 1882 } 1883 1884 struct wtbl_req_hdr * 1885 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1886 int cmd, void *sta_wtbl, struct sk_buff **skb); 1887 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1888 int len, void *sta_ntlv, 1889 void *sta_wtbl); 1890 static inline struct tlv * 1891 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1892 { 1893 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1894 } 1895 1896 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1897 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1898 void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1899 struct ieee80211_vif *vif, 1900 struct ieee80211_link_sta *link_sta, 1901 bool enable, bool newly); 1902 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1903 struct ieee80211_vif *vif, 1904 struct ieee80211_sta *sta, void *sta_wtbl, 1905 void *wtbl_tlv); 1906 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1907 struct ieee80211_vif *vif, 1908 struct mt76_wcid *wcid, 1909 void *sta_wtbl, void *wtbl_tlv); 1910 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1911 struct ieee80211_vif *vif, 1912 struct mt76_wcid *wcid, int cmd); 1913 void mt76_connac_mcu_sta_he_tlv_v2(struct sk_buff *skb, struct ieee80211_sta *sta); 1914 u8 mt76_connac_get_phy_mode_v2(struct mt76_phy *mphy, struct ieee80211_vif *vif, 1915 enum nl80211_band band, 1916 struct ieee80211_link_sta *link_sta); 1917 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev, 1918 struct ieee80211_vif *vif, 1919 struct ieee80211_sta *sta); 1920 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1921 struct ieee80211_sta *sta, 1922 struct ieee80211_vif *vif, 1923 u8 rcpi, u8 state); 1924 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1925 struct ieee80211_sta *sta, void *sta_wtbl, 1926 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc); 1927 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1928 struct ieee80211_ampdu_params *params, 1929 bool enable, bool tx, void *sta_wtbl, 1930 void *wtbl_tlv); 1931 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1932 struct ieee80211_ampdu_params *params, 1933 bool enable, bool tx); 1934 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1935 struct ieee80211_bss_conf *bss_conf, 1936 struct mt76_wcid *wcid, 1937 bool enable); 1938 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 1939 struct ieee80211_ampdu_params *params, 1940 int cmd, bool enable, bool tx); 1941 int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy, 1942 struct mt76_vif *vif, 1943 struct ieee80211_chanctx_conf *ctx); 1944 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1945 struct ieee80211_vif *vif, 1946 struct mt76_wcid *wcid, 1947 bool enable, 1948 struct ieee80211_chanctx_conf *ctx); 1949 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1950 struct mt76_sta_cmd_info *info); 1951 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1952 struct ieee80211_vif *vif); 1953 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1954 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1955 bool hdr_trans); 1956 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1957 u32 mode); 1958 int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1959 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1960 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1961 1962 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1963 struct ieee80211_scan_request *scan_req); 1964 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1965 struct ieee80211_vif *vif); 1966 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1967 struct ieee80211_vif *vif, 1968 struct cfg80211_sched_scan_request *sreq); 1969 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1970 struct ieee80211_vif *vif, 1971 bool enable); 1972 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1973 struct mt76_vif *vif, 1974 struct ieee80211_bss_conf *info); 1975 int mt76_connac_mcu_set_gtk_rekey(struct mt76_dev *dev, struct ieee80211_vif *vif, 1976 bool suspend); 1977 int mt76_connac_mcu_set_wow_ctrl(struct mt76_phy *phy, struct ieee80211_vif *vif, 1978 bool suspend, struct cfg80211_wowlan *wowlan); 1979 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1980 struct ieee80211_vif *vif, 1981 struct cfg80211_gtk_rekey_data *key); 1982 int mt76_connac_mcu_set_suspend_mode(struct mt76_dev *dev, 1983 struct ieee80211_vif *vif, 1984 bool enable, u8 mdtim, 1985 bool wow_suspend); 1986 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1987 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1988 struct ieee80211_vif *vif); 1989 int mt76_connac_sta_state_dp(struct mt76_dev *dev, 1990 enum ieee80211_sta_state old_state, 1991 enum ieee80211_sta_state new_state); 1992 int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1993 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1994 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1995 struct mt76_connac_coredump *coredump); 1996 s8 mt76_connac_get_ch_power(struct mt76_phy *phy, 1997 struct ieee80211_channel *chan, 1998 s8 target_power); 1999 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 2000 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 2001 struct ieee80211_vif *vif); 2002 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 2003 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 2004 2005 const struct ieee80211_sta_he_cap * 2006 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 2007 const struct ieee80211_sta_eht_cap * 2008 mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 2009 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif, 2010 enum nl80211_band band, 2011 struct ieee80211_link_sta *sta); 2012 u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_vif *vif, 2013 enum nl80211_band band); 2014 2015 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 2016 struct mt76_connac_sta_key_conf *sta_key_conf, 2017 struct ieee80211_key_conf *key, int mcu_cmd, 2018 struct mt76_wcid *wcid, enum set_key_cmd cmd); 2019 2020 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif); 2021 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb, 2022 struct ieee80211_vif *vif); 2023 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb, 2024 struct ieee80211_vif *vif, 2025 struct ieee80211_sta *sta, 2026 struct mt76_phy *phy, u16 wlan_idx, 2027 bool enable); 2028 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, 2029 struct ieee80211_sta *sta); 2030 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb, 2031 struct ieee80211_sta *sta, 2032 void *sta_wtbl, void *wtbl_tlv); 2033 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter); 2034 int mt76_connac_mcu_restart(struct mt76_dev *dev); 2035 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, 2036 u8 rx_sel, u8 val); 2037 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb); 2038 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, 2039 const char *fw_wa); 2040 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name); 2041 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb, 2042 int cmd, int *wait_seq); 2043 #endif /* __MT76_CONNAC_MCU_H */ 2044