1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine 4 * 5 * Copyright (C) 2012 Texas Instruments 6 * 7 */ 8 #include <linux/bitmap.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/seq_file.h> 15 #include <linux/slab.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/stat.h> 19 #include <linux/sysfs.h> 20 #include <linux/etherdevice.h> 21 22 #include "cpsw_ale.h" 23 24 #define BITMASK(bits) (BIT(bits) - 1) 25 26 #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask)) 27 #define ALE_VERSION_MINOR(rev) (rev & 0xff) 28 #define ALE_VERSION_1R3 0x0103 29 #define ALE_VERSION_1R4 0x0104 30 31 /* ALE Registers */ 32 #define ALE_IDVER 0x00 33 #define ALE_STATUS 0x04 34 #define ALE_CONTROL 0x08 35 #define ALE_PRESCALE 0x10 36 #define ALE_AGING_TIMER 0x14 37 #define ALE_UNKNOWNVLAN 0x18 38 #define ALE_TABLE_CONTROL 0x20 39 #define ALE_TABLE 0x34 40 #define ALE_PORTCTL 0x40 41 42 /* ALE NetCP NU switch specific Registers */ 43 #define ALE_UNKNOWNVLAN_MEMBER 0x90 44 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94 45 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98 46 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C 47 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) 48 49 #define ALE_POLICER_PORT_OUI 0x100 50 #define ALE_POLICER_DA_SA 0x104 51 #define ALE_POLICER_VLAN 0x108 52 #define ALE_POLICER_ETHERTYPE_IPSA 0x10c 53 #define ALE_POLICER_IPDA 0x110 54 #define ALE_POLICER_PIR 0x118 55 #define ALE_POLICER_CIR 0x11c 56 #define ALE_POLICER_TBL_CTL 0x120 57 #define ALE_POLICER_CTL 0x124 58 #define ALE_POLICER_TEST_CTL 0x128 59 #define ALE_POLICER_HIT_STATUS 0x12c 60 #define ALE_THREAD_DEF 0x134 61 #define ALE_THREAD_CTL 0x138 62 #define ALE_THREAD_VAL 0x13c 63 64 #define ALE_POLICER_TBL_WRITE_ENABLE BIT(31) 65 #define ALE_POLICER_TBL_INDEX_MASK GENMASK(4, 0) 66 67 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 68 69 /* ALE_AGING_TIMER */ 70 #define ALE_AGING_TIMER_MASK GENMASK(23, 0) 71 72 #define ALE_RATE_LIMIT_MIN_PPS 1000 73 74 /** 75 * struct ale_entry_fld - The ALE tbl entry field description 76 * @start_bit: field start bit 77 * @num_bits: field bit length 78 * @flags: field flags 79 */ 80 struct ale_entry_fld { 81 u8 start_bit; 82 u8 num_bits; 83 u8 flags; 84 }; 85 86 enum { 87 CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */ 88 CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */ 89 90 CPSW_ALE_F_COUNT 91 }; 92 93 /** 94 * struct cpsw_ale_dev_id - The ALE version/SoC specific configuration 95 * @dev_id: ALE version/SoC id 96 * @features: features supported by ALE 97 * @tbl_entries: number of ALE entries 98 * @reg_fields: pointer to array of register field configuration 99 * @nu_switch_ale: NU Switch ALE 100 * @vlan_entry_tbl: ALE vlan entry fields description tbl 101 */ 102 struct cpsw_ale_dev_id { 103 const char *dev_id; 104 u32 features; 105 u32 tbl_entries; 106 const struct reg_field *reg_fields; 107 bool nu_switch_ale; 108 const struct ale_entry_fld *vlan_entry_tbl; 109 }; 110 111 #define ALE_TABLE_WRITE BIT(31) 112 113 #define ALE_TYPE_FREE 0 114 #define ALE_TYPE_ADDR 1 115 #define ALE_TYPE_VLAN 2 116 #define ALE_TYPE_VLAN_ADDR 3 117 118 #define ALE_UCAST_PERSISTANT 0 119 #define ALE_UCAST_UNTOUCHED 1 120 #define ALE_UCAST_OUI 2 121 #define ALE_UCAST_TOUCHED 3 122 123 #define ALE_TABLE_SIZE_MULTIPLIER 1024 124 #define ALE_POLICER_SIZE_MULTIPLIER 8 125 126 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 127 { 128 int idx, idx2; 129 u32 hi_val = 0; 130 131 idx = start / 32; 132 idx2 = (start + bits - 1) / 32; 133 /* Check if bits to be fetched exceed a word */ 134 if (idx != idx2) { 135 idx2 = 2 - idx2; /* flip */ 136 hi_val = ale_entry[idx2] << ((idx2 * 32) - start); 137 } 138 start -= idx * 32; 139 idx = 2 - idx; /* flip */ 140 return (hi_val + (ale_entry[idx] >> start)) & BITMASK(bits); 141 } 142 143 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 144 u32 value) 145 { 146 int idx, idx2; 147 148 value &= BITMASK(bits); 149 idx = start / 32; 150 idx2 = (start + bits - 1) / 32; 151 /* Check if bits to be set exceed a word */ 152 if (idx != idx2) { 153 idx2 = 2 - idx2; /* flip */ 154 ale_entry[idx2] &= ~(BITMASK(bits + start - (idx2 * 32))); 155 ale_entry[idx2] |= (value >> ((idx2 * 32) - start)); 156 } 157 start -= idx * 32; 158 idx = 2 - idx; /* flip */ 159 ale_entry[idx] &= ~(BITMASK(bits) << start); 160 ale_entry[idx] |= (value << start); 161 } 162 163 #define DEFINE_ALE_FIELD(name, start, bits) \ 164 static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 165 { \ 166 return cpsw_ale_get_field(ale_entry, start, bits); \ 167 } \ 168 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 169 { \ 170 cpsw_ale_set_field(ale_entry, start, bits, value); \ 171 } 172 173 #define DEFINE_ALE_FIELD1(name, start) \ 174 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \ 175 { \ 176 return cpsw_ale_get_field(ale_entry, start, bits); \ 177 } \ 178 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \ 179 u32 bits) \ 180 { \ 181 cpsw_ale_set_field(ale_entry, start, bits, value); \ 182 } 183 184 enum { 185 ALE_ENT_VID_MEMBER_LIST = 0, 186 ALE_ENT_VID_UNREG_MCAST_MSK, 187 ALE_ENT_VID_REG_MCAST_MSK, 188 ALE_ENT_VID_FORCE_UNTAGGED_MSK, 189 ALE_ENT_VID_UNREG_MCAST_IDX, 190 ALE_ENT_VID_REG_MCAST_IDX, 191 ALE_ENT_VID_LAST, 192 }; 193 194 #define ALE_FLD_ALLOWED BIT(0) 195 #define ALE_FLD_SIZE_PORT_MASK_BITS BIT(1) 196 #define ALE_FLD_SIZE_PORT_NUM_BITS BIT(2) 197 198 #define ALE_ENTRY_FLD(id, start, bits) \ 199 [id] = { \ 200 .start_bit = start, \ 201 .num_bits = bits, \ 202 .flags = ALE_FLD_ALLOWED, \ 203 } 204 205 #define ALE_ENTRY_FLD_DYN_MSK_SIZE(id, start) \ 206 [id] = { \ 207 .start_bit = start, \ 208 .num_bits = 0, \ 209 .flags = ALE_FLD_ALLOWED | \ 210 ALE_FLD_SIZE_PORT_MASK_BITS, \ 211 } 212 213 /* dm814x, am3/am4/am5, k2hk */ 214 static const struct ale_entry_fld vlan_entry_cpsw[ALE_ENT_VID_LAST] = { 215 ALE_ENTRY_FLD(ALE_ENT_VID_MEMBER_LIST, 0, 3), 216 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_MSK, 8, 3), 217 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_MSK, 16, 3), 218 ALE_ENTRY_FLD(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24, 3), 219 }; 220 221 /* k2e/k2l, k3 am65/j721e cpsw2g */ 222 static const struct ale_entry_fld vlan_entry_nu[ALE_ENT_VID_LAST] = { 223 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0), 224 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_IDX, 20, 3), 225 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24), 226 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_IDX, 44, 3), 227 }; 228 229 /* K3 j721e/j7200 cpsw9g/5g, am64x cpsw3g */ 230 static const struct ale_entry_fld vlan_entry_k3_cpswxg[] = { 231 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0), 232 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_UNREG_MCAST_MSK, 12), 233 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24), 234 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_REG_MCAST_MSK, 36), 235 }; 236 237 DEFINE_ALE_FIELD(entry_type, 60, 2) 238 DEFINE_ALE_FIELD(vlan_id, 48, 12) 239 DEFINE_ALE_FIELD(mcast_state, 62, 2) 240 DEFINE_ALE_FIELD1(port_mask, 66) 241 DEFINE_ALE_FIELD(super, 65, 1) 242 DEFINE_ALE_FIELD(ucast_type, 62, 2) 243 DEFINE_ALE_FIELD1(port_num, 66) 244 DEFINE_ALE_FIELD(blocked, 65, 1) 245 DEFINE_ALE_FIELD(secure, 64, 1) 246 DEFINE_ALE_FIELD(mcast, 40, 1) 247 248 #define NU_VLAN_UNREG_MCAST_IDX 1 249 250 static int cpsw_ale_entry_get_fld(struct cpsw_ale *ale, 251 u32 *ale_entry, 252 const struct ale_entry_fld *entry_tbl, 253 int fld_id) 254 { 255 const struct ale_entry_fld *entry_fld; 256 u32 bits; 257 258 if (!ale || !ale_entry) 259 return -EINVAL; 260 261 entry_fld = &entry_tbl[fld_id]; 262 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) { 263 dev_err(ale->params.dev, "get: wrong ale fld id %d\n", fld_id); 264 return -ENOENT; 265 } 266 267 bits = entry_fld->num_bits; 268 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS) 269 bits = ale->port_mask_bits; 270 271 return cpsw_ale_get_field(ale_entry, entry_fld->start_bit, bits); 272 } 273 274 static void cpsw_ale_entry_set_fld(struct cpsw_ale *ale, 275 u32 *ale_entry, 276 const struct ale_entry_fld *entry_tbl, 277 int fld_id, 278 u32 value) 279 { 280 const struct ale_entry_fld *entry_fld; 281 u32 bits; 282 283 if (!ale || !ale_entry) 284 return; 285 286 entry_fld = &entry_tbl[fld_id]; 287 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) { 288 dev_err(ale->params.dev, "set: wrong ale fld id %d\n", fld_id); 289 return; 290 } 291 292 bits = entry_fld->num_bits; 293 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS) 294 bits = ale->port_mask_bits; 295 296 cpsw_ale_set_field(ale_entry, entry_fld->start_bit, bits, value); 297 } 298 299 static int cpsw_ale_vlan_get_fld(struct cpsw_ale *ale, 300 u32 *ale_entry, 301 int fld_id) 302 { 303 return cpsw_ale_entry_get_fld(ale, ale_entry, 304 ale->vlan_entry_tbl, fld_id); 305 } 306 307 static void cpsw_ale_vlan_set_fld(struct cpsw_ale *ale, 308 u32 *ale_entry, 309 int fld_id, 310 u32 value) 311 { 312 cpsw_ale_entry_set_fld(ale, ale_entry, 313 ale->vlan_entry_tbl, fld_id, value); 314 } 315 316 /* The MAC address field in the ALE entry cannot be macroized as above */ 317 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 318 { 319 int i; 320 321 for (i = 0; i < 6; i++) 322 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 323 } 324 325 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 326 { 327 int i; 328 329 for (i = 0; i < 6; i++) 330 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 331 } 332 333 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry) 334 { 335 int i; 336 337 WARN_ON(idx > ale->params.ale_entries); 338 339 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL); 340 341 for (i = 0; i < ALE_ENTRY_WORDS; i++) 342 ale_entry[i] = readl_relaxed(ale->params.ale_regs + 343 ALE_TABLE + 4 * i); 344 345 return idx; 346 } 347 348 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry) 349 { 350 int i; 351 352 WARN_ON(idx > ale->params.ale_entries); 353 354 for (i = 0; i < ALE_ENTRY_WORDS; i++) 355 writel_relaxed(ale_entry[i], ale->params.ale_regs + 356 ALE_TABLE + 4 * i); 357 358 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs + 359 ALE_TABLE_CONTROL); 360 361 return idx; 362 } 363 364 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid) 365 { 366 u32 ale_entry[ALE_ENTRY_WORDS]; 367 int type, idx; 368 369 for (idx = 0; idx < ale->params.ale_entries; idx++) { 370 u8 entry_addr[6]; 371 372 cpsw_ale_read(ale, idx, ale_entry); 373 type = cpsw_ale_get_entry_type(ale_entry); 374 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 375 continue; 376 if (cpsw_ale_get_vlan_id(ale_entry) != vid) 377 continue; 378 cpsw_ale_get_addr(ale_entry, entry_addr); 379 if (ether_addr_equal(entry_addr, addr)) 380 return idx; 381 } 382 return -ENOENT; 383 } 384 385 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid) 386 { 387 u32 ale_entry[ALE_ENTRY_WORDS]; 388 int type, idx; 389 390 for (idx = 0; idx < ale->params.ale_entries; idx++) { 391 cpsw_ale_read(ale, idx, ale_entry); 392 type = cpsw_ale_get_entry_type(ale_entry); 393 if (type != ALE_TYPE_VLAN) 394 continue; 395 if (cpsw_ale_get_vlan_id(ale_entry) == vid) 396 return idx; 397 } 398 return -ENOENT; 399 } 400 401 static int cpsw_ale_match_free(struct cpsw_ale *ale) 402 { 403 u32 ale_entry[ALE_ENTRY_WORDS]; 404 int type, idx; 405 406 for (idx = 0; idx < ale->params.ale_entries; idx++) { 407 cpsw_ale_read(ale, idx, ale_entry); 408 type = cpsw_ale_get_entry_type(ale_entry); 409 if (type == ALE_TYPE_FREE) 410 return idx; 411 } 412 return -ENOENT; 413 } 414 415 static int cpsw_ale_find_ageable(struct cpsw_ale *ale) 416 { 417 u32 ale_entry[ALE_ENTRY_WORDS]; 418 int type, idx; 419 420 for (idx = 0; idx < ale->params.ale_entries; idx++) { 421 cpsw_ale_read(ale, idx, ale_entry); 422 type = cpsw_ale_get_entry_type(ale_entry); 423 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 424 continue; 425 if (cpsw_ale_get_mcast(ale_entry)) 426 continue; 427 type = cpsw_ale_get_ucast_type(ale_entry); 428 if (type != ALE_UCAST_PERSISTANT && 429 type != ALE_UCAST_OUI) 430 return idx; 431 } 432 return -ENOENT; 433 } 434 435 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry, 436 int port_mask) 437 { 438 int mask; 439 440 mask = cpsw_ale_get_port_mask(ale_entry, 441 ale->port_mask_bits); 442 if ((mask & port_mask) == 0) 443 return; /* ports dont intersect, not interested */ 444 mask &= ~port_mask; 445 446 /* free if only remaining port is host port */ 447 if (mask) 448 cpsw_ale_set_port_mask(ale_entry, mask, 449 ale->port_mask_bits); 450 else 451 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 452 } 453 454 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) 455 { 456 u32 ale_entry[ALE_ENTRY_WORDS]; 457 int ret, idx; 458 459 for (idx = 0; idx < ale->params.ale_entries; idx++) { 460 cpsw_ale_read(ale, idx, ale_entry); 461 ret = cpsw_ale_get_entry_type(ale_entry); 462 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR) 463 continue; 464 465 /* if vid passed is -1 then remove all multicast entry from 466 * the table irrespective of vlan id, if a valid vlan id is 467 * passed then remove only multicast added to that vlan id. 468 * if vlan id doesn't match then move on to next entry. 469 */ 470 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid) 471 continue; 472 473 if (cpsw_ale_get_mcast(ale_entry)) { 474 u8 addr[6]; 475 476 if (cpsw_ale_get_super(ale_entry)) 477 continue; 478 479 cpsw_ale_get_addr(ale_entry, addr); 480 if (!is_broadcast_ether_addr(addr)) 481 cpsw_ale_flush_mcast(ale, ale_entry, port_mask); 482 } 483 484 cpsw_ale_write(ale, idx, ale_entry); 485 } 486 return 0; 487 } 488 489 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry, 490 int flags, u16 vid) 491 { 492 if (flags & ALE_VLAN) { 493 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR); 494 cpsw_ale_set_vlan_id(ale_entry, vid); 495 } else { 496 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 497 } 498 } 499 500 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 501 int flags, u16 vid) 502 { 503 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 504 int idx; 505 506 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 507 508 cpsw_ale_set_addr(ale_entry, addr); 509 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 510 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 511 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 512 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits); 513 514 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 515 if (idx < 0) 516 idx = cpsw_ale_match_free(ale); 517 if (idx < 0) 518 idx = cpsw_ale_find_ageable(ale); 519 if (idx < 0) 520 return -ENOMEM; 521 522 cpsw_ale_write(ale, idx, ale_entry); 523 return 0; 524 } 525 526 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 527 int flags, u16 vid) 528 { 529 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 530 int idx; 531 532 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 533 if (idx < 0) 534 return -ENOENT; 535 536 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 537 cpsw_ale_write(ale, idx, ale_entry); 538 return 0; 539 } 540 541 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 542 int flags, u16 vid, int mcast_state) 543 { 544 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 545 int idx, mask; 546 547 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 548 if (idx >= 0) 549 cpsw_ale_read(ale, idx, ale_entry); 550 551 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 552 553 cpsw_ale_set_addr(ale_entry, addr); 554 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0); 555 cpsw_ale_set_mcast_state(ale_entry, mcast_state); 556 557 mask = cpsw_ale_get_port_mask(ale_entry, 558 ale->port_mask_bits); 559 port_mask |= mask; 560 cpsw_ale_set_port_mask(ale_entry, port_mask, 561 ale->port_mask_bits); 562 563 if (idx < 0) 564 idx = cpsw_ale_match_free(ale); 565 if (idx < 0) 566 idx = cpsw_ale_find_ageable(ale); 567 if (idx < 0) 568 return -ENOMEM; 569 570 cpsw_ale_write(ale, idx, ale_entry); 571 return 0; 572 } 573 574 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 575 int flags, u16 vid) 576 { 577 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 578 int mcast_members = 0; 579 int idx; 580 581 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 582 if (idx < 0) 583 return -ENOENT; 584 585 cpsw_ale_read(ale, idx, ale_entry); 586 587 if (port_mask) { 588 mcast_members = cpsw_ale_get_port_mask(ale_entry, 589 ale->port_mask_bits); 590 mcast_members &= ~port_mask; 591 } 592 593 if (mcast_members) 594 cpsw_ale_set_port_mask(ale_entry, mcast_members, 595 ale->port_mask_bits); 596 else 597 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 598 599 cpsw_ale_write(ale, idx, ale_entry); 600 return 0; 601 } 602 603 /* ALE NetCP NU switch specific vlan functions */ 604 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, 605 int reg_mcast, int unreg_mcast) 606 { 607 int idx; 608 609 /* Set VLAN registered multicast flood mask */ 610 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 611 ALE_ENT_VID_REG_MCAST_IDX); 612 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 613 614 /* Set VLAN unregistered multicast flood mask */ 615 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 616 ALE_ENT_VID_UNREG_MCAST_IDX); 617 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 618 } 619 620 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry, 621 u16 vid, int untag_mask) 622 { 623 cpsw_ale_vlan_set_fld(ale, ale_entry, 624 ALE_ENT_VID_FORCE_UNTAGGED_MSK, 625 untag_mask); 626 if (untag_mask & ALE_PORT_HOST) 627 bitmap_set(ale->p0_untag_vid_mask, vid, 1); 628 else 629 bitmap_clear(ale->p0_untag_vid_mask, vid, 1); 630 } 631 632 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, 633 int reg_mcast, int unreg_mcast) 634 { 635 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 636 int idx; 637 638 idx = cpsw_ale_match_vlan(ale, vid); 639 if (idx >= 0) 640 cpsw_ale_read(ale, idx, ale_entry); 641 642 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN); 643 cpsw_ale_set_vlan_id(ale_entry, vid); 644 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 645 646 if (!ale->params.nu_switch_ale) { 647 cpsw_ale_vlan_set_fld(ale, ale_entry, 648 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast); 649 cpsw_ale_vlan_set_fld(ale, ale_entry, 650 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 651 } else { 652 cpsw_ale_vlan_set_fld(ale, ale_entry, 653 ALE_ENT_VID_UNREG_MCAST_IDX, 654 NU_VLAN_UNREG_MCAST_IDX); 655 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast); 656 } 657 658 cpsw_ale_vlan_set_fld(ale, ale_entry, 659 ALE_ENT_VID_MEMBER_LIST, port_mask); 660 661 if (idx < 0) 662 idx = cpsw_ale_match_free(ale); 663 if (idx < 0) 664 idx = cpsw_ale_find_ageable(ale); 665 if (idx < 0) 666 return -ENOMEM; 667 668 cpsw_ale_write(ale, idx, ale_entry); 669 return 0; 670 } 671 672 static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry, 673 u16 vid, int port_mask) 674 { 675 int reg_mcast, unreg_mcast; 676 int members, untag; 677 678 members = cpsw_ale_vlan_get_fld(ale, ale_entry, 679 ALE_ENT_VID_MEMBER_LIST); 680 members &= ~port_mask; 681 if (!members) { 682 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0); 683 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 684 return; 685 } 686 687 untag = cpsw_ale_vlan_get_fld(ale, ale_entry, 688 ALE_ENT_VID_FORCE_UNTAGGED_MSK); 689 reg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 690 ALE_ENT_VID_REG_MCAST_MSK); 691 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 692 ALE_ENT_VID_UNREG_MCAST_MSK); 693 untag &= members; 694 reg_mcast &= members; 695 unreg_mcast &= members; 696 697 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 698 699 if (!ale->params.nu_switch_ale) { 700 cpsw_ale_vlan_set_fld(ale, ale_entry, 701 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast); 702 cpsw_ale_vlan_set_fld(ale, ale_entry, 703 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 704 } else { 705 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, 706 unreg_mcast); 707 } 708 cpsw_ale_vlan_set_fld(ale, ale_entry, 709 ALE_ENT_VID_MEMBER_LIST, members); 710 } 711 712 int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask) 713 { 714 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 715 int idx; 716 717 idx = cpsw_ale_match_vlan(ale, vid); 718 if (idx < 0) 719 return -ENOENT; 720 721 cpsw_ale_read(ale, idx, ale_entry); 722 723 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask); 724 cpsw_ale_write(ale, idx, ale_entry); 725 726 return 0; 727 } 728 729 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) 730 { 731 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 732 int members, idx; 733 734 idx = cpsw_ale_match_vlan(ale, vid); 735 if (idx < 0) 736 return -ENOENT; 737 738 cpsw_ale_read(ale, idx, ale_entry); 739 740 /* if !port_mask - force remove VLAN (legacy). 741 * Check if there are other VLAN members ports 742 * if no - remove VLAN. 743 * if yes it means same VLAN was added to >1 port in multi port mode, so 744 * remove port_mask ports from VLAN ALE entry excluding Host port. 745 */ 746 members = cpsw_ale_vlan_get_fld(ale, ale_entry, ALE_ENT_VID_MEMBER_LIST); 747 members &= ~port_mask; 748 749 if (!port_mask || !members) { 750 /* last port or force remove - remove VLAN */ 751 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0); 752 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 753 } else { 754 port_mask &= ~ALE_PORT_HOST; 755 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask); 756 } 757 758 cpsw_ale_write(ale, idx, ale_entry); 759 760 return 0; 761 } 762 763 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, 764 int untag_mask, int reg_mask, int unreg_mask) 765 { 766 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 767 int reg_mcast_members, unreg_mcast_members; 768 int vlan_members, untag_members; 769 int idx, ret = 0; 770 771 idx = cpsw_ale_match_vlan(ale, vid); 772 if (idx >= 0) 773 cpsw_ale_read(ale, idx, ale_entry); 774 775 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 776 ALE_ENT_VID_MEMBER_LIST); 777 reg_mcast_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 778 ALE_ENT_VID_REG_MCAST_MSK); 779 unreg_mcast_members = 780 cpsw_ale_vlan_get_fld(ale, ale_entry, 781 ALE_ENT_VID_UNREG_MCAST_MSK); 782 untag_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 783 ALE_ENT_VID_FORCE_UNTAGGED_MSK); 784 785 vlan_members |= port_mask; 786 untag_members = (untag_members & ~port_mask) | untag_mask; 787 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask; 788 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask; 789 790 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, 791 reg_mcast_members, unreg_mcast_members); 792 if (ret) { 793 dev_err(ale->params.dev, "Unable to add vlan\n"); 794 return ret; 795 } 796 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, 797 untag_mask); 798 799 return ret; 800 } 801 802 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, 803 bool add) 804 { 805 u32 ale_entry[ALE_ENTRY_WORDS]; 806 int unreg_members = 0; 807 int type, idx; 808 809 for (idx = 0; idx < ale->params.ale_entries; idx++) { 810 cpsw_ale_read(ale, idx, ale_entry); 811 type = cpsw_ale_get_entry_type(ale_entry); 812 if (type != ALE_TYPE_VLAN) 813 continue; 814 815 unreg_members = 816 cpsw_ale_vlan_get_fld(ale, ale_entry, 817 ALE_ENT_VID_UNREG_MCAST_MSK); 818 if (add) 819 unreg_members |= unreg_mcast_mask; 820 else 821 unreg_members &= ~unreg_mcast_mask; 822 cpsw_ale_vlan_set_fld(ale, ale_entry, 823 ALE_ENT_VID_UNREG_MCAST_MSK, 824 unreg_members); 825 cpsw_ale_write(ale, idx, ale_entry); 826 } 827 } 828 829 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry, 830 int allmulti) 831 { 832 int unreg_mcast; 833 834 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry, 835 ALE_ENT_VID_UNREG_MCAST_MSK); 836 if (allmulti) 837 unreg_mcast |= ALE_PORT_HOST; 838 else 839 unreg_mcast &= ~ALE_PORT_HOST; 840 841 cpsw_ale_vlan_set_fld(ale, ale_entry, 842 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast); 843 } 844 845 static void 846 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry, 847 int allmulti) 848 { 849 int unreg_mcast; 850 int idx; 851 852 idx = cpsw_ale_vlan_get_fld(ale, ale_entry, 853 ALE_ENT_VID_UNREG_MCAST_IDX); 854 855 unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 856 857 if (allmulti) 858 unreg_mcast |= ALE_PORT_HOST; 859 else 860 unreg_mcast &= ~ALE_PORT_HOST; 861 862 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 863 } 864 865 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port) 866 { 867 u32 ale_entry[ALE_ENTRY_WORDS]; 868 int type, idx; 869 870 for (idx = 0; idx < ale->params.ale_entries; idx++) { 871 int vlan_members; 872 873 cpsw_ale_read(ale, idx, ale_entry); 874 type = cpsw_ale_get_entry_type(ale_entry); 875 if (type != ALE_TYPE_VLAN) 876 continue; 877 878 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry, 879 ALE_ENT_VID_MEMBER_LIST); 880 881 if (port != -1 && !(vlan_members & BIT(port))) 882 continue; 883 884 if (!ale->params.nu_switch_ale) 885 cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti); 886 else 887 cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry, 888 allmulti); 889 890 cpsw_ale_write(ale, idx, ale_entry); 891 } 892 } 893 894 struct ale_control_info { 895 const char *name; 896 int offset, port_offset; 897 int shift, port_shift; 898 int bits; 899 }; 900 901 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = { 902 [ALE_ENABLE] = { 903 .name = "enable", 904 .offset = ALE_CONTROL, 905 .port_offset = 0, 906 .shift = 31, 907 .port_shift = 0, 908 .bits = 1, 909 }, 910 [ALE_CLEAR] = { 911 .name = "clear", 912 .offset = ALE_CONTROL, 913 .port_offset = 0, 914 .shift = 30, 915 .port_shift = 0, 916 .bits = 1, 917 }, 918 [ALE_AGEOUT] = { 919 .name = "ageout", 920 .offset = ALE_CONTROL, 921 .port_offset = 0, 922 .shift = 29, 923 .port_shift = 0, 924 .bits = 1, 925 }, 926 [ALE_P0_UNI_FLOOD] = { 927 .name = "port0_unicast_flood", 928 .offset = ALE_CONTROL, 929 .port_offset = 0, 930 .shift = 8, 931 .port_shift = 0, 932 .bits = 1, 933 }, 934 [ALE_VLAN_NOLEARN] = { 935 .name = "vlan_nolearn", 936 .offset = ALE_CONTROL, 937 .port_offset = 0, 938 .shift = 7, 939 .port_shift = 0, 940 .bits = 1, 941 }, 942 [ALE_NO_PORT_VLAN] = { 943 .name = "no_port_vlan", 944 .offset = ALE_CONTROL, 945 .port_offset = 0, 946 .shift = 6, 947 .port_shift = 0, 948 .bits = 1, 949 }, 950 [ALE_OUI_DENY] = { 951 .name = "oui_deny", 952 .offset = ALE_CONTROL, 953 .port_offset = 0, 954 .shift = 5, 955 .port_shift = 0, 956 .bits = 1, 957 }, 958 [ALE_BYPASS] = { 959 .name = "bypass", 960 .offset = ALE_CONTROL, 961 .port_offset = 0, 962 .shift = 4, 963 .port_shift = 0, 964 .bits = 1, 965 }, 966 [ALE_RATE_LIMIT_TX] = { 967 .name = "rate_limit_tx", 968 .offset = ALE_CONTROL, 969 .port_offset = 0, 970 .shift = 3, 971 .port_shift = 0, 972 .bits = 1, 973 }, 974 [ALE_VLAN_AWARE] = { 975 .name = "vlan_aware", 976 .offset = ALE_CONTROL, 977 .port_offset = 0, 978 .shift = 2, 979 .port_shift = 0, 980 .bits = 1, 981 }, 982 [ALE_AUTH_ENABLE] = { 983 .name = "auth_enable", 984 .offset = ALE_CONTROL, 985 .port_offset = 0, 986 .shift = 1, 987 .port_shift = 0, 988 .bits = 1, 989 }, 990 [ALE_RATE_LIMIT] = { 991 .name = "rate_limit", 992 .offset = ALE_CONTROL, 993 .port_offset = 0, 994 .shift = 0, 995 .port_shift = 0, 996 .bits = 1, 997 }, 998 [ALE_PORT_STATE] = { 999 .name = "port_state", 1000 .offset = ALE_PORTCTL, 1001 .port_offset = 4, 1002 .shift = 0, 1003 .port_shift = 0, 1004 .bits = 2, 1005 }, 1006 [ALE_PORT_DROP_UNTAGGED] = { 1007 .name = "drop_untagged", 1008 .offset = ALE_PORTCTL, 1009 .port_offset = 4, 1010 .shift = 2, 1011 .port_shift = 0, 1012 .bits = 1, 1013 }, 1014 [ALE_PORT_DROP_UNKNOWN_VLAN] = { 1015 .name = "drop_unknown", 1016 .offset = ALE_PORTCTL, 1017 .port_offset = 4, 1018 .shift = 3, 1019 .port_shift = 0, 1020 .bits = 1, 1021 }, 1022 [ALE_PORT_NOLEARN] = { 1023 .name = "nolearn", 1024 .offset = ALE_PORTCTL, 1025 .port_offset = 4, 1026 .shift = 4, 1027 .port_shift = 0, 1028 .bits = 1, 1029 }, 1030 [ALE_PORT_NO_SA_UPDATE] = { 1031 .name = "no_source_update", 1032 .offset = ALE_PORTCTL, 1033 .port_offset = 4, 1034 .shift = 5, 1035 .port_shift = 0, 1036 .bits = 1, 1037 }, 1038 [ALE_PORT_MACONLY] = { 1039 .name = "mac_only_port_mode", 1040 .offset = ALE_PORTCTL, 1041 .port_offset = 4, 1042 .shift = 11, 1043 .port_shift = 0, 1044 .bits = 1, 1045 }, 1046 [ALE_PORT_MACONLY_CAF] = { 1047 .name = "mac_only_port_caf", 1048 .offset = ALE_PORTCTL, 1049 .port_offset = 4, 1050 .shift = 13, 1051 .port_shift = 0, 1052 .bits = 1, 1053 }, 1054 [ALE_PORT_MCAST_LIMIT] = { 1055 .name = "mcast_limit", 1056 .offset = ALE_PORTCTL, 1057 .port_offset = 4, 1058 .shift = 16, 1059 .port_shift = 0, 1060 .bits = 8, 1061 }, 1062 [ALE_PORT_BCAST_LIMIT] = { 1063 .name = "bcast_limit", 1064 .offset = ALE_PORTCTL, 1065 .port_offset = 4, 1066 .shift = 24, 1067 .port_shift = 0, 1068 .bits = 8, 1069 }, 1070 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = { 1071 .name = "unknown_vlan_member", 1072 .offset = ALE_UNKNOWNVLAN, 1073 .port_offset = 0, 1074 .shift = 0, 1075 .port_shift = 0, 1076 .bits = 6, 1077 }, 1078 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = { 1079 .name = "unknown_mcast_flood", 1080 .offset = ALE_UNKNOWNVLAN, 1081 .port_offset = 0, 1082 .shift = 8, 1083 .port_shift = 0, 1084 .bits = 6, 1085 }, 1086 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = { 1087 .name = "unknown_reg_flood", 1088 .offset = ALE_UNKNOWNVLAN, 1089 .port_offset = 0, 1090 .shift = 16, 1091 .port_shift = 0, 1092 .bits = 6, 1093 }, 1094 [ALE_PORT_UNTAGGED_EGRESS] = { 1095 .name = "untagged_egress", 1096 .offset = ALE_UNKNOWNVLAN, 1097 .port_offset = 0, 1098 .shift = 24, 1099 .port_shift = 0, 1100 .bits = 6, 1101 }, 1102 [ALE_DEFAULT_THREAD_ID] = { 1103 .name = "default_thread_id", 1104 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 1105 .port_offset = 0, 1106 .shift = 0, 1107 .port_shift = 0, 1108 .bits = 6, 1109 }, 1110 [ALE_DEFAULT_THREAD_ENABLE] = { 1111 .name = "default_thread_id_enable", 1112 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 1113 .port_offset = 0, 1114 .shift = 15, 1115 .port_shift = 0, 1116 .bits = 1, 1117 }, 1118 }; 1119 1120 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, 1121 int value) 1122 { 1123 const struct ale_control_info *info; 1124 int offset, shift; 1125 u32 tmp, mask; 1126 1127 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 1128 return -EINVAL; 1129 1130 info = &ale_controls[control]; 1131 if (info->port_offset == 0 && info->port_shift == 0) 1132 port = 0; /* global, port is a dont care */ 1133 1134 if (port < 0 || port >= ale->params.ale_ports) 1135 return -EINVAL; 1136 1137 mask = BITMASK(info->bits); 1138 if (value & ~mask) 1139 return -EINVAL; 1140 1141 offset = info->offset + (port * info->port_offset); 1142 shift = info->shift + (port * info->port_shift); 1143 1144 tmp = readl_relaxed(ale->params.ale_regs + offset); 1145 tmp = (tmp & ~(mask << shift)) | (value << shift); 1146 writel_relaxed(tmp, ale->params.ale_regs + offset); 1147 1148 return 0; 1149 } 1150 1151 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) 1152 { 1153 const struct ale_control_info *info; 1154 int offset, shift; 1155 u32 tmp; 1156 1157 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 1158 return -EINVAL; 1159 1160 info = &ale_controls[control]; 1161 if (info->port_offset == 0 && info->port_shift == 0) 1162 port = 0; /* global, port is a dont care */ 1163 1164 if (port < 0 || port >= ale->params.ale_ports) 1165 return -EINVAL; 1166 1167 offset = info->offset + (port * info->port_offset); 1168 shift = info->shift + (port * info->port_shift); 1169 1170 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift; 1171 return tmp & BITMASK(info->bits); 1172 } 1173 1174 int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps) 1175 1176 { 1177 int val = ratelimit_pps / ALE_RATE_LIMIT_MIN_PPS; 1178 u32 remainder = ratelimit_pps % ALE_RATE_LIMIT_MIN_PPS; 1179 1180 if (ratelimit_pps && !val) { 1181 dev_err(ale->params.dev, "ALE MC port:%d ratelimit min value 1000pps\n", port); 1182 return -EINVAL; 1183 } 1184 1185 if (remainder) 1186 dev_info(ale->params.dev, "ALE port:%d MC ratelimit set to %dpps (requested %d)\n", 1187 port, ratelimit_pps - remainder, ratelimit_pps); 1188 1189 cpsw_ale_control_set(ale, port, ALE_PORT_MCAST_LIMIT, val); 1190 1191 dev_dbg(ale->params.dev, "ALE port:%d MC ratelimit set %d\n", 1192 port, val * ALE_RATE_LIMIT_MIN_PPS); 1193 return 0; 1194 } 1195 1196 int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps) 1197 1198 { 1199 int val = ratelimit_pps / ALE_RATE_LIMIT_MIN_PPS; 1200 u32 remainder = ratelimit_pps % ALE_RATE_LIMIT_MIN_PPS; 1201 1202 if (ratelimit_pps && !val) { 1203 dev_err(ale->params.dev, "ALE port:%d BC ratelimit min value 1000pps\n", port); 1204 return -EINVAL; 1205 } 1206 1207 if (remainder) 1208 dev_info(ale->params.dev, "ALE port:%d BC ratelimit set to %dpps (requested %d)\n", 1209 port, ratelimit_pps - remainder, ratelimit_pps); 1210 1211 cpsw_ale_control_set(ale, port, ALE_PORT_BCAST_LIMIT, val); 1212 1213 dev_dbg(ale->params.dev, "ALE port:%d BC ratelimit set %d\n", 1214 port, val * ALE_RATE_LIMIT_MIN_PPS); 1215 return 0; 1216 } 1217 1218 static void cpsw_ale_timer(struct timer_list *t) 1219 { 1220 struct cpsw_ale *ale = from_timer(ale, t, timer); 1221 1222 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 1223 1224 if (ale->ageout) { 1225 ale->timer.expires = jiffies + ale->ageout; 1226 add_timer(&ale->timer); 1227 } 1228 } 1229 1230 static void cpsw_ale_hw_aging_timer_start(struct cpsw_ale *ale) 1231 { 1232 u32 aging_timer; 1233 1234 aging_timer = ale->params.bus_freq / 1000000; 1235 aging_timer *= ale->params.ale_ageout; 1236 1237 if (aging_timer & ~ALE_AGING_TIMER_MASK) { 1238 aging_timer = ALE_AGING_TIMER_MASK; 1239 dev_warn(ale->params.dev, 1240 "ALE aging timer overflow, set to max\n"); 1241 } 1242 1243 writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER); 1244 } 1245 1246 static void cpsw_ale_hw_aging_timer_stop(struct cpsw_ale *ale) 1247 { 1248 writel(0, ale->params.ale_regs + ALE_AGING_TIMER); 1249 } 1250 1251 static void cpsw_ale_aging_start(struct cpsw_ale *ale) 1252 { 1253 if (!ale->params.ale_ageout) 1254 return; 1255 1256 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) { 1257 cpsw_ale_hw_aging_timer_start(ale); 1258 return; 1259 } 1260 1261 timer_setup(&ale->timer, cpsw_ale_timer, 0); 1262 ale->timer.expires = jiffies + ale->ageout; 1263 add_timer(&ale->timer); 1264 } 1265 1266 static void cpsw_ale_aging_stop(struct cpsw_ale *ale) 1267 { 1268 if (!ale->params.ale_ageout) 1269 return; 1270 1271 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) { 1272 cpsw_ale_hw_aging_timer_stop(ale); 1273 return; 1274 } 1275 1276 del_timer_sync(&ale->timer); 1277 } 1278 1279 void cpsw_ale_start(struct cpsw_ale *ale) 1280 { 1281 unsigned long ale_prescale; 1282 1283 /* configure Broadcast and Multicast Rate Limit 1284 * number_of_packets = (Fclk / ALE_PRESCALE) * port.BCAST/MCAST_LIMIT 1285 * ALE_PRESCALE width is 19bit and min value 0x10 1286 * port.BCAST/MCAST_LIMIT is 8bit 1287 * 1288 * For multi port configuration support the ALE_PRESCALE is configured to 1ms interval, 1289 * which allows to configure port.BCAST/MCAST_LIMIT per port and achieve: 1290 * min number_of_packets = 1000 when port.BCAST/MCAST_LIMIT = 1 1291 * max number_of_packets = 1000 * 255 = 255000 when port.BCAST/MCAST_LIMIT = 0xFF 1292 */ 1293 ale_prescale = ale->params.bus_freq / ALE_RATE_LIMIT_MIN_PPS; 1294 writel((u32)ale_prescale, ale->params.ale_regs + ALE_PRESCALE); 1295 1296 /* Allow MC/BC rate limiting globally. 1297 * The actual Rate Limit cfg enabled per-port by port.BCAST/MCAST_LIMIT 1298 */ 1299 cpsw_ale_control_set(ale, 0, ALE_RATE_LIMIT, 1); 1300 1301 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1); 1302 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1303 1304 cpsw_ale_aging_start(ale); 1305 } 1306 1307 void cpsw_ale_stop(struct cpsw_ale *ale) 1308 { 1309 cpsw_ale_aging_stop(ale); 1310 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1311 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); 1312 } 1313 1314 static const struct reg_field ale_fields_cpsw[] = { 1315 /* CPSW_ALE_IDVER_REG */ 1316 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), 1317 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 15), 1318 }; 1319 1320 static const struct reg_field ale_fields_cpsw_nu[] = { 1321 /* CPSW_ALE_IDVER_REG */ 1322 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), 1323 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10), 1324 /* CPSW_ALE_STATUS_REG */ 1325 [ALE_ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7), 1326 [ALE_POLICERS] = REG_FIELD(ALE_STATUS, 8, 15), 1327 /* CPSW_ALE_POLICER_PORT_OUI_REG */ 1328 [POL_PORT_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31), 1329 [POL_TRUNK_ID] = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30), 1330 [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25), 1331 [POL_PRI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19), 1332 [POL_PRI_VAL] = REG_FIELD(ALE_POLICER_PORT_OUI, 16, 18), 1333 [POL_OUI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 15, 15), 1334 [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 5), 1335 1336 /* CPSW_ALE_POLICER_DA_SA_REG */ 1337 [POL_DST_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 31, 31), 1338 [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 21), 1339 [POL_SRC_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 15, 15), 1340 [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 5), 1341 1342 /* CPSW_ALE_POLICER_VLAN_REG */ 1343 [POL_OVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 31, 31), 1344 [POL_OVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 16, 21), 1345 [POL_IVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 15, 15), 1346 [POL_IVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 0, 5), 1347 1348 /* CPSW_ALE_POLICER_ETHERTYPE_IPSA_REG */ 1349 [POL_ETHERTYPE_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 31, 31), 1350 [POL_ETHERTYPE_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 21), 1351 [POL_IPSRC_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 15, 15), 1352 [POL_IPSRC_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 5), 1353 1354 /* CPSW_ALE_POLICER_IPDA_REG */ 1355 [POL_IPDST_MEN] = REG_FIELD(ALE_POLICER_IPDA, 31, 31), 1356 [POL_IPDST_INDEX] = REG_FIELD(ALE_POLICER_IPDA, 16, 21), 1357 1358 /* CPSW_ALE_POLICER_TBL_CTL_REG */ 1359 /** 1360 * REG_FIELDS not defined for this as fields cannot be correctly 1361 * used independently 1362 */ 1363 1364 /* CPSW_ALE_POLICER_CTL_REG */ 1365 [POL_EN] = REG_FIELD(ALE_POLICER_CTL, 31, 31), 1366 [POL_RED_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 29, 29), 1367 [POL_YELLOW_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 28, 28), 1368 [POL_YELLOW_THRESH] = REG_FIELD(ALE_POLICER_CTL, 24, 26), 1369 [POL_POL_MATCH_MODE] = REG_FIELD(ALE_POLICER_CTL, 22, 23), 1370 [POL_PRIORITY_THREAD_EN] = REG_FIELD(ALE_POLICER_CTL, 21, 21), 1371 [POL_MAC_ONLY_DEF_DIS] = REG_FIELD(ALE_POLICER_CTL, 20, 20), 1372 1373 /* CPSW_ALE_POLICER_TEST_CTL_REG */ 1374 [POL_TEST_CLR] = REG_FIELD(ALE_POLICER_TEST_CTL, 31, 31), 1375 [POL_TEST_CLR_RED] = REG_FIELD(ALE_POLICER_TEST_CTL, 30, 30), 1376 [POL_TEST_CLR_YELLOW] = REG_FIELD(ALE_POLICER_TEST_CTL, 29, 29), 1377 [POL_TEST_CLR_SELECTED] = REG_FIELD(ALE_POLICER_TEST_CTL, 28, 28), 1378 [POL_TEST_ENTRY] = REG_FIELD(ALE_POLICER_TEST_CTL, 0, 4), 1379 1380 /* CPSW_ALE_POLICER_HIT_STATUS_REG */ 1381 [POL_STATUS_HIT] = REG_FIELD(ALE_POLICER_HIT_STATUS, 31, 31), 1382 [POL_STATUS_HIT_RED] = REG_FIELD(ALE_POLICER_HIT_STATUS, 30, 30), 1383 [POL_STATUS_HIT_YELLOW] = REG_FIELD(ALE_POLICER_HIT_STATUS, 29, 29), 1384 1385 /* CPSW_ALE_THREAD_DEF_REG */ 1386 [ALE_DEFAULT_THREAD_EN] = REG_FIELD(ALE_THREAD_DEF, 15, 15), 1387 [ALE_DEFAULT_THREAD_VAL] = REG_FIELD(ALE_THREAD_DEF, 0, 5), 1388 1389 /* CPSW_ALE_THREAD_CTL_REG */ 1390 [ALE_THREAD_CLASS_INDEX] = REG_FIELD(ALE_THREAD_CTL, 0, 4), 1391 1392 /* CPSW_ALE_THREAD_VAL_REG */ 1393 [ALE_THREAD_ENABLE] = REG_FIELD(ALE_THREAD_VAL, 15, 15), 1394 [ALE_THREAD_VALUE] = REG_FIELD(ALE_THREAD_VAL, 0, 5), 1395 }; 1396 1397 static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { 1398 { 1399 /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */ 1400 .dev_id = "cpsw", 1401 .tbl_entries = 1024, 1402 .reg_fields = ale_fields_cpsw, 1403 .vlan_entry_tbl = vlan_entry_cpsw, 1404 }, 1405 { 1406 /* 66ak2h_xgbe */ 1407 .dev_id = "66ak2h-xgbe", 1408 .tbl_entries = 2048, 1409 .reg_fields = ale_fields_cpsw, 1410 .vlan_entry_tbl = vlan_entry_cpsw, 1411 }, 1412 { 1413 .dev_id = "66ak2el", 1414 .features = CPSW_ALE_F_STATUS_REG, 1415 .reg_fields = ale_fields_cpsw_nu, 1416 .nu_switch_ale = true, 1417 .vlan_entry_tbl = vlan_entry_nu, 1418 }, 1419 { 1420 .dev_id = "66ak2g", 1421 .features = CPSW_ALE_F_STATUS_REG, 1422 .tbl_entries = 64, 1423 .reg_fields = ale_fields_cpsw_nu, 1424 .nu_switch_ale = true, 1425 .vlan_entry_tbl = vlan_entry_nu, 1426 }, 1427 { 1428 .dev_id = "am65x-cpsw2g", 1429 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, 1430 .tbl_entries = 64, 1431 .reg_fields = ale_fields_cpsw_nu, 1432 .nu_switch_ale = true, 1433 .vlan_entry_tbl = vlan_entry_nu, 1434 }, 1435 { 1436 .dev_id = "j721e-cpswxg", 1437 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, 1438 .reg_fields = ale_fields_cpsw_nu, 1439 .vlan_entry_tbl = vlan_entry_k3_cpswxg, 1440 }, 1441 { 1442 .dev_id = "am64-cpswxg", 1443 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, 1444 .reg_fields = ale_fields_cpsw_nu, 1445 .vlan_entry_tbl = vlan_entry_k3_cpswxg, 1446 .tbl_entries = 512, 1447 }, 1448 { }, 1449 }; 1450 1451 static const struct 1452 cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id, 1453 const char *dev_id) 1454 { 1455 if (!dev_id) 1456 return NULL; 1457 1458 while (id->dev_id) { 1459 if (strcmp(dev_id, id->dev_id) == 0) 1460 return id; 1461 id++; 1462 } 1463 return NULL; 1464 } 1465 1466 static const struct regmap_config ale_regmap_cfg = { 1467 .reg_bits = 32, 1468 .val_bits = 32, 1469 .reg_stride = 4, 1470 .name = "cpsw-ale", 1471 }; 1472 1473 static int cpsw_ale_regfield_init(struct cpsw_ale *ale) 1474 { 1475 const struct reg_field *reg_fields = ale->params.reg_fields; 1476 struct device *dev = ale->params.dev; 1477 struct regmap *regmap = ale->regmap; 1478 int i; 1479 1480 for (i = 0; i < ALE_FIELDS_MAX; i++) { 1481 ale->fields[i] = devm_regmap_field_alloc(dev, regmap, 1482 reg_fields[i]); 1483 if (IS_ERR(ale->fields[i])) { 1484 dev_err(dev, "Unable to allocate regmap field %d\n", i); 1485 return PTR_ERR(ale->fields[i]); 1486 } 1487 } 1488 1489 return 0; 1490 } 1491 1492 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) 1493 { 1494 u32 ale_entries, rev_major, rev_minor, policers; 1495 const struct cpsw_ale_dev_id *ale_dev_id; 1496 struct cpsw_ale *ale; 1497 int ret; 1498 1499 ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); 1500 if (!ale_dev_id) 1501 return ERR_PTR(-EINVAL); 1502 1503 params->ale_entries = ale_dev_id->tbl_entries; 1504 params->nu_switch_ale = ale_dev_id->nu_switch_ale; 1505 params->reg_fields = ale_dev_id->reg_fields; 1506 1507 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); 1508 if (!ale) 1509 return ERR_PTR(-ENOMEM); 1510 ale->regmap = devm_regmap_init_mmio(params->dev, params->ale_regs, 1511 &ale_regmap_cfg); 1512 if (IS_ERR(ale->regmap)) { 1513 dev_err(params->dev, "Couldn't create CPSW ALE regmap\n"); 1514 return ERR_PTR(-ENOMEM); 1515 } 1516 1517 ale->params = *params; 1518 ret = cpsw_ale_regfield_init(ale); 1519 if (ret) 1520 return ERR_PTR(ret); 1521 1522 ale->p0_untag_vid_mask = devm_bitmap_zalloc(params->dev, VLAN_N_VID, 1523 GFP_KERNEL); 1524 if (!ale->p0_untag_vid_mask) 1525 return ERR_PTR(-ENOMEM); 1526 1527 ale->ageout = ale->params.ale_ageout * HZ; 1528 ale->features = ale_dev_id->features; 1529 ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl; 1530 1531 regmap_field_read(ale->fields[MINOR_VER], &rev_minor); 1532 regmap_field_read(ale->fields[MAJOR_VER], &rev_major); 1533 ale->version = rev_major << 8 | rev_minor; 1534 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n", 1535 rev_major, rev_minor); 1536 1537 if (ale->features & CPSW_ALE_F_STATUS_REG && 1538 !ale->params.ale_entries) { 1539 regmap_field_read(ale->fields[ALE_ENTRIES], &ale_entries); 1540 /* ALE available on newer NetCP switches has introduced 1541 * a register, ALE_STATUS, to indicate the size of ALE 1542 * table which shows the size as a multiple of 1024 entries. 1543 * For these, params.ale_entries will be set to zero. So 1544 * read the register and update the value of ale_entries. 1545 * return error if ale_entries is zero in ALE_STATUS. 1546 */ 1547 if (!ale_entries) 1548 return ERR_PTR(-EINVAL); 1549 1550 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; 1551 ale->params.ale_entries = ale_entries; 1552 } 1553 1554 if (ale->features & CPSW_ALE_F_STATUS_REG && 1555 !ale->params.num_policers) { 1556 regmap_field_read(ale->fields[ALE_POLICERS], &policers); 1557 if (!policers) 1558 return ERR_PTR(-EINVAL); 1559 1560 policers *= ALE_POLICER_SIZE_MULTIPLIER; 1561 ale->params.num_policers = policers; 1562 } 1563 1564 dev_info(ale->params.dev, 1565 "ALE Table size %ld, Policers %ld\n", ale->params.ale_entries, 1566 ale->params.num_policers); 1567 1568 /* set default bits for existing h/w */ 1569 ale->port_mask_bits = ale->params.ale_ports; 1570 ale->port_num_bits = order_base_2(ale->params.ale_ports); 1571 ale->vlan_field_bits = ale->params.ale_ports; 1572 1573 /* Set defaults override for ALE on NetCP NU switch and for version 1574 * 1R3 1575 */ 1576 if (ale->params.nu_switch_ale) { 1577 /* Separate registers for unknown vlan configuration. 1578 * Also there are N bits, where N is number of ale 1579 * ports and shift value should be 0 1580 */ 1581 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits = 1582 ale->params.ale_ports; 1583 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset = 1584 ALE_UNKNOWNVLAN_MEMBER; 1585 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits = 1586 ale->params.ale_ports; 1587 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0; 1588 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset = 1589 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD; 1590 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits = 1591 ale->params.ale_ports; 1592 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0; 1593 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset = 1594 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD; 1595 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits = 1596 ale->params.ale_ports; 1597 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0; 1598 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset = 1599 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS; 1600 } 1601 1602 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1603 return ale; 1604 } 1605 1606 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) 1607 { 1608 int i; 1609 1610 for (i = 0; i < ale->params.ale_entries; i++) { 1611 cpsw_ale_read(ale, i, data); 1612 data += ALE_ENTRY_WORDS; 1613 } 1614 } 1615 1616 void cpsw_ale_restore(struct cpsw_ale *ale, u32 *data) 1617 { 1618 int i; 1619 1620 for (i = 0; i < ale->params.ale_entries; i++) { 1621 cpsw_ale_write(ale, i, data); 1622 data += ALE_ENTRY_WORDS; 1623 } 1624 } 1625 1626 u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale) 1627 { 1628 return ale ? ale->params.ale_entries : 0; 1629 } 1630 1631 /* Reads the specified policer index into ALE POLICER registers */ 1632 static void cpsw_ale_policer_read_idx(struct cpsw_ale *ale, u32 idx) 1633 { 1634 idx &= ALE_POLICER_TBL_INDEX_MASK; 1635 writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL); 1636 } 1637 1638 /* Writes the ALE POLICER registers into the specified policer index */ 1639 static void cpsw_ale_policer_write_idx(struct cpsw_ale *ale, u32 idx) 1640 { 1641 idx &= ALE_POLICER_TBL_INDEX_MASK; 1642 idx |= ALE_POLICER_TBL_WRITE_ENABLE; 1643 writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL); 1644 } 1645 1646 /* enables/disables the custom thread value for the specified policer index */ 1647 static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx, 1648 u32 thread_id, bool enable) 1649 { 1650 regmap_field_write(ale->fields[ALE_THREAD_CLASS_INDEX], idx); 1651 regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id); 1652 regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0); 1653 } 1654 1655 /* Disable all policer entries and thread mappings */ 1656 static void cpsw_ale_policer_reset(struct cpsw_ale *ale) 1657 { 1658 int i; 1659 1660 for (i = 0; i < ale->params.num_policers ; i++) { 1661 cpsw_ale_policer_read_idx(ale, i); 1662 regmap_field_write(ale->fields[POL_PORT_MEN], 0); 1663 regmap_field_write(ale->fields[POL_PRI_MEN], 0); 1664 regmap_field_write(ale->fields[POL_OUI_MEN], 0); 1665 regmap_field_write(ale->fields[POL_DST_MEN], 0); 1666 regmap_field_write(ale->fields[POL_SRC_MEN], 0); 1667 regmap_field_write(ale->fields[POL_OVLAN_MEN], 0); 1668 regmap_field_write(ale->fields[POL_IVLAN_MEN], 0); 1669 regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0); 1670 regmap_field_write(ale->fields[POL_IPSRC_MEN], 0); 1671 regmap_field_write(ale->fields[POL_IPDST_MEN], 0); 1672 regmap_field_write(ale->fields[POL_EN], 0); 1673 regmap_field_write(ale->fields[POL_RED_DROP_EN], 0); 1674 regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0); 1675 regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0); 1676 1677 cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0); 1678 } 1679 } 1680 1681 /* Default classifier is to map 8 user priorities to N receive channels */ 1682 void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) 1683 { 1684 int pri, idx; 1685 /* IEEE802.1D-2004, Standard for Local and metropolitan area networks 1686 * Table G-2 - Traffic type acronyms 1687 * Table G-3 - Defining traffic types 1688 * User priority values 1 and 2 effectively communicate a lower 1689 * priority than 0. In the below table 0 is assigned to higher priority 1690 * thread than 1 and 2 wherever possible. 1691 * The below table maps which thread the user priority needs to be 1692 * sent to for a given number of threads (RX channels). Upper threads 1693 * have higher priority. 1694 * e.g. if number of threads is 8 then user priority 0 will map to 1695 * pri_thread_map[8-1][0] i.e. thread 2 1696 */ 1697 int pri_thread_map[8][8] = { { 0, 0, 0, 0, 0, 0, 0, 0, }, 1698 { 0, 0, 0, 0, 1, 1, 1, 1, }, 1699 { 0, 0, 0, 0, 1, 1, 2, 2, }, 1700 { 1, 0, 0, 1, 2, 2, 3, 3, }, 1701 { 1, 0, 0, 1, 2, 3, 4, 4, }, 1702 { 1, 0, 0, 2, 3, 4, 5, 5, }, 1703 { 1, 0, 0, 2, 3, 4, 5, 6, }, 1704 { 2, 0, 1, 3, 4, 5, 6, 7, } }; 1705 1706 cpsw_ale_policer_reset(ale); 1707 1708 /* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */ 1709 for (pri = 0; pri < 8; pri++) { 1710 idx = pri; 1711 1712 /* Classifier 'idx' match on priority 'pri' */ 1713 cpsw_ale_policer_read_idx(ale, idx); 1714 regmap_field_write(ale->fields[POL_PRI_VAL], pri); 1715 regmap_field_write(ale->fields[POL_PRI_MEN], 1); 1716 cpsw_ale_policer_write_idx(ale, idx); 1717 1718 /* Map Classifier 'idx' to thread provided by the map */ 1719 cpsw_ale_policer_thread_idx_enable(ale, idx, 1720 pri_thread_map[num_rx_ch - 1][pri], 1721 1); 1722 } 1723 } 1724