1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <linux/workqueue.h> 40 #include <net/addrconf.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <rdma/ib_umem.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include "hnae3.h" 47 #include "hns_roce_common.h" 48 #include "hns_roce_device.h" 49 #include "hns_roce_cmd.h" 50 #include "hns_roce_hem.h" 51 #include "hns_roce_hw_v2.h" 52 53 enum { 54 CMD_RST_PRC_OTHERS, 55 CMD_RST_PRC_SUCCESS, 56 CMD_RST_PRC_EBUSY, 57 }; 58 59 enum ecc_resource_type { 60 ECC_RESOURCE_QPC, 61 ECC_RESOURCE_CQC, 62 ECC_RESOURCE_MPT, 63 ECC_RESOURCE_SRQC, 64 ECC_RESOURCE_GMV, 65 ECC_RESOURCE_QPC_TIMER, 66 ECC_RESOURCE_CQC_TIMER, 67 ECC_RESOURCE_SCCC, 68 ECC_RESOURCE_COUNT, 69 }; 70 71 static const struct { 72 const char *name; 73 u8 read_bt0_op; 74 u8 write_bt0_op; 75 } fmea_ram_res[] = { 76 { "ECC_RESOURCE_QPC", 77 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 78 { "ECC_RESOURCE_CQC", 79 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 80 { "ECC_RESOURCE_MPT", 81 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 82 { "ECC_RESOURCE_SRQC", 83 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 84 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 85 { "ECC_RESOURCE_GMV", 86 0, 0 }, 87 { "ECC_RESOURCE_QPC_TIMER", 88 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 89 { "ECC_RESOURCE_CQC_TIMER", 90 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 91 { "ECC_RESOURCE_SCCC", 92 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 93 }; 94 95 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 96 struct ib_sge *sg) 97 { 98 dseg->lkey = cpu_to_le32(sg->lkey); 99 dseg->addr = cpu_to_le64(sg->addr); 100 dseg->len = cpu_to_le32(sg->length); 101 } 102 103 /* 104 * mapped-value = 1 + real-value 105 * The hns wr opcode real value is start from 0, In order to distinguish between 106 * initialized and uninitialized map values, we plus 1 to the actual value when 107 * defining the mapping, so that the validity can be identified by checking the 108 * mapped value is greater than 0. 109 */ 110 #define HR_OPC_MAP(ib_key, hr_key) \ 111 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 112 113 static const u32 hns_roce_op_code[] = { 114 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 115 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 116 HR_OPC_MAP(SEND, SEND), 117 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 118 HR_OPC_MAP(RDMA_READ, RDMA_READ), 119 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 120 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 121 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 122 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 123 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 124 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 125 }; 126 127 static u32 to_hr_opcode(u32 ib_opcode) 128 { 129 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 130 return HNS_ROCE_V2_WQE_OP_MASK; 131 132 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 133 HNS_ROCE_V2_WQE_OP_MASK; 134 } 135 136 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 137 const struct ib_reg_wr *wr) 138 { 139 struct hns_roce_wqe_frmr_seg *fseg = 140 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 141 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 142 u64 pbl_ba; 143 144 /* use ib_access_flags */ 145 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 146 hr_reg_write_bool(fseg, FRMR_ATOMIC, 147 wr->access & IB_ACCESS_REMOTE_ATOMIC); 148 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 149 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 150 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 151 152 /* Data structure reuse may lead to confusion */ 153 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 154 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 155 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 156 157 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 158 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 159 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 160 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 161 162 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 163 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 164 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 165 hr_reg_clear(fseg, FRMR_BLK_MODE); 166 } 167 168 static void set_atomic_seg(const struct ib_send_wr *wr, 169 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 170 unsigned int valid_num_sge) 171 { 172 struct hns_roce_v2_wqe_data_seg *dseg = 173 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 174 struct hns_roce_wqe_atomic_seg *aseg = 175 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 176 177 set_data_seg_v2(dseg, wr->sg_list); 178 179 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 180 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 181 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 182 } else { 183 aseg->fetchadd_swap_data = 184 cpu_to_le64(atomic_wr(wr)->compare_add); 185 aseg->cmp_data = 0; 186 } 187 188 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 189 } 190 191 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 192 const struct ib_send_wr *wr, 193 unsigned int *sge_idx, u32 msg_len) 194 { 195 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 196 unsigned int left_len_in_pg; 197 unsigned int idx = *sge_idx; 198 unsigned int i = 0; 199 unsigned int len; 200 void *addr; 201 void *dseg; 202 203 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 204 ibdev_err(ibdev, 205 "no enough extended sge space for inline data.\n"); 206 return -EINVAL; 207 } 208 209 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 210 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 211 len = wr->sg_list[0].length; 212 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 213 214 /* When copying data to extended sge space, the left length in page may 215 * not long enough for current user's sge. So the data should be 216 * splited into several parts, one in the first page, and the others in 217 * the subsequent pages. 218 */ 219 while (1) { 220 if (len <= left_len_in_pg) { 221 memcpy(dseg, addr, len); 222 223 idx += len / HNS_ROCE_SGE_SIZE; 224 225 i++; 226 if (i >= wr->num_sge) 227 break; 228 229 left_len_in_pg -= len; 230 len = wr->sg_list[i].length; 231 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 232 dseg += len; 233 } else { 234 memcpy(dseg, addr, left_len_in_pg); 235 236 len -= left_len_in_pg; 237 addr += left_len_in_pg; 238 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 239 dseg = hns_roce_get_extend_sge(qp, 240 idx & (qp->sge.sge_cnt - 1)); 241 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 242 } 243 } 244 245 *sge_idx = idx; 246 247 return 0; 248 } 249 250 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 251 unsigned int *sge_ind, unsigned int cnt) 252 { 253 struct hns_roce_v2_wqe_data_seg *dseg; 254 unsigned int idx = *sge_ind; 255 256 while (cnt > 0) { 257 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 258 if (likely(sge->length)) { 259 set_data_seg_v2(dseg, sge); 260 idx++; 261 cnt--; 262 } 263 sge++; 264 } 265 266 *sge_ind = idx; 267 } 268 269 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 270 { 271 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 272 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 273 274 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 275 ibdev_err(&hr_dev->ib_dev, 276 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 277 len, qp->max_inline_data, mtu); 278 return false; 279 } 280 281 return true; 282 } 283 284 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 285 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 286 unsigned int *sge_idx) 287 { 288 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 289 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 290 struct ib_device *ibdev = &hr_dev->ib_dev; 291 unsigned int curr_idx = *sge_idx; 292 void *dseg = rc_sq_wqe; 293 unsigned int i; 294 int ret; 295 296 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 297 ibdev_err(ibdev, "invalid inline parameters!\n"); 298 return -EINVAL; 299 } 300 301 if (!check_inl_data_len(qp, msg_len)) 302 return -EINVAL; 303 304 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 305 306 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 307 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 308 309 for (i = 0; i < wr->num_sge; i++) { 310 memcpy(dseg, ((void *)wr->sg_list[i].addr), 311 wr->sg_list[i].length); 312 dseg += wr->sg_list[i].length; 313 } 314 } else { 315 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 316 317 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 318 if (ret) 319 return ret; 320 321 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 322 } 323 324 *sge_idx = curr_idx; 325 326 return 0; 327 } 328 329 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 330 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 331 unsigned int *sge_ind, 332 unsigned int valid_num_sge) 333 { 334 struct hns_roce_v2_wqe_data_seg *dseg = 335 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 336 struct hns_roce_qp *qp = to_hr_qp(ibqp); 337 int j = 0; 338 int i; 339 340 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 341 (*sge_ind) & (qp->sge.sge_cnt - 1)); 342 343 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 344 !!(wr->send_flags & IB_SEND_INLINE)); 345 if (wr->send_flags & IB_SEND_INLINE) 346 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 347 348 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 349 for (i = 0; i < wr->num_sge; i++) { 350 if (likely(wr->sg_list[i].length)) { 351 set_data_seg_v2(dseg, wr->sg_list + i); 352 dseg++; 353 } 354 } 355 } else { 356 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 357 if (likely(wr->sg_list[i].length)) { 358 set_data_seg_v2(dseg, wr->sg_list + i); 359 dseg++; 360 j++; 361 } 362 } 363 364 set_extend_sge(qp, wr->sg_list + i, sge_ind, 365 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 366 } 367 368 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 369 370 return 0; 371 } 372 373 static int check_send_valid(struct hns_roce_dev *hr_dev, 374 struct hns_roce_qp *hr_qp) 375 { 376 struct ib_device *ibdev = &hr_dev->ib_dev; 377 378 if (unlikely(hr_qp->state == IB_QPS_RESET || 379 hr_qp->state == IB_QPS_INIT || 380 hr_qp->state == IB_QPS_RTR)) { 381 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 382 hr_qp->state); 383 return -EINVAL; 384 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 385 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 386 hr_dev->state); 387 return -EIO; 388 } 389 390 return 0; 391 } 392 393 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 394 unsigned int *sge_len) 395 { 396 unsigned int valid_num = 0; 397 unsigned int len = 0; 398 int i; 399 400 for (i = 0; i < wr->num_sge; i++) { 401 if (likely(wr->sg_list[i].length)) { 402 len += wr->sg_list[i].length; 403 valid_num++; 404 } 405 } 406 407 *sge_len = len; 408 return valid_num; 409 } 410 411 static __le32 get_immtdata(const struct ib_send_wr *wr) 412 { 413 switch (wr->opcode) { 414 case IB_WR_SEND_WITH_IMM: 415 case IB_WR_RDMA_WRITE_WITH_IMM: 416 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 417 default: 418 return 0; 419 } 420 } 421 422 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 423 const struct ib_send_wr *wr) 424 { 425 u32 ib_op = wr->opcode; 426 427 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 428 return -EINVAL; 429 430 ud_sq_wqe->immtdata = get_immtdata(wr); 431 432 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 433 434 return 0; 435 } 436 437 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 438 struct hns_roce_ah *ah) 439 { 440 struct ib_device *ib_dev = ah->ibah.device; 441 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 442 443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 444 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 445 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 446 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 447 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 448 449 ud_sq_wqe->sgid_index = ah->av.gid_index; 450 451 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 452 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 453 454 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 455 return 0; 456 457 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 458 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 459 460 return 0; 461 } 462 463 static inline int set_ud_wqe(struct hns_roce_qp *qp, 464 const struct ib_send_wr *wr, 465 void *wqe, unsigned int *sge_idx, 466 unsigned int owner_bit) 467 { 468 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 469 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 470 unsigned int curr_idx = *sge_idx; 471 unsigned int valid_num_sge; 472 u32 msg_len = 0; 473 int ret; 474 475 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 476 477 ret = set_ud_opcode(ud_sq_wqe, wr); 478 if (WARN_ON(ret)) 479 return ret; 480 481 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 482 483 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 484 !!(wr->send_flags & IB_SEND_SIGNALED)); 485 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 486 !!(wr->send_flags & IB_SEND_SOLICITED)); 487 488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 489 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 490 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 491 curr_idx & (qp->sge.sge_cnt - 1)); 492 493 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 494 qp->qkey : ud_wr(wr)->remote_qkey); 495 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 496 497 ret = fill_ud_av(ud_sq_wqe, ah); 498 if (ret) 499 return ret; 500 501 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 502 503 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 504 505 /* 506 * The pipeline can sequentially post all valid WQEs into WQ buffer, 507 * including new WQEs waiting for the doorbell to update the PI again. 508 * Therefore, the owner bit of WQE MUST be updated after all fields 509 * and extSGEs have been written into DDR instead of cache. 510 */ 511 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 512 dma_wmb(); 513 514 *sge_idx = curr_idx; 515 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 516 517 return 0; 518 } 519 520 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 521 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 522 const struct ib_send_wr *wr) 523 { 524 u32 ib_op = wr->opcode; 525 int ret = 0; 526 527 rc_sq_wqe->immtdata = get_immtdata(wr); 528 529 switch (ib_op) { 530 case IB_WR_RDMA_READ: 531 case IB_WR_RDMA_WRITE: 532 case IB_WR_RDMA_WRITE_WITH_IMM: 533 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 534 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 535 break; 536 case IB_WR_SEND: 537 case IB_WR_SEND_WITH_IMM: 538 break; 539 case IB_WR_ATOMIC_CMP_AND_SWP: 540 case IB_WR_ATOMIC_FETCH_AND_ADD: 541 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 542 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 543 break; 544 case IB_WR_REG_MR: 545 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 546 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 547 else 548 ret = -EOPNOTSUPP; 549 break; 550 case IB_WR_SEND_WITH_INV: 551 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 552 break; 553 default: 554 ret = -EINVAL; 555 } 556 557 if (unlikely(ret)) 558 return ret; 559 560 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 561 562 return ret; 563 } 564 565 static inline int set_rc_wqe(struct hns_roce_qp *qp, 566 const struct ib_send_wr *wr, 567 void *wqe, unsigned int *sge_idx, 568 unsigned int owner_bit) 569 { 570 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 571 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 572 unsigned int curr_idx = *sge_idx; 573 unsigned int valid_num_sge; 574 u32 msg_len = 0; 575 int ret; 576 577 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 578 579 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 580 581 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 582 if (WARN_ON(ret)) 583 return ret; 584 585 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 586 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 587 588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 589 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 590 591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 592 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 593 594 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 595 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { 596 if (msg_len != ATOMIC_WR_LEN) 597 return -EINVAL; 598 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 599 } else if (wr->opcode != IB_WR_REG_MR) { 600 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 601 &curr_idx, valid_num_sge); 602 if (ret) 603 return ret; 604 } 605 606 /* 607 * The pipeline can sequentially post all valid WQEs into WQ buffer, 608 * including new WQEs waiting for the doorbell to update the PI again. 609 * Therefore, the owner bit of WQE MUST be updated after all fields 610 * and extSGEs have been written into DDR instead of cache. 611 */ 612 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 613 dma_wmb(); 614 615 *sge_idx = curr_idx; 616 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 617 618 return ret; 619 } 620 621 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 622 struct hns_roce_qp *qp) 623 { 624 if (unlikely(qp->state == IB_QPS_ERR)) { 625 flush_cqe(hr_dev, qp); 626 } else { 627 struct hns_roce_v2_db sq_db = {}; 628 629 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 630 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 631 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 632 hr_reg_write(&sq_db, DB_SL, qp->sl); 633 634 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 635 } 636 } 637 638 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 639 struct hns_roce_qp *qp) 640 { 641 if (unlikely(qp->state == IB_QPS_ERR)) { 642 flush_cqe(hr_dev, qp); 643 } else { 644 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 645 *qp->rdb.db_record = 646 qp->rq.head & V2_DB_PRODUCER_IDX_M; 647 } else { 648 struct hns_roce_v2_db rq_db = {}; 649 650 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 651 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 652 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 653 654 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 655 qp->rq.db_reg); 656 } 657 } 658 } 659 660 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 661 u64 __iomem *dest) 662 { 663 #define HNS_ROCE_WRITE_TIMES 8 664 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 665 struct hnae3_handle *handle = priv->handle; 666 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 667 int i; 668 669 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 670 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 671 writeq_relaxed(*(val + i), dest + i); 672 } 673 674 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 675 void *wqe) 676 { 677 #define HNS_ROCE_SL_SHIFT 2 678 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 679 680 /* All kinds of DirectWQE have the same header field layout */ 681 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 682 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 683 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 684 qp->sl >> HNS_ROCE_SL_SHIFT); 685 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 686 687 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 688 } 689 690 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 691 const struct ib_send_wr *wr, 692 const struct ib_send_wr **bad_wr) 693 { 694 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 695 struct ib_device *ibdev = &hr_dev->ib_dev; 696 struct hns_roce_qp *qp = to_hr_qp(ibqp); 697 unsigned long flags = 0; 698 unsigned int owner_bit; 699 unsigned int sge_idx; 700 unsigned int wqe_idx; 701 void *wqe = NULL; 702 u32 nreq; 703 int ret; 704 705 spin_lock_irqsave(&qp->sq.lock, flags); 706 707 ret = check_send_valid(hr_dev, qp); 708 if (unlikely(ret)) { 709 *bad_wr = wr; 710 nreq = 0; 711 goto out; 712 } 713 714 sge_idx = qp->next_sge; 715 716 for (nreq = 0; wr; ++nreq, wr = wr->next) { 717 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 718 ret = -ENOMEM; 719 *bad_wr = wr; 720 goto out; 721 } 722 723 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 724 725 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 726 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 727 wr->num_sge, qp->sq.max_gs); 728 ret = -EINVAL; 729 *bad_wr = wr; 730 goto out; 731 } 732 733 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 734 qp->sq.wrid[wqe_idx] = wr->wr_id; 735 owner_bit = 736 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 737 738 /* Corresponding to the QP type, wqe process separately */ 739 if (ibqp->qp_type == IB_QPT_RC) 740 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 741 else 742 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 743 744 if (unlikely(ret)) { 745 *bad_wr = wr; 746 goto out; 747 } 748 } 749 750 out: 751 if (likely(nreq)) { 752 qp->sq.head += nreq; 753 qp->next_sge = sge_idx; 754 755 if (nreq == 1 && !ret && 756 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 757 write_dwqe(hr_dev, qp, wqe); 758 else 759 update_sq_db(hr_dev, qp); 760 } 761 762 spin_unlock_irqrestore(&qp->sq.lock, flags); 763 764 return ret; 765 } 766 767 static int check_recv_valid(struct hns_roce_dev *hr_dev, 768 struct hns_roce_qp *hr_qp) 769 { 770 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 771 return -EIO; 772 773 if (hr_qp->state == IB_QPS_RESET) 774 return -EINVAL; 775 776 return 0; 777 } 778 779 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 780 u32 max_sge, bool rsv) 781 { 782 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 783 u32 i, cnt; 784 785 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 786 /* Skip zero-length sge */ 787 if (!wr->sg_list[i].length) 788 continue; 789 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 790 cnt++; 791 } 792 793 /* Fill a reserved sge to make hw stop reading remaining segments */ 794 if (rsv) { 795 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 796 dseg[cnt].addr = 0; 797 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 798 } else { 799 /* Clear remaining segments to make ROCEE ignore sges */ 800 if (cnt < max_sge) 801 memset(dseg + cnt, 0, 802 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 803 } 804 } 805 806 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 807 u32 wqe_idx, u32 max_sge) 808 { 809 void *wqe = NULL; 810 811 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 812 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 813 } 814 815 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 816 const struct ib_recv_wr *wr, 817 const struct ib_recv_wr **bad_wr) 818 { 819 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 820 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 821 struct ib_device *ibdev = &hr_dev->ib_dev; 822 u32 wqe_idx, nreq, max_sge; 823 unsigned long flags; 824 int ret; 825 826 spin_lock_irqsave(&hr_qp->rq.lock, flags); 827 828 ret = check_recv_valid(hr_dev, hr_qp); 829 if (unlikely(ret)) { 830 *bad_wr = wr; 831 nreq = 0; 832 goto out; 833 } 834 835 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 836 for (nreq = 0; wr; ++nreq, wr = wr->next) { 837 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 838 hr_qp->ibqp.recv_cq))) { 839 ret = -ENOMEM; 840 *bad_wr = wr; 841 goto out; 842 } 843 844 if (unlikely(wr->num_sge > max_sge)) { 845 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 846 wr->num_sge, max_sge); 847 ret = -EINVAL; 848 *bad_wr = wr; 849 goto out; 850 } 851 852 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 853 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 854 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 855 } 856 857 out: 858 if (likely(nreq)) { 859 hr_qp->rq.head += nreq; 860 861 update_rq_db(hr_dev, hr_qp); 862 } 863 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 864 865 return ret; 866 } 867 868 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 869 { 870 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 871 } 872 873 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 874 { 875 return hns_roce_buf_offset(idx_que->mtr.kmem, 876 n << idx_que->entry_shift); 877 } 878 879 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 880 { 881 /* always called with interrupts disabled. */ 882 spin_lock(&srq->lock); 883 884 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 885 srq->idx_que.tail++; 886 887 spin_unlock(&srq->lock); 888 } 889 890 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 891 { 892 struct hns_roce_idx_que *idx_que = &srq->idx_que; 893 894 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 895 } 896 897 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 898 const struct ib_recv_wr *wr) 899 { 900 struct ib_device *ib_dev = srq->ibsrq.device; 901 902 if (unlikely(wr->num_sge > max_sge)) { 903 ibdev_err(ib_dev, 904 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 905 wr->num_sge, max_sge); 906 return -EINVAL; 907 } 908 909 if (unlikely(hns_roce_srqwq_overflow(srq))) { 910 ibdev_err(ib_dev, 911 "failed to check srqwq status, srqwq is full.\n"); 912 return -ENOMEM; 913 } 914 915 return 0; 916 } 917 918 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 919 { 920 struct hns_roce_idx_que *idx_que = &srq->idx_que; 921 u32 pos; 922 923 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 924 if (unlikely(pos == srq->wqe_cnt)) 925 return -ENOSPC; 926 927 bitmap_set(idx_que->bitmap, pos, 1); 928 *wqe_idx = pos; 929 return 0; 930 } 931 932 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 933 { 934 struct hns_roce_idx_que *idx_que = &srq->idx_que; 935 unsigned int head; 936 __le32 *buf; 937 938 head = idx_que->head & (srq->wqe_cnt - 1); 939 940 buf = get_idx_buf(idx_que, head); 941 *buf = cpu_to_le32(wqe_idx); 942 943 idx_que->head++; 944 } 945 946 static void update_srq_db(struct hns_roce_srq *srq) 947 { 948 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 949 struct hns_roce_v2_db db; 950 951 hr_reg_write(&db, DB_TAG, srq->srqn); 952 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 953 hr_reg_write(&db, DB_PI, srq->idx_que.head); 954 955 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 956 } 957 958 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 959 const struct ib_recv_wr *wr, 960 const struct ib_recv_wr **bad_wr) 961 { 962 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 963 unsigned long flags; 964 int ret = 0; 965 u32 max_sge; 966 u32 wqe_idx; 967 void *wqe; 968 u32 nreq; 969 970 spin_lock_irqsave(&srq->lock, flags); 971 972 max_sge = srq->max_gs - srq->rsv_sge; 973 for (nreq = 0; wr; ++nreq, wr = wr->next) { 974 ret = check_post_srq_valid(srq, max_sge, wr); 975 if (ret) { 976 *bad_wr = wr; 977 break; 978 } 979 980 ret = get_srq_wqe_idx(srq, &wqe_idx); 981 if (unlikely(ret)) { 982 *bad_wr = wr; 983 break; 984 } 985 986 wqe = get_srq_wqe_buf(srq, wqe_idx); 987 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 988 fill_wqe_idx(srq, wqe_idx); 989 srq->wrid[wqe_idx] = wr->wr_id; 990 } 991 992 if (likely(nreq)) { 993 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 994 *srq->rdb.db_record = srq->idx_que.head & 995 V2_DB_PRODUCER_IDX_M; 996 else 997 update_srq_db(srq); 998 } 999 1000 spin_unlock_irqrestore(&srq->lock, flags); 1001 1002 return ret; 1003 } 1004 1005 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1006 unsigned long instance_stage, 1007 unsigned long reset_stage) 1008 { 1009 /* When hardware reset has been completed once or more, we should stop 1010 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1011 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1012 * stage of soft reset process, we should exit with error, and then 1013 * HNAE3_INIT_CLIENT related process can rollback the operation like 1014 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1015 * process will exit with error to notify NIC driver to reschedule soft 1016 * reset process once again. 1017 */ 1018 hr_dev->is_reset = true; 1019 hr_dev->dis_db = true; 1020 1021 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1022 instance_stage == HNS_ROCE_STATE_INIT) 1023 return CMD_RST_PRC_EBUSY; 1024 1025 return CMD_RST_PRC_SUCCESS; 1026 } 1027 1028 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1029 unsigned long instance_stage, 1030 unsigned long reset_stage) 1031 { 1032 #define HW_RESET_TIMEOUT_US 1000000 1033 #define HW_RESET_SLEEP_US 1000 1034 1035 struct hns_roce_v2_priv *priv = hr_dev->priv; 1036 struct hnae3_handle *handle = priv->handle; 1037 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1038 unsigned long val; 1039 int ret; 1040 1041 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1042 * doorbell to hardware. If now in .init_instance() function, we should 1043 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1044 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1045 * related process can rollback the operation like notifing hardware to 1046 * free resources, HNAE3_INIT_CLIENT related process will exit with 1047 * error to notify NIC driver to reschedule soft reset process once 1048 * again. 1049 */ 1050 hr_dev->dis_db = true; 1051 1052 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1053 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1054 HW_RESET_TIMEOUT_US, false, handle); 1055 if (!ret) 1056 hr_dev->is_reset = true; 1057 1058 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1059 instance_stage == HNS_ROCE_STATE_INIT) 1060 return CMD_RST_PRC_EBUSY; 1061 1062 return CMD_RST_PRC_SUCCESS; 1063 } 1064 1065 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1066 { 1067 struct hns_roce_v2_priv *priv = hr_dev->priv; 1068 struct hnae3_handle *handle = priv->handle; 1069 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1070 1071 /* When software reset is detected at .init_instance() function, we 1072 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1073 * with error. 1074 */ 1075 hr_dev->dis_db = true; 1076 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1077 hr_dev->is_reset = true; 1078 1079 return CMD_RST_PRC_EBUSY; 1080 } 1081 1082 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1083 struct hnae3_handle *handle) 1084 { 1085 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1086 unsigned long instance_stage; /* the current instance stage */ 1087 unsigned long reset_stage; /* the current reset stage */ 1088 unsigned long reset_cnt; 1089 bool sw_resetting; 1090 bool hw_resetting; 1091 1092 /* Get information about reset from NIC driver or RoCE driver itself, 1093 * the meaning of the following variables from NIC driver are described 1094 * as below: 1095 * reset_cnt -- The count value of completed hardware reset. 1096 * hw_resetting -- Whether hardware device is resetting now. 1097 * sw_resetting -- Whether NIC's software reset process is running now. 1098 */ 1099 instance_stage = handle->rinfo.instance_state; 1100 reset_stage = handle->rinfo.reset_state; 1101 reset_cnt = ops->ae_dev_reset_cnt(handle); 1102 if (reset_cnt != hr_dev->reset_cnt) 1103 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1104 reset_stage); 1105 1106 hw_resetting = ops->get_cmdq_stat(handle); 1107 if (hw_resetting) 1108 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1109 reset_stage); 1110 1111 sw_resetting = ops->ae_dev_resetting(handle); 1112 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1113 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1114 1115 return CMD_RST_PRC_OTHERS; 1116 } 1117 1118 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1119 { 1120 struct hns_roce_v2_priv *priv = hr_dev->priv; 1121 struct hnae3_handle *handle = priv->handle; 1122 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1123 1124 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1125 return true; 1126 1127 if (ops->get_hw_reset_stat(handle)) 1128 return true; 1129 1130 if (ops->ae_dev_resetting(handle)) 1131 return true; 1132 1133 return false; 1134 } 1135 1136 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1137 { 1138 struct hns_roce_v2_priv *priv = hr_dev->priv; 1139 u32 status; 1140 1141 if (hr_dev->is_reset) 1142 status = CMD_RST_PRC_SUCCESS; 1143 else 1144 status = check_aedev_reset_status(hr_dev, priv->handle); 1145 1146 *busy = (status == CMD_RST_PRC_EBUSY); 1147 1148 return status == CMD_RST_PRC_OTHERS; 1149 } 1150 1151 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1152 struct hns_roce_v2_cmq_ring *ring) 1153 { 1154 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1155 1156 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1157 &ring->desc_dma_addr, GFP_KERNEL); 1158 if (!ring->desc) 1159 return -ENOMEM; 1160 1161 return 0; 1162 } 1163 1164 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1165 struct hns_roce_v2_cmq_ring *ring) 1166 { 1167 dma_free_coherent(hr_dev->dev, 1168 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1169 ring->desc, ring->desc_dma_addr); 1170 1171 ring->desc_dma_addr = 0; 1172 } 1173 1174 static int init_csq(struct hns_roce_dev *hr_dev, 1175 struct hns_roce_v2_cmq_ring *csq) 1176 { 1177 dma_addr_t dma; 1178 int ret; 1179 1180 csq->desc_num = CMD_CSQ_DESC_NUM; 1181 spin_lock_init(&csq->lock); 1182 csq->flag = TYPE_CSQ; 1183 csq->head = 0; 1184 1185 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1186 if (ret) 1187 return ret; 1188 1189 dma = csq->desc_dma_addr; 1190 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1191 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1192 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1193 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1194 1195 /* Make sure to write CI first and then PI */ 1196 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1197 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1198 1199 return 0; 1200 } 1201 1202 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1203 { 1204 struct hns_roce_v2_priv *priv = hr_dev->priv; 1205 int ret; 1206 1207 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1208 1209 ret = init_csq(hr_dev, &priv->cmq.csq); 1210 if (ret) 1211 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1212 1213 return ret; 1214 } 1215 1216 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1217 { 1218 struct hns_roce_v2_priv *priv = hr_dev->priv; 1219 1220 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1221 } 1222 1223 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1224 enum hns_roce_opcode_type opcode, 1225 bool is_read) 1226 { 1227 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1228 desc->opcode = cpu_to_le16(opcode); 1229 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1230 if (is_read) 1231 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1232 else 1233 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1234 } 1235 1236 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1237 { 1238 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1239 struct hns_roce_v2_priv *priv = hr_dev->priv; 1240 1241 return tail == priv->cmq.csq.head; 1242 } 1243 1244 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1245 { 1246 struct hns_roce_v2_priv *priv = hr_dev->priv; 1247 struct hnae3_handle *handle = priv->handle; 1248 1249 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1250 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1251 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1252 } 1253 1254 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1255 { 1256 struct hns_roce_cmd_errcode errcode_table[] = { 1257 {CMD_EXEC_SUCCESS, 0}, 1258 {CMD_NO_AUTH, -EPERM}, 1259 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1260 {CMD_CRQ_FULL, -EXFULL}, 1261 {CMD_NEXT_ERR, -ENOSR}, 1262 {CMD_NOT_EXEC, -ENOTBLK}, 1263 {CMD_PARA_ERR, -EINVAL}, 1264 {CMD_RESULT_ERR, -ERANGE}, 1265 {CMD_TIMEOUT, -ETIME}, 1266 {CMD_HILINK_ERR, -ENOLINK}, 1267 {CMD_INFO_ILLEGAL, -ENXIO}, 1268 {CMD_INVALID, -EBADR}, 1269 }; 1270 u16 i; 1271 1272 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1273 if (desc_ret == errcode_table[i].return_status) 1274 return errcode_table[i].errno; 1275 return -EIO; 1276 } 1277 1278 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 1279 { 1280 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = { 1281 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT}, 1282 }; 1283 int i; 1284 1285 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++) 1286 if (cmdq_tx_timeout[i].opcode == opcode) 1287 return cmdq_tx_timeout[i].tx_timeout; 1288 1289 return tx_timeout; 1290 } 1291 1292 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u16 opcode) 1293 { 1294 struct hns_roce_v2_priv *priv = hr_dev->priv; 1295 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout); 1296 u32 timeout = 0; 1297 1298 do { 1299 if (hns_roce_cmq_csq_done(hr_dev)) 1300 break; 1301 udelay(1); 1302 } while (++timeout < tx_timeout); 1303 } 1304 1305 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1306 struct hns_roce_cmq_desc *desc, int num) 1307 { 1308 struct hns_roce_v2_priv *priv = hr_dev->priv; 1309 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1310 u16 desc_ret; 1311 u32 tail; 1312 int ret; 1313 int i; 1314 1315 spin_lock_bh(&csq->lock); 1316 1317 tail = csq->head; 1318 1319 for (i = 0; i < num; i++) { 1320 csq->desc[csq->head++] = desc[i]; 1321 if (csq->head == csq->desc_num) 1322 csq->head = 0; 1323 } 1324 1325 /* Write to hardware */ 1326 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1327 1328 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]); 1329 1330 hns_roce_wait_csq_done(hr_dev, le16_to_cpu(desc->opcode)); 1331 if (hns_roce_cmq_csq_done(hr_dev)) { 1332 ret = 0; 1333 for (i = 0; i < num; i++) { 1334 /* check the result of hardware write back */ 1335 desc[i] = csq->desc[tail++]; 1336 if (tail == csq->desc_num) 1337 tail = 0; 1338 1339 desc_ret = le16_to_cpu(desc[i].retval); 1340 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1341 continue; 1342 1343 dev_err_ratelimited(hr_dev->dev, 1344 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1345 desc->opcode, desc_ret); 1346 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1347 } 1348 } else { 1349 /* FW/HW reset or incorrect number of desc */ 1350 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1351 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1352 csq->head, tail); 1353 csq->head = tail; 1354 1355 update_cmdq_status(hr_dev); 1356 1357 ret = -EAGAIN; 1358 } 1359 1360 spin_unlock_bh(&csq->lock); 1361 1362 if (ret) 1363 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]); 1364 1365 return ret; 1366 } 1367 1368 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1369 struct hns_roce_cmq_desc *desc, int num) 1370 { 1371 bool busy; 1372 int ret; 1373 1374 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1375 return -EIO; 1376 1377 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1378 return busy ? -EBUSY : 0; 1379 1380 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1381 if (ret) { 1382 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1383 return busy ? -EBUSY : 0; 1384 } 1385 1386 return ret; 1387 } 1388 1389 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1390 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1391 { 1392 struct hns_roce_cmd_mailbox *mbox; 1393 int ret; 1394 1395 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1396 if (IS_ERR(mbox)) 1397 return PTR_ERR(mbox); 1398 1399 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1400 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1401 return ret; 1402 } 1403 1404 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1405 { 1406 struct hns_roce_query_version *resp; 1407 struct hns_roce_cmq_desc desc; 1408 int ret; 1409 1410 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1411 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1412 if (ret) 1413 return ret; 1414 1415 resp = (struct hns_roce_query_version *)desc.data; 1416 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1417 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1418 1419 return 0; 1420 } 1421 1422 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1423 struct hnae3_handle *handle) 1424 { 1425 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1426 unsigned long end; 1427 1428 hr_dev->dis_db = true; 1429 1430 dev_warn(hr_dev->dev, 1431 "func clear is pending, device in resetting state.\n"); 1432 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1433 while (end) { 1434 if (!ops->get_hw_reset_stat(handle)) { 1435 hr_dev->is_reset = true; 1436 dev_info(hr_dev->dev, 1437 "func clear success after reset.\n"); 1438 return; 1439 } 1440 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1441 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1442 } 1443 1444 dev_warn(hr_dev->dev, "func clear failed.\n"); 1445 } 1446 1447 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1448 struct hnae3_handle *handle) 1449 { 1450 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1451 unsigned long end; 1452 1453 hr_dev->dis_db = true; 1454 1455 dev_warn(hr_dev->dev, 1456 "func clear is pending, device in resetting state.\n"); 1457 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1458 while (end) { 1459 if (ops->ae_dev_reset_cnt(handle) != 1460 hr_dev->reset_cnt) { 1461 hr_dev->is_reset = true; 1462 dev_info(hr_dev->dev, 1463 "func clear success after sw reset\n"); 1464 return; 1465 } 1466 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1467 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1468 } 1469 1470 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1471 } 1472 1473 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1474 int flag) 1475 { 1476 struct hns_roce_v2_priv *priv = hr_dev->priv; 1477 struct hnae3_handle *handle = priv->handle; 1478 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1479 1480 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1481 hr_dev->dis_db = true; 1482 hr_dev->is_reset = true; 1483 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1484 return; 1485 } 1486 1487 if (ops->get_hw_reset_stat(handle)) { 1488 func_clr_hw_resetting_state(hr_dev, handle); 1489 return; 1490 } 1491 1492 if (ops->ae_dev_resetting(handle) && 1493 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1494 func_clr_sw_resetting_state(hr_dev, handle); 1495 return; 1496 } 1497 1498 if (retval && !flag) 1499 dev_warn(hr_dev->dev, 1500 "func clear read failed, ret = %d.\n", retval); 1501 1502 dev_warn(hr_dev->dev, "func clear failed.\n"); 1503 } 1504 1505 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1506 { 1507 bool fclr_write_fail_flag = false; 1508 struct hns_roce_func_clear *resp; 1509 struct hns_roce_cmq_desc desc; 1510 unsigned long end; 1511 int ret = 0; 1512 1513 if (check_device_is_in_reset(hr_dev)) 1514 goto out; 1515 1516 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1517 resp = (struct hns_roce_func_clear *)desc.data; 1518 resp->rst_funcid_en = cpu_to_le32(vf_id); 1519 1520 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1521 if (ret) { 1522 fclr_write_fail_flag = true; 1523 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1524 ret); 1525 goto out; 1526 } 1527 1528 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1529 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1530 while (end) { 1531 if (check_device_is_in_reset(hr_dev)) 1532 goto out; 1533 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1534 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1535 1536 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1537 true); 1538 1539 resp->rst_funcid_en = cpu_to_le32(vf_id); 1540 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1541 if (ret) 1542 continue; 1543 1544 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1545 if (vf_id == 0) 1546 hr_dev->is_reset = true; 1547 return; 1548 } 1549 } 1550 1551 out: 1552 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1553 } 1554 1555 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1556 { 1557 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1558 struct hns_roce_cmq_desc desc[2]; 1559 struct hns_roce_cmq_req *req_a; 1560 1561 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1562 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1563 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1564 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1565 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1566 1567 return hns_roce_cmq_send(hr_dev, desc, 2); 1568 } 1569 1570 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1571 { 1572 int ret; 1573 int i; 1574 1575 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1576 return; 1577 1578 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1579 __hns_roce_function_clear(hr_dev, i); 1580 1581 if (i == 0) 1582 continue; 1583 1584 ret = hns_roce_free_vf_resource(hr_dev, i); 1585 if (ret) 1586 ibdev_err(&hr_dev->ib_dev, 1587 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1588 i, ret); 1589 } 1590 } 1591 1592 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1593 { 1594 struct hns_roce_cmq_desc desc; 1595 int ret; 1596 1597 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1598 false); 1599 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1600 if (ret) 1601 ibdev_err(&hr_dev->ib_dev, 1602 "failed to clear extended doorbell info, ret = %d.\n", 1603 ret); 1604 1605 return ret; 1606 } 1607 1608 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1609 { 1610 struct hns_roce_query_fw_info *resp; 1611 struct hns_roce_cmq_desc desc; 1612 int ret; 1613 1614 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1615 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1616 if (ret) 1617 return ret; 1618 1619 resp = (struct hns_roce_query_fw_info *)desc.data; 1620 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1621 1622 return 0; 1623 } 1624 1625 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1626 { 1627 struct hns_roce_cmq_desc desc; 1628 int ret; 1629 1630 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1631 hr_dev->func_num = 1; 1632 return 0; 1633 } 1634 1635 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1636 true); 1637 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1638 if (ret) { 1639 hr_dev->func_num = 1; 1640 return ret; 1641 } 1642 1643 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1644 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1645 1646 return 0; 1647 } 1648 1649 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1650 u64 *stats, u32 port, int *num_counters) 1651 { 1652 #define CNT_PER_DESC 3 1653 struct hns_roce_cmq_desc *desc; 1654 int bd_idx, cnt_idx; 1655 __le64 *cnt_data; 1656 int desc_num; 1657 int ret; 1658 int i; 1659 1660 if (port > hr_dev->caps.num_ports) 1661 return -EINVAL; 1662 1663 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1664 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1665 if (!desc) 1666 return -ENOMEM; 1667 1668 for (i = 0; i < desc_num; i++) { 1669 hns_roce_cmq_setup_basic_desc(&desc[i], 1670 HNS_ROCE_OPC_QUERY_COUNTER, true); 1671 if (i != desc_num - 1) 1672 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1673 } 1674 1675 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1676 if (ret) { 1677 ibdev_err(&hr_dev->ib_dev, 1678 "failed to get counter, ret = %d.\n", ret); 1679 goto err_out; 1680 } 1681 1682 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1683 bd_idx = i / CNT_PER_DESC; 1684 if (!(desc[bd_idx].flag & HNS_ROCE_CMD_FLAG_NEXT) && 1685 bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC) 1686 break; 1687 1688 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1689 cnt_idx = i % CNT_PER_DESC; 1690 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1691 } 1692 *num_counters = i; 1693 1694 err_out: 1695 kfree(desc); 1696 return ret; 1697 } 1698 1699 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1700 { 1701 struct hns_roce_cmq_desc desc; 1702 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1703 u32 clock_cycles_of_1us; 1704 1705 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1706 false); 1707 1708 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1709 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1710 else 1711 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1712 1713 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1714 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1715 1716 return hns_roce_cmq_send(hr_dev, &desc, 1); 1717 } 1718 1719 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1720 { 1721 struct hns_roce_cmq_desc desc[2]; 1722 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1723 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1724 struct hns_roce_caps *caps = &hr_dev->caps; 1725 enum hns_roce_opcode_type opcode; 1726 u32 func_num; 1727 int ret; 1728 1729 if (is_vf) { 1730 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1731 func_num = 1; 1732 } else { 1733 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1734 func_num = hr_dev->func_num; 1735 } 1736 1737 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1738 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1739 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1740 1741 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1742 if (ret) 1743 return ret; 1744 1745 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1746 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1747 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1748 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1749 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1750 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1751 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1752 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1753 1754 if (is_vf) { 1755 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1756 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1757 func_num; 1758 } else { 1759 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1760 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1761 func_num; 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1768 { 1769 struct hns_roce_cmq_desc desc; 1770 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1771 struct hns_roce_caps *caps = &hr_dev->caps; 1772 int ret; 1773 1774 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1775 true); 1776 1777 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1778 if (ret) 1779 return ret; 1780 1781 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1782 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1783 1784 return 0; 1785 } 1786 1787 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1788 { 1789 struct device *dev = hr_dev->dev; 1790 int ret; 1791 1792 ret = load_func_res_caps(hr_dev, false); 1793 if (ret) { 1794 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1795 return ret; 1796 } 1797 1798 ret = load_pf_timer_res_caps(hr_dev); 1799 if (ret) 1800 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1801 ret); 1802 1803 return ret; 1804 } 1805 1806 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1807 { 1808 struct device *dev = hr_dev->dev; 1809 int ret; 1810 1811 ret = load_func_res_caps(hr_dev, true); 1812 if (ret) 1813 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1814 1815 return ret; 1816 } 1817 1818 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1819 u32 vf_id) 1820 { 1821 struct hns_roce_vf_switch *swt; 1822 struct hns_roce_cmq_desc desc; 1823 int ret; 1824 1825 swt = (struct hns_roce_vf_switch *)desc.data; 1826 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1827 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1828 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1829 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1830 if (ret) 1831 return ret; 1832 1833 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1834 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1835 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1836 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1837 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1838 1839 return hns_roce_cmq_send(hr_dev, &desc, 1); 1840 } 1841 1842 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1843 { 1844 u32 vf_id; 1845 int ret; 1846 1847 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1848 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1849 if (ret) 1850 return ret; 1851 } 1852 return 0; 1853 } 1854 1855 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1856 { 1857 struct hns_roce_cmq_desc desc[2]; 1858 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1859 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1860 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1861 struct hns_roce_caps *caps = &hr_dev->caps; 1862 1863 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1864 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1865 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1866 1867 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1868 1869 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1870 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1871 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1872 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1873 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1874 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1875 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1876 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1877 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1878 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1879 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1880 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1881 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1882 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1883 1884 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1885 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1886 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1887 vf_id * caps->gmv_bt_num); 1888 } else { 1889 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1890 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1891 vf_id * caps->sgid_bt_num); 1892 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1893 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1894 vf_id * caps->smac_bt_num); 1895 } 1896 1897 return hns_roce_cmq_send(hr_dev, desc, 2); 1898 } 1899 1900 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1901 { 1902 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1903 u32 vf_id; 1904 int ret; 1905 1906 for (vf_id = 0; vf_id < func_num; vf_id++) { 1907 ret = config_vf_hem_resource(hr_dev, vf_id); 1908 if (ret) { 1909 dev_err(hr_dev->dev, 1910 "failed to config vf-%u hem res, ret = %d.\n", 1911 vf_id, ret); 1912 return ret; 1913 } 1914 } 1915 1916 return 0; 1917 } 1918 1919 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1920 { 1921 struct hns_roce_cmq_desc desc; 1922 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1923 struct hns_roce_caps *caps = &hr_dev->caps; 1924 1925 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1926 1927 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1928 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1929 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1930 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1931 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1932 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1933 1934 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1935 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1936 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1937 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1938 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1939 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1940 1941 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1942 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1943 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1944 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1945 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1946 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1947 1948 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1949 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1950 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1951 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1952 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1953 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1954 1955 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1956 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1957 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1958 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1959 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1960 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1961 1962 return hns_roce_cmq_send(hr_dev, &desc, 1); 1963 } 1964 1965 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1966 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1967 { 1968 u64 obj_per_chunk; 1969 u64 bt_chunk_size = PAGE_SIZE; 1970 u64 buf_chunk_size = PAGE_SIZE; 1971 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1972 1973 *buf_page_size = 0; 1974 *bt_page_size = 0; 1975 1976 switch (hop_num) { 1977 case 3: 1978 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1979 (bt_chunk_size / BA_BYTE_LEN) * 1980 (bt_chunk_size / BA_BYTE_LEN) * 1981 obj_per_chunk_default; 1982 break; 1983 case 2: 1984 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1985 (bt_chunk_size / BA_BYTE_LEN) * 1986 obj_per_chunk_default; 1987 break; 1988 case 1: 1989 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1990 obj_per_chunk_default; 1991 break; 1992 case HNS_ROCE_HOP_NUM_0: 1993 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1994 break; 1995 default: 1996 pr_err("table %u not support hop_num = %u!\n", hem_type, 1997 hop_num); 1998 return; 1999 } 2000 2001 if (hem_type >= HEM_TYPE_MTT) 2002 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2003 else 2004 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2005 } 2006 2007 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2008 { 2009 struct hns_roce_caps *caps = &hr_dev->caps; 2010 2011 /* EQ */ 2012 caps->eqe_ba_pg_sz = 0; 2013 caps->eqe_buf_pg_sz = 0; 2014 2015 /* Link Table */ 2016 caps->llm_buf_pg_sz = 0; 2017 2018 /* MR */ 2019 caps->mpt_ba_pg_sz = 0; 2020 caps->mpt_buf_pg_sz = 0; 2021 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2022 caps->pbl_buf_pg_sz = 0; 2023 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2024 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2025 HEM_TYPE_MTPT); 2026 2027 /* QP */ 2028 caps->qpc_ba_pg_sz = 0; 2029 caps->qpc_buf_pg_sz = 0; 2030 caps->qpc_timer_ba_pg_sz = 0; 2031 caps->qpc_timer_buf_pg_sz = 0; 2032 caps->sccc_ba_pg_sz = 0; 2033 caps->sccc_buf_pg_sz = 0; 2034 caps->mtt_ba_pg_sz = 0; 2035 caps->mtt_buf_pg_sz = 0; 2036 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2037 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2038 HEM_TYPE_QPC); 2039 2040 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2041 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2042 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2043 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2044 2045 /* CQ */ 2046 caps->cqc_ba_pg_sz = 0; 2047 caps->cqc_buf_pg_sz = 0; 2048 caps->cqc_timer_ba_pg_sz = 0; 2049 caps->cqc_timer_buf_pg_sz = 0; 2050 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2051 caps->cqe_buf_pg_sz = 0; 2052 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2053 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2054 HEM_TYPE_CQC); 2055 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2056 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2057 2058 /* SRQ */ 2059 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2060 caps->srqc_ba_pg_sz = 0; 2061 caps->srqc_buf_pg_sz = 0; 2062 caps->srqwqe_ba_pg_sz = 0; 2063 caps->srqwqe_buf_pg_sz = 0; 2064 caps->idx_ba_pg_sz = 0; 2065 caps->idx_buf_pg_sz = 0; 2066 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2067 caps->srqc_hop_num, caps->srqc_bt_num, 2068 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2069 HEM_TYPE_SRQC); 2070 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2071 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2072 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2073 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2074 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2075 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2076 } 2077 2078 /* GMV */ 2079 caps->gmv_ba_pg_sz = 0; 2080 caps->gmv_buf_pg_sz = 0; 2081 } 2082 2083 /* Apply all loaded caps before setting to hardware */ 2084 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2085 { 2086 #define MAX_GID_TBL_LEN 256 2087 struct hns_roce_caps *caps = &hr_dev->caps; 2088 struct hns_roce_v2_priv *priv = hr_dev->priv; 2089 2090 /* The following configurations don't need to be got from firmware. */ 2091 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2092 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2093 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2094 2095 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2096 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2097 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2098 2099 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2100 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2101 2102 if (!caps->num_comp_vectors) 2103 caps->num_comp_vectors = 2104 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2105 (u32)priv->handle->rinfo.num_vectors - 2106 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2107 2108 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2109 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2110 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2111 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2112 2113 /* The following configurations will be overwritten */ 2114 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2115 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2116 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2117 2118 /* The following configurations are not got from firmware */ 2119 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2120 2121 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2122 2123 /* It's meaningless to support excessively large gid_table_len, 2124 * as the type of sgid_index in kernel struct ib_global_route 2125 * and userspace struct ibv_global_route are u8/uint8_t (0-255). 2126 */ 2127 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN, 2128 caps->gmv_bt_num * 2129 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz)); 2130 2131 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 2132 caps->gmv_entry_sz); 2133 } else { 2134 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2135 2136 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2137 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2138 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2139 caps->gid_table_len[0] /= func_num; 2140 } 2141 2142 if (hr_dev->is_vf) { 2143 caps->default_aeq_arm_st = 0x3; 2144 caps->default_ceq_arm_st = 0x3; 2145 caps->default_ceq_max_cnt = 0x1; 2146 caps->default_ceq_period = 0x10; 2147 caps->default_aeq_max_cnt = 0x1; 2148 caps->default_aeq_period = 0x10; 2149 } 2150 2151 set_hem_page_size(hr_dev); 2152 } 2153 2154 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2155 { 2156 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2157 struct hns_roce_caps *caps = &hr_dev->caps; 2158 struct hns_roce_query_pf_caps_a *resp_a; 2159 struct hns_roce_query_pf_caps_b *resp_b; 2160 struct hns_roce_query_pf_caps_c *resp_c; 2161 struct hns_roce_query_pf_caps_d *resp_d; 2162 struct hns_roce_query_pf_caps_e *resp_e; 2163 enum hns_roce_opcode_type cmd; 2164 int ctx_hop_num; 2165 int pbl_hop_num; 2166 int ret; 2167 int i; 2168 2169 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2170 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2171 2172 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2173 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2174 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2175 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2176 else 2177 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2178 } 2179 2180 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2181 if (ret) 2182 return ret; 2183 2184 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2185 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2186 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2187 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2188 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2189 2190 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2191 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2192 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2193 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2194 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2195 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2196 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2197 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2198 caps->num_other_vectors = resp_a->num_other_vectors; 2199 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2200 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2201 2202 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2203 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2204 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2205 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2206 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2207 caps->idx_entry_sz = resp_b->idx_entry_sz; 2208 caps->sccc_sz = resp_b->sccc_sz; 2209 caps->max_mtu = resp_b->max_mtu; 2210 caps->min_cqes = resp_b->min_cqes; 2211 caps->min_wqes = resp_b->min_wqes; 2212 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2213 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2214 caps->phy_num_uars = resp_b->phy_num_uars; 2215 ctx_hop_num = resp_b->ctx_hop_num; 2216 pbl_hop_num = resp_b->pbl_hop_num; 2217 2218 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2219 2220 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2221 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2222 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2223 2224 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2225 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2226 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2227 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2228 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2229 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2230 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2231 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2232 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2233 2234 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2235 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP); 2236 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2237 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2238 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2239 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2240 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG); 2241 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2242 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2243 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2244 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2245 2246 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2247 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2248 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2249 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2250 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2251 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2252 2253 caps->qpc_hop_num = ctx_hop_num; 2254 caps->sccc_hop_num = ctx_hop_num; 2255 caps->srqc_hop_num = ctx_hop_num; 2256 caps->cqc_hop_num = ctx_hop_num; 2257 caps->mpt_hop_num = ctx_hop_num; 2258 caps->mtt_hop_num = pbl_hop_num; 2259 caps->cqe_hop_num = pbl_hop_num; 2260 caps->srqwqe_hop_num = pbl_hop_num; 2261 caps->idx_hop_num = pbl_hop_num; 2262 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2263 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2264 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2265 2266 if (!(caps->page_size_cap & PAGE_SIZE)) 2267 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2268 2269 if (!hr_dev->is_vf) { 2270 caps->cqe_sz = resp_a->cqe_sz; 2271 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2272 caps->default_aeq_arm_st = 2273 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2274 caps->default_ceq_arm_st = 2275 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2276 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2277 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2278 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2279 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2280 } 2281 2282 return 0; 2283 } 2284 2285 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2286 { 2287 struct hns_roce_cmq_desc desc; 2288 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2289 2290 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2291 false); 2292 2293 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2294 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2295 2296 return hns_roce_cmq_send(hr_dev, &desc, 1); 2297 } 2298 2299 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2300 { 2301 struct hns_roce_caps *caps = &hr_dev->caps; 2302 int ret; 2303 2304 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2305 return 0; 2306 2307 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2308 caps->qpc_sz); 2309 if (ret) { 2310 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2311 return ret; 2312 } 2313 2314 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2315 caps->sccc_sz); 2316 if (ret) 2317 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2318 2319 return ret; 2320 } 2321 2322 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2323 { 2324 struct device *dev = hr_dev->dev; 2325 int ret; 2326 2327 hr_dev->func_num = 1; 2328 2329 ret = hns_roce_query_caps(hr_dev); 2330 if (ret) { 2331 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2332 return ret; 2333 } 2334 2335 ret = hns_roce_query_vf_resource(hr_dev); 2336 if (ret) { 2337 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2338 return ret; 2339 } 2340 2341 apply_func_caps(hr_dev); 2342 2343 ret = hns_roce_v2_set_bt(hr_dev); 2344 if (ret) 2345 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2346 2347 return ret; 2348 } 2349 2350 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2351 { 2352 struct device *dev = hr_dev->dev; 2353 int ret; 2354 2355 ret = hns_roce_query_func_info(hr_dev); 2356 if (ret) { 2357 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2358 return ret; 2359 } 2360 2361 ret = hns_roce_config_global_param(hr_dev); 2362 if (ret) { 2363 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2364 return ret; 2365 } 2366 2367 ret = hns_roce_set_vf_switch_param(hr_dev); 2368 if (ret) { 2369 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2370 return ret; 2371 } 2372 2373 ret = hns_roce_query_caps(hr_dev); 2374 if (ret) { 2375 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2376 return ret; 2377 } 2378 2379 ret = hns_roce_query_pf_resource(hr_dev); 2380 if (ret) { 2381 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2382 return ret; 2383 } 2384 2385 apply_func_caps(hr_dev); 2386 2387 ret = hns_roce_alloc_vf_resource(hr_dev); 2388 if (ret) { 2389 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2390 return ret; 2391 } 2392 2393 ret = hns_roce_v2_set_bt(hr_dev); 2394 if (ret) { 2395 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2396 return ret; 2397 } 2398 2399 /* Configure the size of QPC, SCCC, etc. */ 2400 return hns_roce_config_entry_size(hr_dev); 2401 } 2402 2403 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2404 { 2405 struct device *dev = hr_dev->dev; 2406 int ret; 2407 2408 ret = hns_roce_cmq_query_hw_info(hr_dev); 2409 if (ret) { 2410 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2411 return ret; 2412 } 2413 2414 ret = hns_roce_query_fw_ver(hr_dev); 2415 if (ret) { 2416 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2417 return ret; 2418 } 2419 2420 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2421 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2422 2423 if (hr_dev->is_vf) 2424 return hns_roce_v2_vf_profile(hr_dev); 2425 else 2426 return hns_roce_v2_pf_profile(hr_dev); 2427 } 2428 2429 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2430 { 2431 u32 i, next_ptr, page_num; 2432 __le64 *entry = cfg_buf; 2433 dma_addr_t addr; 2434 u64 val; 2435 2436 page_num = data_buf->npages; 2437 for (i = 0; i < page_num; i++) { 2438 addr = hns_roce_buf_page(data_buf, i); 2439 if (i == (page_num - 1)) 2440 next_ptr = 0; 2441 else 2442 next_ptr = i + 1; 2443 2444 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2445 entry[i] = cpu_to_le64(val); 2446 } 2447 } 2448 2449 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2450 struct hns_roce_link_table *table) 2451 { 2452 struct hns_roce_cmq_desc desc[2]; 2453 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2454 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2455 struct hns_roce_buf *buf = table->buf; 2456 enum hns_roce_opcode_type opcode; 2457 dma_addr_t addr; 2458 2459 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2460 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2461 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2462 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2463 2464 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2465 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2466 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2467 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2468 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2469 2470 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2471 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2472 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2473 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2474 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2475 2476 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2477 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2478 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2479 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2480 2481 return hns_roce_cmq_send(hr_dev, desc, 2); 2482 } 2483 2484 static struct hns_roce_link_table * 2485 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2486 { 2487 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num; 2488 struct hns_roce_v2_priv *priv = hr_dev->priv; 2489 struct hns_roce_link_table *link_tbl; 2490 u32 pg_shift, size, min_size; 2491 2492 link_tbl = &priv->ext_llm; 2493 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2494 size = hr_dev->caps.num_qps * hr_dev->func_num * 2495 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2496 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift; 2497 2498 /* Alloc data table */ 2499 size = max(size, min_size); 2500 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2501 if (IS_ERR(link_tbl->buf)) 2502 return ERR_PTR(-ENOMEM); 2503 2504 /* Alloc config table */ 2505 size = link_tbl->buf->npages * sizeof(u64); 2506 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2507 &link_tbl->table.map, 2508 GFP_KERNEL); 2509 if (!link_tbl->table.buf) { 2510 hns_roce_buf_free(hr_dev, link_tbl->buf); 2511 return ERR_PTR(-ENOMEM); 2512 } 2513 2514 return link_tbl; 2515 } 2516 2517 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2518 struct hns_roce_link_table *tbl) 2519 { 2520 if (tbl->buf) { 2521 u32 size = tbl->buf->npages * sizeof(u64); 2522 2523 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2524 tbl->table.map); 2525 } 2526 2527 hns_roce_buf_free(hr_dev, tbl->buf); 2528 } 2529 2530 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2531 { 2532 struct hns_roce_link_table *link_tbl; 2533 int ret; 2534 2535 link_tbl = alloc_link_table_buf(hr_dev); 2536 if (IS_ERR(link_tbl)) 2537 return -ENOMEM; 2538 2539 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2540 ret = -EINVAL; 2541 goto err_alloc; 2542 } 2543 2544 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2545 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2546 if (ret) 2547 goto err_alloc; 2548 2549 return 0; 2550 2551 err_alloc: 2552 free_link_table_buf(hr_dev, link_tbl); 2553 return ret; 2554 } 2555 2556 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2557 { 2558 struct hns_roce_v2_priv *priv = hr_dev->priv; 2559 2560 free_link_table_buf(hr_dev, &priv->ext_llm); 2561 } 2562 2563 static void free_dip_list(struct hns_roce_dev *hr_dev) 2564 { 2565 struct hns_roce_dip *hr_dip; 2566 struct hns_roce_dip *tmp; 2567 unsigned long flags; 2568 2569 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2570 2571 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2572 list_del(&hr_dip->node); 2573 kfree(hr_dip); 2574 } 2575 2576 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2577 } 2578 2579 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2580 { 2581 struct hns_roce_v2_priv *priv = hr_dev->priv; 2582 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2583 struct ib_device *ibdev = &hr_dev->ib_dev; 2584 struct hns_roce_pd *hr_pd; 2585 struct ib_pd *pd; 2586 2587 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2588 if (ZERO_OR_NULL_PTR(hr_pd)) 2589 return NULL; 2590 pd = &hr_pd->ibpd; 2591 pd->device = ibdev; 2592 2593 if (hns_roce_alloc_pd(pd, NULL)) { 2594 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2595 kfree(hr_pd); 2596 return NULL; 2597 } 2598 free_mr->rsv_pd = to_hr_pd(pd); 2599 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2600 free_mr->rsv_pd->ibpd.uobject = NULL; 2601 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2602 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2603 2604 return pd; 2605 } 2606 2607 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2608 { 2609 struct hns_roce_v2_priv *priv = hr_dev->priv; 2610 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2611 struct ib_device *ibdev = &hr_dev->ib_dev; 2612 struct ib_cq_init_attr cq_init_attr = {}; 2613 struct hns_roce_cq *hr_cq; 2614 struct ib_cq *cq; 2615 2616 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2617 2618 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2619 if (ZERO_OR_NULL_PTR(hr_cq)) 2620 return NULL; 2621 2622 cq = &hr_cq->ib_cq; 2623 cq->device = ibdev; 2624 2625 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2626 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2627 kfree(hr_cq); 2628 return NULL; 2629 } 2630 free_mr->rsv_cq = to_hr_cq(cq); 2631 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2632 free_mr->rsv_cq->ib_cq.uobject = NULL; 2633 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2634 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2635 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2636 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2637 2638 return cq; 2639 } 2640 2641 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2642 struct ib_qp_init_attr *init_attr, int i) 2643 { 2644 struct hns_roce_v2_priv *priv = hr_dev->priv; 2645 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2646 struct ib_device *ibdev = &hr_dev->ib_dev; 2647 struct hns_roce_qp *hr_qp; 2648 struct ib_qp *qp; 2649 int ret; 2650 2651 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2652 if (ZERO_OR_NULL_PTR(hr_qp)) 2653 return -ENOMEM; 2654 2655 qp = &hr_qp->ibqp; 2656 qp->device = ibdev; 2657 2658 ret = hns_roce_create_qp(qp, init_attr, NULL); 2659 if (ret) { 2660 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2661 kfree(hr_qp); 2662 return ret; 2663 } 2664 2665 free_mr->rsv_qp[i] = hr_qp; 2666 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2667 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2668 2669 return 0; 2670 } 2671 2672 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2673 { 2674 struct hns_roce_v2_priv *priv = hr_dev->priv; 2675 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2676 struct ib_qp *qp; 2677 int i; 2678 2679 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2680 if (free_mr->rsv_qp[i]) { 2681 qp = &free_mr->rsv_qp[i]->ibqp; 2682 hns_roce_v2_destroy_qp(qp, NULL); 2683 kfree(free_mr->rsv_qp[i]); 2684 free_mr->rsv_qp[i] = NULL; 2685 } 2686 } 2687 2688 if (free_mr->rsv_cq) { 2689 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2690 kfree(free_mr->rsv_cq); 2691 free_mr->rsv_cq = NULL; 2692 } 2693 2694 if (free_mr->rsv_pd) { 2695 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2696 kfree(free_mr->rsv_pd); 2697 free_mr->rsv_pd = NULL; 2698 } 2699 2700 mutex_destroy(&free_mr->mutex); 2701 } 2702 2703 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2704 { 2705 struct hns_roce_v2_priv *priv = hr_dev->priv; 2706 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2707 struct ib_qp_init_attr qp_init_attr = {}; 2708 struct ib_pd *pd; 2709 struct ib_cq *cq; 2710 int ret; 2711 int i; 2712 2713 pd = free_mr_init_pd(hr_dev); 2714 if (!pd) 2715 return -ENOMEM; 2716 2717 cq = free_mr_init_cq(hr_dev); 2718 if (!cq) { 2719 ret = -ENOMEM; 2720 goto create_failed_cq; 2721 } 2722 2723 qp_init_attr.qp_type = IB_QPT_RC; 2724 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2725 qp_init_attr.send_cq = cq; 2726 qp_init_attr.recv_cq = cq; 2727 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2728 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2729 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2730 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2731 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2732 2733 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2734 if (ret) 2735 goto create_failed_qp; 2736 } 2737 2738 return 0; 2739 2740 create_failed_qp: 2741 for (i--; i >= 0; i--) { 2742 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 2743 kfree(free_mr->rsv_qp[i]); 2744 } 2745 hns_roce_destroy_cq(cq, NULL); 2746 kfree(cq); 2747 2748 create_failed_cq: 2749 hns_roce_dealloc_pd(pd, NULL); 2750 kfree(pd); 2751 2752 return ret; 2753 } 2754 2755 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2756 struct ib_qp_attr *attr, int sl_num) 2757 { 2758 struct hns_roce_v2_priv *priv = hr_dev->priv; 2759 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2760 struct ib_device *ibdev = &hr_dev->ib_dev; 2761 struct hns_roce_qp *hr_qp; 2762 int loopback; 2763 int mask; 2764 int ret; 2765 2766 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2767 hr_qp->free_mr_en = 1; 2768 hr_qp->ibqp.device = ibdev; 2769 hr_qp->ibqp.qp_type = IB_QPT_RC; 2770 2771 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2772 attr->qp_state = IB_QPS_INIT; 2773 attr->port_num = 1; 2774 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2775 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2776 IB_QPS_INIT, NULL); 2777 if (ret) { 2778 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2779 ret); 2780 return ret; 2781 } 2782 2783 loopback = hr_dev->loop_idc; 2784 /* Set qpc lbi = 1 incidate loopback IO */ 2785 hr_dev->loop_idc = 1; 2786 2787 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2788 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2789 attr->qp_state = IB_QPS_RTR; 2790 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2791 attr->path_mtu = IB_MTU_256; 2792 attr->dest_qp_num = hr_qp->qpn; 2793 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2794 2795 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2796 2797 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2798 IB_QPS_RTR, NULL); 2799 hr_dev->loop_idc = loopback; 2800 if (ret) { 2801 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2802 ret); 2803 return ret; 2804 } 2805 2806 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2807 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2808 attr->qp_state = IB_QPS_RTS; 2809 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2810 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2811 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2812 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2813 IB_QPS_RTS, NULL); 2814 if (ret) 2815 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2816 ret); 2817 2818 return ret; 2819 } 2820 2821 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2822 { 2823 struct hns_roce_v2_priv *priv = hr_dev->priv; 2824 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2825 struct ib_qp_attr attr = {}; 2826 int ret; 2827 int i; 2828 2829 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2830 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2831 rdma_ah_set_port_num(&attr.ah_attr, 1); 2832 2833 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2834 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2835 if (ret) 2836 return ret; 2837 } 2838 2839 return 0; 2840 } 2841 2842 static int free_mr_init(struct hns_roce_dev *hr_dev) 2843 { 2844 struct hns_roce_v2_priv *priv = hr_dev->priv; 2845 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2846 int ret; 2847 2848 mutex_init(&free_mr->mutex); 2849 2850 ret = free_mr_alloc_res(hr_dev); 2851 if (ret) { 2852 mutex_destroy(&free_mr->mutex); 2853 return ret; 2854 } 2855 2856 ret = free_mr_modify_qp(hr_dev); 2857 if (ret) 2858 goto err_modify_qp; 2859 2860 return 0; 2861 2862 err_modify_qp: 2863 free_mr_exit(hr_dev); 2864 2865 return ret; 2866 } 2867 2868 static int get_hem_table(struct hns_roce_dev *hr_dev) 2869 { 2870 unsigned int qpc_count; 2871 unsigned int cqc_count; 2872 unsigned int gmv_count; 2873 int ret; 2874 int i; 2875 2876 /* Alloc memory for source address table buffer space chunk */ 2877 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2878 gmv_count++) { 2879 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2880 if (ret) 2881 goto err_gmv_failed; 2882 } 2883 2884 if (hr_dev->is_vf) 2885 return 0; 2886 2887 /* Alloc memory for QPC Timer buffer space chunk */ 2888 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2889 qpc_count++) { 2890 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2891 qpc_count); 2892 if (ret) { 2893 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2894 goto err_qpc_timer_failed; 2895 } 2896 } 2897 2898 /* Alloc memory for CQC Timer buffer space chunk */ 2899 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2900 cqc_count++) { 2901 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2902 cqc_count); 2903 if (ret) { 2904 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2905 goto err_cqc_timer_failed; 2906 } 2907 } 2908 2909 return 0; 2910 2911 err_cqc_timer_failed: 2912 for (i = 0; i < cqc_count; i++) 2913 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2914 2915 err_qpc_timer_failed: 2916 for (i = 0; i < qpc_count; i++) 2917 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2918 2919 err_gmv_failed: 2920 for (i = 0; i < gmv_count; i++) 2921 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2922 2923 return ret; 2924 } 2925 2926 static void put_hem_table(struct hns_roce_dev *hr_dev) 2927 { 2928 int i; 2929 2930 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2931 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2932 2933 if (hr_dev->is_vf) 2934 return; 2935 2936 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2937 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2938 2939 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2940 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2941 } 2942 2943 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2944 { 2945 int ret; 2946 2947 /* The hns ROCEE requires the extdb info to be cleared before using */ 2948 ret = hns_roce_clear_extdb_list_info(hr_dev); 2949 if (ret) 2950 return ret; 2951 2952 ret = get_hem_table(hr_dev); 2953 if (ret) 2954 return ret; 2955 2956 if (hr_dev->is_vf) 2957 return 0; 2958 2959 ret = hns_roce_init_link_table(hr_dev); 2960 if (ret) { 2961 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2962 goto err_llm_init_failed; 2963 } 2964 2965 return 0; 2966 2967 err_llm_init_failed: 2968 put_hem_table(hr_dev); 2969 2970 return ret; 2971 } 2972 2973 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2974 { 2975 hns_roce_function_clear(hr_dev); 2976 2977 if (!hr_dev->is_vf) 2978 hns_roce_free_link_table(hr_dev); 2979 2980 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2981 free_dip_list(hr_dev); 2982 } 2983 2984 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2985 struct hns_roce_mbox_msg *mbox_msg) 2986 { 2987 struct hns_roce_cmq_desc desc; 2988 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2989 2990 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2991 2992 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2993 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2994 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2995 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2996 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2997 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2998 mbox_msg->token); 2999 3000 return hns_roce_cmq_send(hr_dev, &desc, 1); 3001 } 3002 3003 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 3004 u8 *complete_status) 3005 { 3006 struct hns_roce_mbox_status *mb_st; 3007 struct hns_roce_cmq_desc desc; 3008 unsigned long end; 3009 int ret = -EBUSY; 3010 u32 status; 3011 bool busy; 3012 3013 mb_st = (struct hns_roce_mbox_status *)desc.data; 3014 end = msecs_to_jiffies(timeout) + jiffies; 3015 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 3016 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 3017 return -EIO; 3018 3019 status = 0; 3020 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3021 true); 3022 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3023 if (!ret) { 3024 status = le32_to_cpu(mb_st->mb_status_hw_run); 3025 /* No pending message exists in ROCEE mbox. */ 3026 if (!(status & MB_ST_HW_RUN_M)) 3027 break; 3028 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3029 break; 3030 } 3031 3032 if (time_after(jiffies, end)) { 3033 dev_err_ratelimited(hr_dev->dev, 3034 "failed to wait mbox status 0x%x\n", 3035 status); 3036 return -ETIMEDOUT; 3037 } 3038 3039 cond_resched(); 3040 ret = -EBUSY; 3041 } 3042 3043 if (!ret) { 3044 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3045 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3046 /* Ignore all errors if the mbox is unavailable. */ 3047 ret = 0; 3048 *complete_status = MB_ST_COMPLETE_M; 3049 } 3050 3051 return ret; 3052 } 3053 3054 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3055 struct hns_roce_mbox_msg *mbox_msg) 3056 { 3057 u8 status = 0; 3058 int ret; 3059 3060 /* Waiting for the mbox to be idle */ 3061 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3062 &status); 3063 if (unlikely(ret)) { 3064 dev_err_ratelimited(hr_dev->dev, 3065 "failed to check post mbox status = 0x%x, ret = %d.\n", 3066 status, ret); 3067 return ret; 3068 } 3069 3070 /* Post new message to mbox */ 3071 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3072 if (ret) 3073 dev_err_ratelimited(hr_dev->dev, 3074 "failed to post mailbox, ret = %d.\n", ret); 3075 3076 return ret; 3077 } 3078 3079 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3080 { 3081 u8 status = 0; 3082 int ret; 3083 3084 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3085 &status); 3086 if (!ret) { 3087 if (status != MB_ST_COMPLETE_SUCC) 3088 return -EBUSY; 3089 } else { 3090 dev_err_ratelimited(hr_dev->dev, 3091 "failed to check mbox status = 0x%x, ret = %d.\n", 3092 status, ret); 3093 } 3094 3095 return ret; 3096 } 3097 3098 static void copy_gid(void *dest, const union ib_gid *gid) 3099 { 3100 #define GID_SIZE 4 3101 const union ib_gid *src = gid; 3102 __le32 (*p)[GID_SIZE] = dest; 3103 int i; 3104 3105 if (!gid) 3106 src = &zgid; 3107 3108 for (i = 0; i < GID_SIZE; i++) 3109 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3110 } 3111 3112 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3113 int gid_index, const union ib_gid *gid, 3114 enum hns_roce_sgid_type sgid_type) 3115 { 3116 struct hns_roce_cmq_desc desc; 3117 struct hns_roce_cfg_sgid_tb *sgid_tb = 3118 (struct hns_roce_cfg_sgid_tb *)desc.data; 3119 3120 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3121 3122 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3123 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3124 3125 copy_gid(&sgid_tb->vf_sgid_l, gid); 3126 3127 return hns_roce_cmq_send(hr_dev, &desc, 1); 3128 } 3129 3130 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3131 int gid_index, const union ib_gid *gid, 3132 enum hns_roce_sgid_type sgid_type, 3133 const struct ib_gid_attr *attr) 3134 { 3135 struct hns_roce_cmq_desc desc[2]; 3136 struct hns_roce_cfg_gmv_tb_a *tb_a = 3137 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3138 struct hns_roce_cfg_gmv_tb_b *tb_b = 3139 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3140 3141 u16 vlan_id = VLAN_CFI_MASK; 3142 u8 mac[ETH_ALEN] = {}; 3143 int ret; 3144 3145 if (gid) { 3146 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3147 if (ret) 3148 return ret; 3149 } 3150 3151 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3152 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3153 3154 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3155 3156 copy_gid(&tb_a->vf_sgid_l, gid); 3157 3158 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3159 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3160 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3161 3162 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3163 3164 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3165 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3166 3167 return hns_roce_cmq_send(hr_dev, desc, 2); 3168 } 3169 3170 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3171 const union ib_gid *gid, 3172 const struct ib_gid_attr *attr) 3173 { 3174 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3175 int ret; 3176 3177 if (gid) { 3178 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3179 if (ipv6_addr_v4mapped((void *)gid)) 3180 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3181 else 3182 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3183 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3184 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3185 } 3186 } 3187 3188 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3189 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3190 else 3191 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3192 3193 if (ret) 3194 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3195 ret); 3196 3197 return ret; 3198 } 3199 3200 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3201 const u8 *addr) 3202 { 3203 struct hns_roce_cmq_desc desc; 3204 struct hns_roce_cfg_smac_tb *smac_tb = 3205 (struct hns_roce_cfg_smac_tb *)desc.data; 3206 u16 reg_smac_h; 3207 u32 reg_smac_l; 3208 3209 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3210 3211 reg_smac_l = *(u32 *)(&addr[0]); 3212 reg_smac_h = *(u16 *)(&addr[4]); 3213 3214 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3215 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3216 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3217 3218 return hns_roce_cmq_send(hr_dev, &desc, 1); 3219 } 3220 3221 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3222 struct hns_roce_v2_mpt_entry *mpt_entry, 3223 struct hns_roce_mr *mr) 3224 { 3225 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3226 struct ib_device *ibdev = &hr_dev->ib_dev; 3227 dma_addr_t pbl_ba; 3228 int ret; 3229 int i; 3230 3231 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3232 min_t(int, ARRAY_SIZE(pages), mr->npages)); 3233 if (ret) { 3234 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret); 3235 return ret; 3236 } 3237 3238 /* Aligned to the hardware address access unit */ 3239 for (i = 0; i < ARRAY_SIZE(pages); i++) 3240 pages[i] >>= MPT_PBL_BUF_ADDR_S; 3241 3242 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3243 3244 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3245 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S); 3246 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3247 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3248 3249 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3250 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3251 3252 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3253 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3254 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3255 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3256 3257 return 0; 3258 } 3259 3260 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3261 void *mb_buf, struct hns_roce_mr *mr) 3262 { 3263 struct hns_roce_v2_mpt_entry *mpt_entry; 3264 3265 mpt_entry = mb_buf; 3266 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3267 3268 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3269 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3270 3271 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3272 mr->access & IB_ACCESS_MW_BIND); 3273 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3274 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3275 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3276 mr->access & IB_ACCESS_REMOTE_READ); 3277 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3278 mr->access & IB_ACCESS_REMOTE_WRITE); 3279 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3280 mr->access & IB_ACCESS_LOCAL_WRITE); 3281 3282 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3283 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3284 mpt_entry->lkey = cpu_to_le32(mr->key); 3285 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3286 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3287 3288 if (mr->type != MR_TYPE_MR) 3289 hr_reg_enable(mpt_entry, MPT_PA); 3290 3291 if (mr->type == MR_TYPE_DMA) 3292 return 0; 3293 3294 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3295 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3296 3297 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3298 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3299 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3300 3301 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3302 } 3303 3304 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3305 struct hns_roce_mr *mr, int flags, 3306 void *mb_buf) 3307 { 3308 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3309 u32 mr_access_flags = mr->access; 3310 int ret = 0; 3311 3312 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3313 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3314 3315 if (flags & IB_MR_REREG_ACCESS) { 3316 hr_reg_write(mpt_entry, MPT_BIND_EN, 3317 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3318 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3319 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3320 hr_reg_write(mpt_entry, MPT_RR_EN, 3321 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3322 hr_reg_write(mpt_entry, MPT_RW_EN, 3323 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3324 hr_reg_write(mpt_entry, MPT_LW_EN, 3325 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3326 } 3327 3328 if (flags & IB_MR_REREG_TRANS) { 3329 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3330 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3331 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3332 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3333 3334 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3335 } 3336 3337 return ret; 3338 } 3339 3340 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) 3341 { 3342 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3343 struct hns_roce_v2_mpt_entry *mpt_entry; 3344 3345 mpt_entry = mb_buf; 3346 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3347 3348 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3349 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3350 3351 hr_reg_enable(mpt_entry, MPT_RA_EN); 3352 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3353 3354 hr_reg_enable(mpt_entry, MPT_FRE); 3355 hr_reg_clear(mpt_entry, MPT_MR_MW); 3356 hr_reg_enable(mpt_entry, MPT_BPD); 3357 hr_reg_clear(mpt_entry, MPT_PA); 3358 3359 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3360 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3361 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3362 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3363 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3364 3365 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3366 3367 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3368 MPT_PBL_BA_ADDR_S)); 3369 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3370 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3371 3372 return 0; 3373 } 3374 3375 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3376 { 3377 struct hns_roce_v2_mpt_entry *mpt_entry; 3378 3379 mpt_entry = mb_buf; 3380 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3381 3382 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3383 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3384 3385 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3386 hr_reg_enable(mpt_entry, MPT_LW_EN); 3387 3388 hr_reg_enable(mpt_entry, MPT_MR_MW); 3389 hr_reg_enable(mpt_entry, MPT_BPD); 3390 hr_reg_clear(mpt_entry, MPT_PA); 3391 hr_reg_write(mpt_entry, MPT_BQP, 3392 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3393 3394 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3395 3396 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3397 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3398 mw->pbl_hop_num); 3399 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3400 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3401 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3402 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3403 3404 return 0; 3405 } 3406 3407 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3408 { 3409 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3410 struct ib_device *ibdev = &hr_dev->ib_dev; 3411 const struct ib_send_wr *bad_wr; 3412 struct ib_rdma_wr rdma_wr = {}; 3413 struct ib_send_wr *send_wr; 3414 int ret; 3415 3416 send_wr = &rdma_wr.wr; 3417 send_wr->opcode = IB_WR_RDMA_WRITE; 3418 3419 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3420 if (ret) { 3421 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3422 ret); 3423 return ret; 3424 } 3425 3426 return 0; 3427 } 3428 3429 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3430 struct ib_wc *wc); 3431 3432 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3433 { 3434 struct hns_roce_v2_priv *priv = hr_dev->priv; 3435 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3436 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3437 struct ib_device *ibdev = &hr_dev->ib_dev; 3438 struct hns_roce_qp *hr_qp; 3439 unsigned long end; 3440 int cqe_cnt = 0; 3441 int npolled; 3442 int ret; 3443 int i; 3444 3445 /* 3446 * If the device initialization is not complete or in the uninstall 3447 * process, then there is no need to execute free mr. 3448 */ 3449 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3450 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3451 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3452 return; 3453 3454 mutex_lock(&free_mr->mutex); 3455 3456 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3457 hr_qp = free_mr->rsv_qp[i]; 3458 3459 ret = free_mr_post_send_lp_wqe(hr_qp); 3460 if (ret) { 3461 ibdev_err(ibdev, 3462 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3463 hr_qp->qpn, ret); 3464 break; 3465 } 3466 3467 cqe_cnt++; 3468 } 3469 3470 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3471 while (cqe_cnt) { 3472 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3473 if (npolled < 0) { 3474 ibdev_err(ibdev, 3475 "failed to poll cqe for free mr, remain %d cqe.\n", 3476 cqe_cnt); 3477 goto out; 3478 } 3479 3480 if (time_after(jiffies, end)) { 3481 ibdev_err(ibdev, 3482 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3483 cqe_cnt); 3484 goto out; 3485 } 3486 cqe_cnt -= npolled; 3487 } 3488 3489 out: 3490 mutex_unlock(&free_mr->mutex); 3491 } 3492 3493 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3494 { 3495 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3496 free_mr_send_cmd_to_hw(hr_dev); 3497 } 3498 3499 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3500 { 3501 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3502 } 3503 3504 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3505 { 3506 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3507 3508 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3509 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3510 NULL; 3511 } 3512 3513 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3514 struct hns_roce_cq *hr_cq) 3515 { 3516 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3517 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3518 } else { 3519 struct hns_roce_v2_db cq_db = {}; 3520 3521 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3522 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3523 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3524 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3525 3526 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3527 } 3528 } 3529 3530 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3531 struct hns_roce_srq *srq) 3532 { 3533 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3534 struct hns_roce_v2_cqe *cqe, *dest; 3535 u32 prod_index; 3536 int nfreed = 0; 3537 int wqe_index; 3538 u8 owner_bit; 3539 3540 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3541 ++prod_index) { 3542 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3543 break; 3544 } 3545 3546 /* 3547 * Now backwards through the CQ, removing CQ entries 3548 * that match our QP by overwriting them with next entries. 3549 */ 3550 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3551 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3552 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3553 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3554 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3555 hns_roce_free_srq_wqe(srq, wqe_index); 3556 } 3557 ++nfreed; 3558 } else if (nfreed) { 3559 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3560 hr_cq->ib_cq.cqe); 3561 owner_bit = hr_reg_read(dest, CQE_OWNER); 3562 memcpy(dest, cqe, hr_cq->cqe_size); 3563 hr_reg_write(dest, CQE_OWNER, owner_bit); 3564 } 3565 } 3566 3567 if (nfreed) { 3568 hr_cq->cons_index += nfreed; 3569 update_cq_db(hr_dev, hr_cq); 3570 } 3571 } 3572 3573 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3574 struct hns_roce_srq *srq) 3575 { 3576 spin_lock_irq(&hr_cq->lock); 3577 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3578 spin_unlock_irq(&hr_cq->lock); 3579 } 3580 3581 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3582 struct hns_roce_cq *hr_cq, void *mb_buf, 3583 u64 *mtts, dma_addr_t dma_handle) 3584 { 3585 struct hns_roce_v2_cq_context *cq_context; 3586 3587 cq_context = mb_buf; 3588 memset(cq_context, 0, sizeof(*cq_context)); 3589 3590 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3591 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3592 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3593 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3594 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3595 3596 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3597 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3598 3599 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3600 hr_reg_enable(cq_context, CQC_STASH); 3601 3602 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3603 to_hr_hw_page_addr(mtts[0])); 3604 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3605 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3606 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3607 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3608 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3609 to_hr_hw_page_addr(mtts[1])); 3610 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3611 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3612 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3613 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3614 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3615 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3616 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S); 3617 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S); 3618 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3619 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3620 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3621 ((u32)hr_cq->db.dma) >> 1); 3622 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3623 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S); 3624 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3625 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3626 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3627 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3628 } 3629 3630 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3631 enum ib_cq_notify_flags flags) 3632 { 3633 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3634 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3635 struct hns_roce_v2_db cq_db = {}; 3636 u32 notify_flag; 3637 3638 /* 3639 * flags = 0, then notify_flag : next 3640 * flags = 1, then notify flag : solocited 3641 */ 3642 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3643 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3644 3645 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3646 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3647 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3648 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3649 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3650 3651 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3652 3653 return 0; 3654 } 3655 3656 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3657 int num_entries, struct ib_wc *wc) 3658 { 3659 unsigned int left; 3660 int npolled = 0; 3661 3662 left = wq->head - wq->tail; 3663 if (left == 0) 3664 return 0; 3665 3666 left = min_t(unsigned int, (unsigned int)num_entries, left); 3667 while (npolled < left) { 3668 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3669 wc->status = IB_WC_WR_FLUSH_ERR; 3670 wc->vendor_err = 0; 3671 wc->qp = &hr_qp->ibqp; 3672 3673 wq->tail++; 3674 wc++; 3675 npolled++; 3676 } 3677 3678 return npolled; 3679 } 3680 3681 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3682 struct ib_wc *wc) 3683 { 3684 struct hns_roce_qp *hr_qp; 3685 int npolled = 0; 3686 3687 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3688 npolled += sw_comp(hr_qp, &hr_qp->sq, 3689 num_entries - npolled, wc + npolled); 3690 if (npolled >= num_entries) 3691 goto out; 3692 } 3693 3694 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3695 npolled += sw_comp(hr_qp, &hr_qp->rq, 3696 num_entries - npolled, wc + npolled); 3697 if (npolled >= num_entries) 3698 goto out; 3699 } 3700 3701 out: 3702 return npolled; 3703 } 3704 3705 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3706 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3707 struct ib_wc *wc) 3708 { 3709 static const struct { 3710 u32 cqe_status; 3711 enum ib_wc_status wc_status; 3712 } map[] = { 3713 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3714 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3715 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3716 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3717 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3718 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3719 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3720 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3721 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3722 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3723 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3724 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3725 IB_WC_RETRY_EXC_ERR }, 3726 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3727 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3728 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3729 }; 3730 3731 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3732 int i; 3733 3734 wc->status = IB_WC_GENERAL_ERR; 3735 for (i = 0; i < ARRAY_SIZE(map); i++) 3736 if (cqe_status == map[i].cqe_status) { 3737 wc->status = map[i].wc_status; 3738 break; 3739 } 3740 3741 if (likely(wc->status == IB_WC_SUCCESS || 3742 wc->status == IB_WC_WR_FLUSH_ERR)) 3743 return; 3744 3745 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n", 3746 cqe_status); 3747 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3748 cq->cqe_size, false); 3749 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3750 3751 /* 3752 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3753 * the standard protocol, the driver must ignore it and needn't to set 3754 * the QP to an error state. 3755 */ 3756 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3757 return; 3758 3759 flush_cqe(hr_dev, qp); 3760 } 3761 3762 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3763 struct hns_roce_qp **cur_qp) 3764 { 3765 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3766 struct hns_roce_qp *hr_qp = *cur_qp; 3767 u32 qpn; 3768 3769 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3770 3771 if (!hr_qp || qpn != hr_qp->qpn) { 3772 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3773 if (unlikely(!hr_qp)) { 3774 ibdev_err(&hr_dev->ib_dev, 3775 "CQ %06lx with entry for unknown QPN %06x\n", 3776 hr_cq->cqn, qpn); 3777 return -EINVAL; 3778 } 3779 *cur_qp = hr_qp; 3780 } 3781 3782 return 0; 3783 } 3784 3785 /* 3786 * mapped-value = 1 + real-value 3787 * The ib wc opcode's real value is start from 0, In order to distinguish 3788 * between initialized and uninitialized map values, we plus 1 to the actual 3789 * value when defining the mapping, so that the validity can be identified by 3790 * checking whether the mapped value is greater than 0. 3791 */ 3792 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3793 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3794 3795 static const u32 wc_send_op_map[] = { 3796 HR_WC_OP_MAP(SEND, SEND), 3797 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3798 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3799 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3800 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3801 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3802 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3803 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3804 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3805 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3806 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3807 HR_WC_OP_MAP(BIND_MW, REG_MR), 3808 }; 3809 3810 static int to_ib_wc_send_op(u32 hr_opcode) 3811 { 3812 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3813 return -EINVAL; 3814 3815 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3816 -EINVAL; 3817 } 3818 3819 static const u32 wc_recv_op_map[] = { 3820 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3821 HR_WC_OP_MAP(SEND, RECV), 3822 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3823 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3824 }; 3825 3826 static int to_ib_wc_recv_op(u32 hr_opcode) 3827 { 3828 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3829 return -EINVAL; 3830 3831 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3832 -EINVAL; 3833 } 3834 3835 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3836 { 3837 u32 hr_opcode; 3838 int ib_opcode; 3839 3840 wc->wc_flags = 0; 3841 3842 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3843 switch (hr_opcode) { 3844 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3845 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3846 break; 3847 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3848 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3849 wc->wc_flags |= IB_WC_WITH_IMM; 3850 break; 3851 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3852 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3853 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3854 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3855 wc->byte_len = 8; 3856 break; 3857 default: 3858 break; 3859 } 3860 3861 ib_opcode = to_ib_wc_send_op(hr_opcode); 3862 if (ib_opcode < 0) 3863 wc->status = IB_WC_GENERAL_ERR; 3864 else 3865 wc->opcode = ib_opcode; 3866 } 3867 3868 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3869 { 3870 u32 hr_opcode; 3871 int ib_opcode; 3872 3873 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3874 3875 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3876 switch (hr_opcode) { 3877 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3878 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3879 wc->wc_flags = IB_WC_WITH_IMM; 3880 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3881 break; 3882 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3883 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3884 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3885 break; 3886 default: 3887 wc->wc_flags = 0; 3888 } 3889 3890 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3891 if (ib_opcode < 0) 3892 wc->status = IB_WC_GENERAL_ERR; 3893 else 3894 wc->opcode = ib_opcode; 3895 3896 wc->sl = hr_reg_read(cqe, CQE_SL); 3897 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3898 wc->slid = 0; 3899 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3900 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3901 wc->pkey_index = 0; 3902 3903 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3904 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3905 wc->wc_flags |= IB_WC_WITH_VLAN; 3906 } else { 3907 wc->vlan_id = 0xffff; 3908 } 3909 3910 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3911 3912 return 0; 3913 } 3914 3915 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3916 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3917 { 3918 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3919 struct hns_roce_qp *qp = *cur_qp; 3920 struct hns_roce_srq *srq = NULL; 3921 struct hns_roce_v2_cqe *cqe; 3922 struct hns_roce_wq *wq; 3923 int is_send; 3924 u16 wqe_idx; 3925 int ret; 3926 3927 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3928 if (!cqe) 3929 return -EAGAIN; 3930 3931 ++hr_cq->cons_index; 3932 /* Memory barrier */ 3933 rmb(); 3934 3935 ret = get_cur_qp(hr_cq, cqe, &qp); 3936 if (ret) 3937 return ret; 3938 3939 wc->qp = &qp->ibqp; 3940 wc->vendor_err = 0; 3941 3942 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3943 3944 is_send = !hr_reg_read(cqe, CQE_S_R); 3945 if (is_send) { 3946 wq = &qp->sq; 3947 3948 /* If sg_signal_bit is set, tail pointer will be updated to 3949 * the WQE corresponding to the current CQE. 3950 */ 3951 if (qp->sq_signal_bits) 3952 wq->tail += (wqe_idx - (u16)wq->tail) & 3953 (wq->wqe_cnt - 1); 3954 3955 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3956 ++wq->tail; 3957 3958 fill_send_wc(wc, cqe); 3959 } else { 3960 if (qp->ibqp.srq) { 3961 srq = to_hr_srq(qp->ibqp.srq); 3962 wc->wr_id = srq->wrid[wqe_idx]; 3963 hns_roce_free_srq_wqe(srq, wqe_idx); 3964 } else { 3965 wq = &qp->rq; 3966 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3967 ++wq->tail; 3968 } 3969 3970 ret = fill_recv_wc(wc, cqe); 3971 } 3972 3973 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3974 if (unlikely(wc->status != IB_WC_SUCCESS)) 3975 return 0; 3976 3977 return ret; 3978 } 3979 3980 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3981 struct ib_wc *wc) 3982 { 3983 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3984 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3985 struct hns_roce_qp *cur_qp = NULL; 3986 unsigned long flags; 3987 int npolled; 3988 3989 spin_lock_irqsave(&hr_cq->lock, flags); 3990 3991 /* 3992 * When the device starts to reset, the state is RST_DOWN. At this time, 3993 * there may still be some valid CQEs in the hardware that are not 3994 * polled. Therefore, it is not allowed to switch to the software mode 3995 * immediately. When the state changes to UNINIT, CQE no longer exists 3996 * in the hardware, and then switch to software mode. 3997 */ 3998 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3999 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 4000 goto out; 4001 } 4002 4003 for (npolled = 0; npolled < num_entries; ++npolled) { 4004 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4005 break; 4006 } 4007 4008 if (npolled) 4009 update_cq_db(hr_dev, hr_cq); 4010 4011 out: 4012 spin_unlock_irqrestore(&hr_cq->lock, flags); 4013 4014 return npolled; 4015 } 4016 4017 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4018 u32 step_idx, u8 *mbox_cmd) 4019 { 4020 u8 cmd; 4021 4022 switch (type) { 4023 case HEM_TYPE_QPC: 4024 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4025 break; 4026 case HEM_TYPE_MTPT: 4027 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4028 break; 4029 case HEM_TYPE_CQC: 4030 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4031 break; 4032 case HEM_TYPE_SRQC: 4033 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4034 break; 4035 case HEM_TYPE_SCCC: 4036 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4037 break; 4038 case HEM_TYPE_QPC_TIMER: 4039 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4040 break; 4041 case HEM_TYPE_CQC_TIMER: 4042 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4043 break; 4044 default: 4045 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4046 return -EINVAL; 4047 } 4048 4049 *mbox_cmd = cmd + step_idx; 4050 4051 return 0; 4052 } 4053 4054 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4055 dma_addr_t base_addr) 4056 { 4057 struct hns_roce_cmq_desc desc; 4058 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4059 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4060 u64 addr = to_hr_hw_page_addr(base_addr); 4061 4062 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4063 4064 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4065 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4066 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4067 4068 return hns_roce_cmq_send(hr_dev, &desc, 1); 4069 } 4070 4071 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4072 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4073 { 4074 int ret; 4075 u8 cmd; 4076 4077 if (unlikely(hem_type == HEM_TYPE_GMV)) 4078 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4079 4080 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4081 return 0; 4082 4083 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4084 if (ret < 0) 4085 return ret; 4086 4087 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4088 } 4089 4090 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4091 struct hns_roce_hem_table *table, int obj, 4092 u32 step_idx) 4093 { 4094 struct hns_roce_hem_mhop mhop; 4095 struct hns_roce_hem *hem; 4096 unsigned long mhop_obj = obj; 4097 int i, j, k; 4098 int ret = 0; 4099 u64 hem_idx = 0; 4100 u64 l1_idx = 0; 4101 u64 bt_ba = 0; 4102 u32 chunk_ba_num; 4103 u32 hop_num; 4104 4105 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4106 return 0; 4107 4108 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4109 i = mhop.l0_idx; 4110 j = mhop.l1_idx; 4111 k = mhop.l2_idx; 4112 hop_num = mhop.hop_num; 4113 chunk_ba_num = mhop.bt_chunk_size / 8; 4114 4115 if (hop_num == 2) { 4116 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4117 k; 4118 l1_idx = i * chunk_ba_num + j; 4119 } else if (hop_num == 1) { 4120 hem_idx = i * chunk_ba_num + j; 4121 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4122 hem_idx = i; 4123 } 4124 4125 if (table->type == HEM_TYPE_SCCC) 4126 obj = mhop.l0_idx; 4127 4128 if (check_whether_last_step(hop_num, step_idx)) { 4129 hem = table->hem[hem_idx]; 4130 4131 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx); 4132 } else { 4133 if (step_idx == 0) 4134 bt_ba = table->bt_l0_dma_addr[i]; 4135 else if (step_idx == 1 && hop_num == 2) 4136 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4137 4138 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4139 } 4140 4141 return ret; 4142 } 4143 4144 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4145 struct hns_roce_hem_table *table, 4146 int tag, u32 step_idx) 4147 { 4148 struct hns_roce_cmd_mailbox *mailbox; 4149 struct device *dev = hr_dev->dev; 4150 u8 cmd = 0xff; 4151 int ret; 4152 4153 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4154 return 0; 4155 4156 switch (table->type) { 4157 case HEM_TYPE_QPC: 4158 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4159 break; 4160 case HEM_TYPE_MTPT: 4161 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4162 break; 4163 case HEM_TYPE_CQC: 4164 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4165 break; 4166 case HEM_TYPE_SRQC: 4167 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4168 break; 4169 case HEM_TYPE_SCCC: 4170 case HEM_TYPE_QPC_TIMER: 4171 case HEM_TYPE_CQC_TIMER: 4172 case HEM_TYPE_GMV: 4173 return 0; 4174 default: 4175 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4176 table->type); 4177 return 0; 4178 } 4179 4180 cmd += step_idx; 4181 4182 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4183 if (IS_ERR(mailbox)) 4184 return PTR_ERR(mailbox); 4185 4186 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4187 4188 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4189 return ret; 4190 } 4191 4192 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4193 struct hns_roce_v2_qp_context *context, 4194 struct hns_roce_v2_qp_context *qpc_mask, 4195 struct hns_roce_qp *hr_qp) 4196 { 4197 struct hns_roce_cmd_mailbox *mailbox; 4198 int qpc_size; 4199 int ret; 4200 4201 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4202 if (IS_ERR(mailbox)) 4203 return PTR_ERR(mailbox); 4204 4205 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4206 qpc_size = hr_dev->caps.qpc_sz; 4207 memcpy(mailbox->buf, context, qpc_size); 4208 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4209 4210 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4211 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4212 4213 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4214 4215 return ret; 4216 } 4217 4218 static void set_access_flags(struct hns_roce_qp *hr_qp, 4219 struct hns_roce_v2_qp_context *context, 4220 struct hns_roce_v2_qp_context *qpc_mask, 4221 const struct ib_qp_attr *attr, int attr_mask) 4222 { 4223 u8 dest_rd_atomic; 4224 u32 access_flags; 4225 4226 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4227 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4228 4229 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4230 attr->qp_access_flags : hr_qp->atomic_rd_en; 4231 4232 if (!dest_rd_atomic) 4233 access_flags &= IB_ACCESS_REMOTE_WRITE; 4234 4235 hr_reg_write_bool(context, QPC_RRE, 4236 access_flags & IB_ACCESS_REMOTE_READ); 4237 hr_reg_clear(qpc_mask, QPC_RRE); 4238 4239 hr_reg_write_bool(context, QPC_RWE, 4240 access_flags & IB_ACCESS_REMOTE_WRITE); 4241 hr_reg_clear(qpc_mask, QPC_RWE); 4242 4243 hr_reg_write_bool(context, QPC_ATE, 4244 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4245 hr_reg_clear(qpc_mask, QPC_ATE); 4246 hr_reg_write_bool(context, QPC_EXT_ATE, 4247 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4248 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4249 } 4250 4251 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4252 struct hns_roce_v2_qp_context *context) 4253 { 4254 hr_reg_write(context, QPC_SGE_SHIFT, 4255 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4256 hr_qp->sge.sge_shift)); 4257 4258 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4259 4260 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4261 } 4262 4263 static inline int get_cqn(struct ib_cq *ib_cq) 4264 { 4265 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4266 } 4267 4268 static inline int get_pdn(struct ib_pd *ib_pd) 4269 { 4270 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4271 } 4272 4273 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4274 struct hns_roce_v2_qp_context *context, 4275 struct hns_roce_v2_qp_context *qpc_mask) 4276 { 4277 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4278 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4279 4280 /* 4281 * In v2 engine, software pass context and context mask to hardware 4282 * when modifying qp. If software need modify some fields in context, 4283 * we should set all bits of the relevant fields in context mask to 4284 * 0 at the same time, else set them to 0x1. 4285 */ 4286 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4287 4288 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4289 4290 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4291 4292 set_qpc_wqe_cnt(hr_qp, context); 4293 4294 /* No VLAN need to set 0xFFF */ 4295 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4296 4297 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4298 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4299 4300 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4301 } 4302 4303 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4304 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4305 4306 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4307 hr_reg_enable(context, QPC_OWNER_MODE); 4308 4309 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4310 lower_32_bits(hr_qp->rdb.dma) >> 1); 4311 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4312 upper_32_bits(hr_qp->rdb.dma)); 4313 4314 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4315 4316 if (ibqp->srq) { 4317 hr_reg_enable(context, QPC_SRQ_EN); 4318 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4319 } 4320 4321 hr_reg_enable(context, QPC_FRE); 4322 4323 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4324 4325 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4326 return; 4327 4328 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4329 hr_reg_enable(&context->ext, QPCEX_STASH); 4330 } 4331 4332 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4333 struct hns_roce_v2_qp_context *context, 4334 struct hns_roce_v2_qp_context *qpc_mask) 4335 { 4336 /* 4337 * In v2 engine, software pass context and context mask to hardware 4338 * when modifying qp. If software need modify some fields in context, 4339 * we should set all bits of the relevant fields in context mask to 4340 * 0 at the same time, else set them to 0x1. 4341 */ 4342 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4343 hr_reg_clear(qpc_mask, QPC_TST); 4344 4345 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4346 hr_reg_clear(qpc_mask, QPC_PD); 4347 4348 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4349 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4350 4351 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4352 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4353 4354 if (ibqp->srq) { 4355 hr_reg_enable(context, QPC_SRQ_EN); 4356 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4357 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4358 hr_reg_clear(qpc_mask, QPC_SRQN); 4359 } 4360 } 4361 4362 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4363 struct hns_roce_qp *hr_qp, 4364 struct hns_roce_v2_qp_context *context, 4365 struct hns_roce_v2_qp_context *qpc_mask) 4366 { 4367 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4368 u64 wqe_sge_ba; 4369 int ret; 4370 4371 /* Search qp buf's mtts */ 4372 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4373 MTT_MIN_COUNT); 4374 if (hr_qp->rq.wqe_cnt && ret) { 4375 ibdev_err(&hr_dev->ib_dev, 4376 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n", 4377 hr_qp->qpn, ret); 4378 return ret; 4379 } 4380 4381 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); 4382 4383 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4384 qpc_mask->wqe_sge_ba = 0; 4385 4386 /* 4387 * In v2 engine, software pass context and context mask to hardware 4388 * when modifying qp. If software need modify some fields in context, 4389 * we should set all bits of the relevant fields in context mask to 4390 * 0 at the same time, else set them to 0x1. 4391 */ 4392 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4393 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4394 4395 hr_reg_write(context, QPC_SQ_HOP_NUM, 4396 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4397 hr_qp->sq.wqe_cnt)); 4398 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4399 4400 hr_reg_write(context, QPC_SGE_HOP_NUM, 4401 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4402 hr_qp->sge.sge_cnt)); 4403 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4404 4405 hr_reg_write(context, QPC_RQ_HOP_NUM, 4406 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4407 hr_qp->rq.wqe_cnt)); 4408 4409 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4410 4411 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4412 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4413 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4414 4415 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4416 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4417 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4418 4419 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4420 qpc_mask->rq_cur_blk_addr = 0; 4421 4422 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4423 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4424 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4425 4426 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4427 qpc_mask->rq_nxt_blk_addr = 0; 4428 4429 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4430 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4431 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4432 4433 return 0; 4434 } 4435 4436 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4437 struct hns_roce_qp *hr_qp, 4438 struct hns_roce_v2_qp_context *context, 4439 struct hns_roce_v2_qp_context *qpc_mask) 4440 { 4441 struct ib_device *ibdev = &hr_dev->ib_dev; 4442 u64 sge_cur_blk = 0; 4443 u64 sq_cur_blk = 0; 4444 int ret; 4445 4446 /* search qp buf's mtts */ 4447 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, 4448 &sq_cur_blk, 1); 4449 if (ret) { 4450 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n", 4451 hr_qp->qpn, ret); 4452 return ret; 4453 } 4454 if (hr_qp->sge.sge_cnt > 0) { 4455 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4456 hr_qp->sge.offset, &sge_cur_blk, 1); 4457 if (ret) { 4458 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n", 4459 hr_qp->qpn, ret); 4460 return ret; 4461 } 4462 } 4463 4464 /* 4465 * In v2 engine, software pass context and context mask to hardware 4466 * when modifying qp. If software need modify some fields in context, 4467 * we should set all bits of the relevant fields in context mask to 4468 * 0 at the same time, else set them to 0x1. 4469 */ 4470 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4471 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4472 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4473 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4474 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4475 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4476 4477 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4478 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4479 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4480 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4481 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4482 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4483 4484 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4485 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4486 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4487 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4488 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4489 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4490 4491 return 0; 4492 } 4493 4494 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4495 const struct ib_qp_attr *attr) 4496 { 4497 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4498 return IB_MTU_4096; 4499 4500 return attr->path_mtu; 4501 } 4502 4503 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4504 const struct ib_qp_attr *attr, int attr_mask, 4505 struct hns_roce_v2_qp_context *context, 4506 struct hns_roce_v2_qp_context *qpc_mask, 4507 struct ib_udata *udata) 4508 { 4509 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4510 struct hns_roce_ucontext, ibucontext); 4511 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4512 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4513 struct ib_device *ibdev = &hr_dev->ib_dev; 4514 dma_addr_t trrl_ba; 4515 dma_addr_t irrl_ba; 4516 enum ib_mtu ib_mtu; 4517 const u8 *smac; 4518 u8 lp_pktn_ini; 4519 u64 *mtts; 4520 u8 *dmac; 4521 u32 port; 4522 int mtu; 4523 int ret; 4524 4525 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4526 if (ret) { 4527 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4528 return ret; 4529 } 4530 4531 /* Search IRRL's mtts */ 4532 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4533 hr_qp->qpn, &irrl_ba); 4534 if (!mtts) { 4535 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4536 return -EINVAL; 4537 } 4538 4539 /* Search TRRL's mtts */ 4540 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4541 hr_qp->qpn, &trrl_ba); 4542 if (!mtts) { 4543 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4544 return -EINVAL; 4545 } 4546 4547 if (attr_mask & IB_QP_ALT_PATH) { 4548 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4549 attr_mask); 4550 return -EINVAL; 4551 } 4552 4553 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S); 4554 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4555 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S); 4556 qpc_mask->trrl_ba = 0; 4557 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S); 4558 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4559 4560 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S); 4561 qpc_mask->irrl_ba = 0; 4562 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S); 4563 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4564 4565 hr_reg_enable(context, QPC_RMT_E2E); 4566 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4567 4568 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4569 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4570 4571 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4572 4573 smac = (const u8 *)hr_dev->dev_addr[port]; 4574 dmac = (u8 *)attr->ah_attr.roce.dmac; 4575 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4576 if (ether_addr_equal_unaligned(dmac, smac) || 4577 hr_dev->loop_idc == 0x1) { 4578 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4579 hr_reg_clear(qpc_mask, QPC_LBI); 4580 } 4581 4582 if (attr_mask & IB_QP_DEST_QPN) { 4583 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4584 hr_reg_clear(qpc_mask, QPC_DQPN); 4585 } 4586 4587 memcpy(&context->dmac, dmac, sizeof(u32)); 4588 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4589 qpc_mask->dmac = 0; 4590 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4591 4592 ib_mtu = get_mtu(ibqp, attr); 4593 hr_qp->path_mtu = ib_mtu; 4594 4595 mtu = ib_mtu_enum_to_int(ib_mtu); 4596 if (WARN_ON(mtu <= 0)) 4597 return -EINVAL; 4598 #define MIN_LP_MSG_LEN 1024 4599 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4600 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4601 4602 if (attr_mask & IB_QP_PATH_MTU) { 4603 hr_reg_write(context, QPC_MTU, ib_mtu); 4604 hr_reg_clear(qpc_mask, QPC_MTU); 4605 } 4606 4607 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4608 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4609 4610 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4611 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4612 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4613 4614 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4615 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4616 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4617 4618 context->rq_rnr_timer = 0; 4619 qpc_mask->rq_rnr_timer = 0; 4620 4621 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4622 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4623 4624 #define MAX_LP_SGEN 3 4625 /* rocee send 2^lp_sgen_ini segs every time */ 4626 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN); 4627 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4628 4629 if (udata && ibqp->qp_type == IB_QPT_RC && 4630 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4631 hr_reg_write_bool(context, QPC_RQIE, 4632 hr_dev->caps.flags & 4633 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4634 hr_reg_clear(qpc_mask, QPC_RQIE); 4635 } 4636 4637 if (udata && 4638 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4639 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4640 hr_reg_write_bool(context, QPC_CQEIE, 4641 hr_dev->caps.flags & 4642 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4643 hr_reg_clear(qpc_mask, QPC_CQEIE); 4644 4645 hr_reg_write(context, QPC_CQEIS, 0); 4646 hr_reg_clear(qpc_mask, QPC_CQEIS); 4647 } 4648 4649 return 0; 4650 } 4651 4652 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask, 4653 struct hns_roce_v2_qp_context *context, 4654 struct hns_roce_v2_qp_context *qpc_mask) 4655 { 4656 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4657 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4658 struct ib_device *ibdev = &hr_dev->ib_dev; 4659 int ret; 4660 4661 /* Not support alternate path and path migration */ 4662 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4663 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4664 return -EINVAL; 4665 } 4666 4667 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4668 if (ret) { 4669 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4670 return ret; 4671 } 4672 4673 /* 4674 * Set some fields in context to zero, Because the default values 4675 * of all fields in context are zero, we need not set them to 0 again. 4676 * but we should set the relevant fields of context mask to 0. 4677 */ 4678 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4679 4680 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4681 4682 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4683 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4684 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4685 4686 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4687 4688 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4689 4690 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4691 4692 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4693 4694 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4695 4696 return 0; 4697 } 4698 4699 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4700 u32 *dip_idx) 4701 { 4702 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4703 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4704 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4705 u32 *head = &hr_dev->qp_table.idx_table.head; 4706 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4707 struct hns_roce_dip *hr_dip; 4708 unsigned long flags; 4709 int ret = 0; 4710 4711 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4712 4713 spare_idx[*tail] = ibqp->qp_num; 4714 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4715 4716 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4717 if (!memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) { 4718 *dip_idx = hr_dip->dip_idx; 4719 goto out; 4720 } 4721 } 4722 4723 /* If no dgid is found, a new dip and a mapping between dgid and 4724 * dip_idx will be created. 4725 */ 4726 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4727 if (!hr_dip) { 4728 ret = -ENOMEM; 4729 goto out; 4730 } 4731 4732 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4733 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4734 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4735 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4736 4737 out: 4738 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4739 return ret; 4740 } 4741 4742 enum { 4743 CONG_DCQCN, 4744 CONG_WINDOW, 4745 }; 4746 4747 enum { 4748 UNSUPPORT_CONG_LEVEL, 4749 SUPPORT_CONG_LEVEL, 4750 }; 4751 4752 enum { 4753 CONG_LDCP, 4754 CONG_HC3, 4755 }; 4756 4757 enum { 4758 DIP_INVALID, 4759 DIP_VALID, 4760 }; 4761 4762 enum { 4763 WND_LIMIT, 4764 WND_UNLIMIT, 4765 }; 4766 4767 static int check_cong_type(struct ib_qp *ibqp, 4768 struct hns_roce_congestion_algorithm *cong_alg) 4769 { 4770 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4771 4772 /* different congestion types match different configurations */ 4773 switch (hr_qp->cong_type) { 4774 case CONG_TYPE_DCQCN: 4775 cong_alg->alg_sel = CONG_DCQCN; 4776 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4777 cong_alg->dip_vld = DIP_INVALID; 4778 cong_alg->wnd_mode_sel = WND_LIMIT; 4779 break; 4780 case CONG_TYPE_LDCP: 4781 cong_alg->alg_sel = CONG_WINDOW; 4782 cong_alg->alg_sub_sel = CONG_LDCP; 4783 cong_alg->dip_vld = DIP_INVALID; 4784 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4785 break; 4786 case CONG_TYPE_HC3: 4787 cong_alg->alg_sel = CONG_WINDOW; 4788 cong_alg->alg_sub_sel = CONG_HC3; 4789 cong_alg->dip_vld = DIP_INVALID; 4790 cong_alg->wnd_mode_sel = WND_LIMIT; 4791 break; 4792 case CONG_TYPE_DIP: 4793 cong_alg->alg_sel = CONG_DCQCN; 4794 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4795 cong_alg->dip_vld = DIP_VALID; 4796 cong_alg->wnd_mode_sel = WND_LIMIT; 4797 break; 4798 default: 4799 hr_qp->cong_type = CONG_TYPE_DCQCN; 4800 cong_alg->alg_sel = CONG_DCQCN; 4801 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4802 cong_alg->dip_vld = DIP_INVALID; 4803 cong_alg->wnd_mode_sel = WND_LIMIT; 4804 break; 4805 } 4806 4807 return 0; 4808 } 4809 4810 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4811 struct hns_roce_v2_qp_context *context, 4812 struct hns_roce_v2_qp_context *qpc_mask) 4813 { 4814 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4815 struct hns_roce_congestion_algorithm cong_field; 4816 struct ib_device *ibdev = ibqp->device; 4817 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4818 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4819 u32 dip_idx = 0; 4820 int ret; 4821 4822 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4823 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4824 return 0; 4825 4826 ret = check_cong_type(ibqp, &cong_field); 4827 if (ret) 4828 return ret; 4829 4830 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4831 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 4832 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4833 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4834 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4835 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4836 cong_field.alg_sub_sel); 4837 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4838 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4839 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4840 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4841 cong_field.wnd_mode_sel); 4842 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4843 4844 /* if dip is disabled, there is no need to set dip idx */ 4845 if (cong_field.dip_vld == 0) 4846 return 0; 4847 4848 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4849 if (ret) { 4850 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4851 return ret; 4852 } 4853 4854 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4855 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4856 4857 return 0; 4858 } 4859 4860 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp, 4861 u8 *tc_mode, u8 *priority) 4862 { 4863 struct hns_roce_v2_priv *priv = hr_dev->priv; 4864 struct hnae3_handle *handle = priv->handle; 4865 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 4866 4867 if (!ops->get_dscp_prio) 4868 return -EOPNOTSUPP; 4869 4870 return ops->get_dscp_prio(handle, dscp, tc_mode, priority); 4871 } 4872 4873 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl) 4874 { 4875 u32 max_sl; 4876 4877 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4878 if (unlikely(sl > max_sl)) { 4879 ibdev_err_ratelimited(&hr_dev->ib_dev, 4880 "failed to set SL(%u). Shouldn't be larger than %u.\n", 4881 sl, max_sl); 4882 return false; 4883 } 4884 4885 return true; 4886 } 4887 4888 static int hns_roce_set_sl(struct ib_qp *ibqp, 4889 const struct ib_qp_attr *attr, 4890 struct hns_roce_v2_qp_context *context, 4891 struct hns_roce_v2_qp_context *qpc_mask) 4892 { 4893 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4894 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4895 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4896 struct ib_device *ibdev = &hr_dev->ib_dev; 4897 int ret; 4898 4899 ret = hns_roce_hw_v2_get_dscp(hr_dev, get_tclass(&attr->ah_attr.grh), 4900 &hr_qp->tc_mode, &hr_qp->priority); 4901 if (ret && ret != -EOPNOTSUPP && 4902 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 4903 ibdev_err_ratelimited(ibdev, 4904 "failed to get dscp, ret = %d.\n", ret); 4905 return ret; 4906 } 4907 4908 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP && 4909 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 4910 hr_qp->sl = hr_qp->priority; 4911 else 4912 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4913 4914 if (!check_sl_valid(hr_dev, hr_qp->sl)) 4915 return -EINVAL; 4916 4917 hr_reg_write(context, QPC_SL, hr_qp->sl); 4918 hr_reg_clear(qpc_mask, QPC_SL); 4919 4920 return 0; 4921 } 4922 4923 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4924 const struct ib_qp_attr *attr, 4925 int attr_mask, 4926 struct hns_roce_v2_qp_context *context, 4927 struct hns_roce_v2_qp_context *qpc_mask) 4928 { 4929 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4930 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4931 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4932 struct ib_device *ibdev = &hr_dev->ib_dev; 4933 const struct ib_gid_attr *gid_attr = NULL; 4934 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 4935 int is_roce_protocol; 4936 u16 vlan_id = 0xffff; 4937 bool is_udp = false; 4938 u8 ib_port; 4939 u8 hr_port; 4940 int ret; 4941 4942 /* 4943 * If free_mr_en of qp is set, it means that this qp comes from 4944 * free mr. This qp will perform the loopback operation. 4945 * In the loopback scenario, only sl needs to be set. 4946 */ 4947 if (hr_qp->free_mr_en) { 4948 if (!check_sl_valid(hr_dev, sl)) 4949 return -EINVAL; 4950 hr_reg_write(context, QPC_SL, sl); 4951 hr_reg_clear(qpc_mask, QPC_SL); 4952 hr_qp->sl = sl; 4953 return 0; 4954 } 4955 4956 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4957 hr_port = ib_port - 1; 4958 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4959 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4960 4961 if (is_roce_protocol) { 4962 gid_attr = attr->ah_attr.grh.sgid_attr; 4963 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4964 if (ret) 4965 return ret; 4966 4967 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4968 } 4969 4970 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4971 if (vlan_id < VLAN_N_VID && 4972 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4973 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4974 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4975 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4976 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4977 } 4978 4979 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4980 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4981 4982 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4983 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4984 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4985 return -EINVAL; 4986 } 4987 4988 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4989 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4990 return -EINVAL; 4991 } 4992 4993 hr_reg_write(context, QPC_UDPSPN, 4994 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4995 attr->dest_qp_num) : 4996 0); 4997 4998 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4999 5000 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 5001 5002 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 5003 5004 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 5005 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 5006 5007 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 5008 if (ret) 5009 return ret; 5010 5011 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 5012 hr_reg_clear(qpc_mask, QPC_TC); 5013 5014 hr_reg_write(context, QPC_FL, grh->flow_label); 5015 hr_reg_clear(qpc_mask, QPC_FL); 5016 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5017 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 5018 5019 return hns_roce_set_sl(ibqp, attr, context, qpc_mask); 5020 } 5021 5022 static bool check_qp_state(enum ib_qp_state cur_state, 5023 enum ib_qp_state new_state) 5024 { 5025 static const bool sm[][IB_QPS_ERR + 1] = { 5026 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 5027 [IB_QPS_INIT] = true }, 5028 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 5029 [IB_QPS_INIT] = true, 5030 [IB_QPS_RTR] = true, 5031 [IB_QPS_ERR] = true }, 5032 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 5033 [IB_QPS_RTS] = true, 5034 [IB_QPS_ERR] = true }, 5035 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 5036 [IB_QPS_RTS] = true, 5037 [IB_QPS_ERR] = true }, 5038 [IB_QPS_SQD] = {}, 5039 [IB_QPS_SQE] = {}, 5040 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 5041 [IB_QPS_ERR] = true } 5042 }; 5043 5044 return sm[cur_state][new_state]; 5045 } 5046 5047 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 5048 const struct ib_qp_attr *attr, 5049 int attr_mask, 5050 enum ib_qp_state cur_state, 5051 enum ib_qp_state new_state, 5052 struct hns_roce_v2_qp_context *context, 5053 struct hns_roce_v2_qp_context *qpc_mask, 5054 struct ib_udata *udata) 5055 { 5056 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5057 int ret = 0; 5058 5059 if (!check_qp_state(cur_state, new_state)) { 5060 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 5061 return -EINVAL; 5062 } 5063 5064 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5065 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5066 modify_qp_reset_to_init(ibqp, context, qpc_mask); 5067 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5068 modify_qp_init_to_init(ibqp, context, qpc_mask); 5069 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5070 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5071 qpc_mask, udata); 5072 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5073 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask); 5074 } 5075 5076 return ret; 5077 } 5078 5079 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5080 { 5081 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5082 #define QP_ACK_TIMEOUT_MAX 31 5083 5084 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5085 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5086 ibdev_warn(&hr_dev->ib_dev, 5087 "local ACK timeout shall be 0 to 20.\n"); 5088 return false; 5089 } 5090 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5091 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5092 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5093 ibdev_warn(&hr_dev->ib_dev, 5094 "local ACK timeout shall be 0 to 31.\n"); 5095 return false; 5096 } 5097 } 5098 5099 return true; 5100 } 5101 5102 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5103 const struct ib_qp_attr *attr, 5104 int attr_mask, 5105 struct hns_roce_v2_qp_context *context, 5106 struct hns_roce_v2_qp_context *qpc_mask) 5107 { 5108 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5109 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5110 int ret = 0; 5111 u8 timeout; 5112 5113 if (attr_mask & IB_QP_AV) { 5114 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5115 qpc_mask); 5116 if (ret) 5117 return ret; 5118 } 5119 5120 if (attr_mask & IB_QP_TIMEOUT) { 5121 timeout = attr->timeout; 5122 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5123 hr_reg_write(context, QPC_AT, timeout); 5124 hr_reg_clear(qpc_mask, QPC_AT); 5125 } 5126 } 5127 5128 if (attr_mask & IB_QP_RETRY_CNT) { 5129 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5130 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5131 5132 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5133 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5134 } 5135 5136 if (attr_mask & IB_QP_RNR_RETRY) { 5137 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5138 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5139 5140 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5141 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5142 } 5143 5144 if (attr_mask & IB_QP_SQ_PSN) { 5145 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5146 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5147 5148 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5149 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5150 5151 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5152 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5153 5154 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5155 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5156 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5157 5158 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5159 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5160 5161 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5162 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5163 } 5164 5165 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5166 attr->max_dest_rd_atomic) { 5167 hr_reg_write(context, QPC_RR_MAX, 5168 fls(attr->max_dest_rd_atomic - 1)); 5169 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5170 } 5171 5172 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5173 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5174 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5175 } 5176 5177 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5178 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5179 5180 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5181 hr_reg_write(context, QPC_MIN_RNR_TIME, 5182 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5183 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5184 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5185 } 5186 5187 if (attr_mask & IB_QP_RQ_PSN) { 5188 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5189 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5190 5191 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5192 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5193 } 5194 5195 if (attr_mask & IB_QP_QKEY) { 5196 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5197 qpc_mask->qkey_xrcd = 0; 5198 hr_qp->qkey = attr->qkey; 5199 } 5200 5201 return ret; 5202 } 5203 5204 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5205 const struct ib_qp_attr *attr, 5206 int attr_mask) 5207 { 5208 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5209 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5210 5211 if (attr_mask & IB_QP_ACCESS_FLAGS) 5212 hr_qp->atomic_rd_en = attr->qp_access_flags; 5213 5214 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5215 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5216 if (attr_mask & IB_QP_PORT) { 5217 hr_qp->port = attr->port_num - 1; 5218 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5219 } 5220 } 5221 5222 static void clear_qp(struct hns_roce_qp *hr_qp) 5223 { 5224 struct ib_qp *ibqp = &hr_qp->ibqp; 5225 5226 if (ibqp->send_cq) 5227 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5228 hr_qp->qpn, NULL); 5229 5230 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5231 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5232 hr_qp->qpn, ibqp->srq ? 5233 to_hr_srq(ibqp->srq) : NULL); 5234 5235 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5236 *hr_qp->rdb.db_record = 0; 5237 5238 hr_qp->rq.head = 0; 5239 hr_qp->rq.tail = 0; 5240 hr_qp->sq.head = 0; 5241 hr_qp->sq.tail = 0; 5242 hr_qp->next_sge = 0; 5243 } 5244 5245 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5246 struct hns_roce_v2_qp_context *context, 5247 struct hns_roce_v2_qp_context *qpc_mask) 5248 { 5249 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5250 unsigned long sq_flag = 0; 5251 unsigned long rq_flag = 0; 5252 5253 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5254 return; 5255 5256 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5257 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5258 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5259 hr_qp->state = IB_QPS_ERR; 5260 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5261 5262 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5263 return; 5264 5265 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5266 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5267 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5268 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5269 } 5270 5271 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5272 const struct ib_qp_attr *attr, 5273 int attr_mask, enum ib_qp_state cur_state, 5274 enum ib_qp_state new_state, struct ib_udata *udata) 5275 { 5276 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5277 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5278 struct hns_roce_v2_qp_context ctx[2]; 5279 struct hns_roce_v2_qp_context *context = ctx; 5280 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5281 struct ib_device *ibdev = &hr_dev->ib_dev; 5282 int ret; 5283 5284 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5285 return -EOPNOTSUPP; 5286 5287 /* 5288 * In v2 engine, software pass context and context mask to hardware 5289 * when modifying qp. If software need modify some fields in context, 5290 * we should set all bits of the relevant fields in context mask to 5291 * 0 at the same time, else set them to 0x1. 5292 */ 5293 memset(context, 0, hr_dev->caps.qpc_sz); 5294 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5295 5296 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5297 new_state, context, qpc_mask, udata); 5298 if (ret) 5299 goto out; 5300 5301 /* When QP state is err, SQ and RQ WQE should be flushed */ 5302 if (new_state == IB_QPS_ERR) 5303 v2_set_flushed_fields(ibqp, context, qpc_mask); 5304 5305 /* Configure the optional fields */ 5306 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5307 qpc_mask); 5308 if (ret) 5309 goto out; 5310 5311 hr_reg_write_bool(context, QPC_INV_CREDIT, 5312 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5313 ibqp->srq); 5314 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5315 5316 /* Every status migrate must change state */ 5317 hr_reg_write(context, QPC_QP_ST, new_state); 5318 hr_reg_clear(qpc_mask, QPC_QP_ST); 5319 5320 /* SW pass context to HW */ 5321 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5322 if (ret) { 5323 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5324 goto out; 5325 } 5326 5327 hr_qp->state = new_state; 5328 5329 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5330 5331 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5332 clear_qp(hr_qp); 5333 5334 out: 5335 return ret; 5336 } 5337 5338 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5339 { 5340 static const enum ib_qp_state map[] = { 5341 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5342 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5343 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5344 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5345 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5346 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5347 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5348 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5349 }; 5350 5351 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5352 } 5353 5354 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5355 void *buffer) 5356 { 5357 struct hns_roce_cmd_mailbox *mailbox; 5358 int ret; 5359 5360 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5361 if (IS_ERR(mailbox)) 5362 return PTR_ERR(mailbox); 5363 5364 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5365 qpn); 5366 if (ret) 5367 goto out; 5368 5369 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5370 5371 out: 5372 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5373 return ret; 5374 } 5375 5376 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5377 void *buffer) 5378 { 5379 struct hns_roce_srq_context *context; 5380 struct hns_roce_cmd_mailbox *mailbox; 5381 int ret; 5382 5383 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5384 if (IS_ERR(mailbox)) 5385 return PTR_ERR(mailbox); 5386 5387 context = mailbox->buf; 5388 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5389 srqn); 5390 if (ret) 5391 goto out; 5392 5393 memcpy(buffer, context, sizeof(*context)); 5394 5395 out: 5396 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5397 return ret; 5398 } 5399 5400 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 qpn, 5401 void *buffer) 5402 { 5403 struct hns_roce_v2_scc_context *context; 5404 struct hns_roce_cmd_mailbox *mailbox; 5405 int ret; 5406 5407 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5408 if (IS_ERR(mailbox)) 5409 return PTR_ERR(mailbox); 5410 5411 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC, 5412 qpn); 5413 if (ret) 5414 goto out; 5415 5416 context = mailbox->buf; 5417 memcpy(buffer, context, sizeof(*context)); 5418 5419 out: 5420 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5421 return ret; 5422 } 5423 5424 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5425 struct hns_roce_v2_qp_context *context) 5426 { 5427 u8 timeout; 5428 5429 timeout = (u8)hr_reg_read(context, QPC_AT); 5430 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5431 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5432 5433 return timeout; 5434 } 5435 5436 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5437 int qp_attr_mask, 5438 struct ib_qp_init_attr *qp_init_attr) 5439 { 5440 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5441 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5442 struct hns_roce_v2_qp_context context = {}; 5443 struct ib_device *ibdev = &hr_dev->ib_dev; 5444 int tmp_qp_state; 5445 int state; 5446 int ret; 5447 5448 memset(qp_attr, 0, sizeof(*qp_attr)); 5449 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5450 5451 mutex_lock(&hr_qp->mutex); 5452 5453 if (hr_qp->state == IB_QPS_RESET) { 5454 qp_attr->qp_state = IB_QPS_RESET; 5455 ret = 0; 5456 goto done; 5457 } 5458 5459 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5460 if (ret) { 5461 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5462 ret = -EINVAL; 5463 goto out; 5464 } 5465 5466 state = hr_reg_read(&context, QPC_QP_ST); 5467 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5468 if (tmp_qp_state == -1) { 5469 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5470 ret = -EINVAL; 5471 goto out; 5472 } 5473 hr_qp->state = (u8)tmp_qp_state; 5474 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5475 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5476 qp_attr->path_mig_state = IB_MIG_ARMED; 5477 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5478 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5479 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5480 5481 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5482 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5483 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5484 qp_attr->qp_access_flags = 5485 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5486 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5487 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5488 5489 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5490 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5491 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5492 struct ib_global_route *grh = 5493 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5494 5495 rdma_ah_set_sl(&qp_attr->ah_attr, 5496 hr_reg_read(&context, QPC_SL)); 5497 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5498 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5499 grh->flow_label = hr_reg_read(&context, QPC_FL); 5500 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5501 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5502 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5503 5504 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5505 } 5506 5507 qp_attr->port_num = hr_qp->port + 1; 5508 qp_attr->sq_draining = 0; 5509 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5510 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5511 5512 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5513 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5514 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5515 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5516 5517 done: 5518 qp_attr->cur_qp_state = qp_attr->qp_state; 5519 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5520 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5521 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5522 5523 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5524 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5525 5526 qp_init_attr->qp_context = ibqp->qp_context; 5527 qp_init_attr->qp_type = ibqp->qp_type; 5528 qp_init_attr->recv_cq = ibqp->recv_cq; 5529 qp_init_attr->send_cq = ibqp->send_cq; 5530 qp_init_attr->srq = ibqp->srq; 5531 qp_init_attr->cap = qp_attr->cap; 5532 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5533 5534 out: 5535 mutex_unlock(&hr_qp->mutex); 5536 return ret; 5537 } 5538 5539 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5540 { 5541 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5542 hr_qp->ibqp.qp_type == IB_QPT_UD || 5543 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5544 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5545 hr_qp->state != IB_QPS_RESET); 5546 } 5547 5548 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5549 struct hns_roce_qp *hr_qp, 5550 struct ib_udata *udata) 5551 { 5552 struct ib_device *ibdev = &hr_dev->ib_dev; 5553 struct hns_roce_cq *send_cq, *recv_cq; 5554 unsigned long flags; 5555 int ret = 0; 5556 5557 if (modify_qp_is_ok(hr_qp)) { 5558 /* Modify qp to reset before destroying qp */ 5559 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5560 hr_qp->state, IB_QPS_RESET, udata); 5561 if (ret) 5562 ibdev_err(ibdev, 5563 "failed to modify QP to RST, ret = %d.\n", 5564 ret); 5565 } 5566 5567 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5568 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5569 5570 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5571 hns_roce_lock_cqs(send_cq, recv_cq); 5572 5573 if (!udata) { 5574 if (recv_cq) 5575 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5576 (hr_qp->ibqp.srq ? 5577 to_hr_srq(hr_qp->ibqp.srq) : 5578 NULL)); 5579 5580 if (send_cq && send_cq != recv_cq) 5581 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5582 } 5583 5584 hns_roce_qp_remove(hr_dev, hr_qp); 5585 5586 hns_roce_unlock_cqs(send_cq, recv_cq); 5587 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5588 5589 return ret; 5590 } 5591 5592 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5593 { 5594 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5595 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5596 int ret; 5597 5598 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5599 if (ret) 5600 ibdev_err(&hr_dev->ib_dev, 5601 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5602 hr_qp->qpn, ret); 5603 5604 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5605 5606 return 0; 5607 } 5608 5609 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5610 struct hns_roce_qp *hr_qp) 5611 { 5612 struct ib_device *ibdev = &hr_dev->ib_dev; 5613 struct hns_roce_sccc_clr_done *resp; 5614 struct hns_roce_sccc_clr *clr; 5615 struct hns_roce_cmq_desc desc; 5616 int ret, i; 5617 5618 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5619 return 0; 5620 5621 mutex_lock(&hr_dev->qp_table.scc_mutex); 5622 5623 /* set scc ctx clear done flag */ 5624 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5625 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5626 if (ret) { 5627 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5628 goto out; 5629 } 5630 5631 /* clear scc context */ 5632 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5633 clr = (struct hns_roce_sccc_clr *)desc.data; 5634 clr->qpn = cpu_to_le32(hr_qp->qpn); 5635 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5636 if (ret) { 5637 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5638 goto out; 5639 } 5640 5641 /* query scc context clear is done or not */ 5642 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5643 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5644 hns_roce_cmq_setup_basic_desc(&desc, 5645 HNS_ROCE_OPC_QUERY_SCCC, true); 5646 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5647 if (ret) { 5648 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5649 ret); 5650 goto out; 5651 } 5652 5653 if (resp->clr_done) 5654 goto out; 5655 5656 msleep(20); 5657 } 5658 5659 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5660 ret = -ETIMEDOUT; 5661 5662 out: 5663 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5664 return ret; 5665 } 5666 5667 #define DMA_IDX_SHIFT 3 5668 #define DMA_WQE_SHIFT 3 5669 5670 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5671 struct hns_roce_srq_context *ctx) 5672 { 5673 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5674 struct ib_device *ibdev = srq->ibsrq.device; 5675 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5676 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5677 dma_addr_t dma_handle_idx; 5678 int ret; 5679 5680 /* Get physical address of idx que buf */ 5681 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5682 ARRAY_SIZE(mtts_idx)); 5683 if (ret) { 5684 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5685 ret); 5686 return ret; 5687 } 5688 5689 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); 5690 5691 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5692 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5693 5694 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5695 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5696 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5697 5698 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5699 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5700 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5701 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5702 5703 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5704 to_hr_hw_page_addr(mtts_idx[0])); 5705 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5706 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5707 5708 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5709 to_hr_hw_page_addr(mtts_idx[1])); 5710 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5711 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5712 5713 return 0; 5714 } 5715 5716 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5717 { 5718 struct ib_device *ibdev = srq->ibsrq.device; 5719 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5720 struct hns_roce_srq_context *ctx = mb_buf; 5721 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5722 dma_addr_t dma_handle_wqe; 5723 int ret; 5724 5725 memset(ctx, 0, sizeof(*ctx)); 5726 5727 /* Get the physical address of srq buf */ 5728 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5729 ARRAY_SIZE(mtts_wqe)); 5730 if (ret) { 5731 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5732 ret); 5733 return ret; 5734 } 5735 5736 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr); 5737 5738 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5739 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5740 srq->ibsrq.srq_type == IB_SRQT_XRC); 5741 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5742 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5743 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5744 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5745 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5746 hr_reg_write(ctx, SRQC_RQWS, 5747 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5748 5749 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5750 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5751 srq->wqe_cnt)); 5752 5753 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5754 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5755 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5756 5757 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5758 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5759 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5760 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5761 5762 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 5763 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 5764 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 5765 lower_32_bits(srq->rdb.dma) >> 1); 5766 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 5767 upper_32_bits(srq->rdb.dma)); 5768 } 5769 5770 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5771 } 5772 5773 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5774 struct ib_srq_attr *srq_attr, 5775 enum ib_srq_attr_mask srq_attr_mask, 5776 struct ib_udata *udata) 5777 { 5778 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5779 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5780 struct hns_roce_srq_context *srq_context; 5781 struct hns_roce_srq_context *srqc_mask; 5782 struct hns_roce_cmd_mailbox *mailbox; 5783 int ret = 0; 5784 5785 /* Resizing SRQs is not supported yet */ 5786 if (srq_attr_mask & IB_SRQ_MAX_WR) { 5787 ret = -EOPNOTSUPP; 5788 goto out; 5789 } 5790 5791 if (srq_attr_mask & IB_SRQ_LIMIT) { 5792 if (srq_attr->srq_limit > srq->wqe_cnt) { 5793 ret = -EINVAL; 5794 goto out; 5795 } 5796 5797 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5798 if (IS_ERR(mailbox)) { 5799 ret = PTR_ERR(mailbox); 5800 goto out; 5801 } 5802 5803 srq_context = mailbox->buf; 5804 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5805 5806 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5807 5808 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5809 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5810 5811 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5812 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5813 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5814 if (ret) 5815 ibdev_err(&hr_dev->ib_dev, 5816 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5817 ret); 5818 } 5819 5820 out: 5821 if (ret) 5822 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]); 5823 5824 return ret; 5825 } 5826 5827 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5828 { 5829 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5830 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5831 struct hns_roce_srq_context *srq_context; 5832 struct hns_roce_cmd_mailbox *mailbox; 5833 int ret; 5834 5835 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5836 if (IS_ERR(mailbox)) 5837 return PTR_ERR(mailbox); 5838 5839 srq_context = mailbox->buf; 5840 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5841 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5842 if (ret) { 5843 ibdev_err(&hr_dev->ib_dev, 5844 "failed to process cmd of querying SRQ, ret = %d.\n", 5845 ret); 5846 goto out; 5847 } 5848 5849 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5850 attr->max_wr = srq->wqe_cnt; 5851 attr->max_sge = srq->max_gs - srq->rsv_sge; 5852 5853 out: 5854 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5855 return ret; 5856 } 5857 5858 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5859 { 5860 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5861 struct hns_roce_v2_cq_context *cq_context; 5862 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5863 struct hns_roce_v2_cq_context *cqc_mask; 5864 struct hns_roce_cmd_mailbox *mailbox; 5865 int ret; 5866 5867 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5868 ret = PTR_ERR_OR_ZERO(mailbox); 5869 if (ret) 5870 goto err_out; 5871 5872 cq_context = mailbox->buf; 5873 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5874 5875 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5876 5877 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5878 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5879 5880 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5881 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5882 dev_info(hr_dev->dev, 5883 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5884 cq_period); 5885 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08; 5886 } 5887 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5888 } 5889 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5890 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5891 5892 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5893 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5894 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5895 if (ret) 5896 ibdev_err(&hr_dev->ib_dev, 5897 "failed to process cmd when modifying CQ, ret = %d.\n", 5898 ret); 5899 5900 err_out: 5901 if (ret) 5902 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]); 5903 5904 return ret; 5905 } 5906 5907 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5908 void *buffer) 5909 { 5910 struct hns_roce_v2_cq_context *context; 5911 struct hns_roce_cmd_mailbox *mailbox; 5912 int ret; 5913 5914 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5915 if (IS_ERR(mailbox)) 5916 return PTR_ERR(mailbox); 5917 5918 context = mailbox->buf; 5919 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5920 HNS_ROCE_CMD_QUERY_CQC, cqn); 5921 if (ret) { 5922 ibdev_err(&hr_dev->ib_dev, 5923 "failed to process cmd when querying CQ, ret = %d.\n", 5924 ret); 5925 goto err_mailbox; 5926 } 5927 5928 memcpy(buffer, context, sizeof(*context)); 5929 5930 err_mailbox: 5931 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5932 5933 return ret; 5934 } 5935 5936 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5937 void *buffer) 5938 { 5939 struct hns_roce_v2_mpt_entry *context; 5940 struct hns_roce_cmd_mailbox *mailbox; 5941 int ret; 5942 5943 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5944 if (IS_ERR(mailbox)) 5945 return PTR_ERR(mailbox); 5946 5947 context = mailbox->buf; 5948 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5949 key_to_hw_index(key)); 5950 if (ret) { 5951 ibdev_err(&hr_dev->ib_dev, 5952 "failed to process cmd when querying MPT, ret = %d.\n", 5953 ret); 5954 goto err_mailbox; 5955 } 5956 5957 memcpy(buffer, context, sizeof(*context)); 5958 5959 err_mailbox: 5960 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5961 5962 return ret; 5963 } 5964 5965 static void hns_roce_irq_work_handle(struct work_struct *work) 5966 { 5967 struct hns_roce_work *irq_work = 5968 container_of(work, struct hns_roce_work, work); 5969 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5970 5971 switch (irq_work->event_type) { 5972 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5973 ibdev_info(ibdev, "path migrated succeeded.\n"); 5974 break; 5975 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5976 ibdev_warn(ibdev, "path migration failed.\n"); 5977 break; 5978 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5979 break; 5980 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5981 ibdev_dbg(ibdev, "send queue drained.\n"); 5982 break; 5983 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5984 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5985 irq_work->queue_num, irq_work->sub_type); 5986 break; 5987 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5988 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5989 irq_work->queue_num); 5990 break; 5991 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5992 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5993 irq_work->queue_num, irq_work->sub_type); 5994 break; 5995 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5996 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 5997 break; 5998 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5999 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 6000 break; 6001 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6002 ibdev_err(ibdev, "SRQ catas error.\n"); 6003 break; 6004 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6005 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 6006 break; 6007 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6008 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 6009 break; 6010 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6011 ibdev_warn(ibdev, "DB overflow.\n"); 6012 break; 6013 case HNS_ROCE_EVENT_TYPE_FLR: 6014 ibdev_warn(ibdev, "function level reset.\n"); 6015 break; 6016 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6017 ibdev_err(ibdev, "xrc domain violation error.\n"); 6018 break; 6019 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6020 ibdev_err(ibdev, "invalid xrceth error.\n"); 6021 break; 6022 default: 6023 break; 6024 } 6025 6026 kfree(irq_work); 6027 } 6028 6029 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 6030 struct hns_roce_eq *eq, u32 queue_num) 6031 { 6032 struct hns_roce_work *irq_work; 6033 6034 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 6035 if (!irq_work) 6036 return; 6037 6038 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 6039 irq_work->hr_dev = hr_dev; 6040 irq_work->event_type = eq->event_type; 6041 irq_work->sub_type = eq->sub_type; 6042 irq_work->queue_num = queue_num; 6043 queue_work(hr_dev->irq_workq, &irq_work->work); 6044 } 6045 6046 static void update_eq_db(struct hns_roce_eq *eq) 6047 { 6048 struct hns_roce_dev *hr_dev = eq->hr_dev; 6049 struct hns_roce_v2_db eq_db = {}; 6050 6051 if (eq->type_flag == HNS_ROCE_AEQ) { 6052 hr_reg_write(&eq_db, EQ_DB_CMD, 6053 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6054 HNS_ROCE_EQ_DB_CMD_AEQ : 6055 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 6056 } else { 6057 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 6058 6059 hr_reg_write(&eq_db, EQ_DB_CMD, 6060 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6061 HNS_ROCE_EQ_DB_CMD_CEQ : 6062 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 6063 } 6064 6065 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 6066 6067 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 6068 } 6069 6070 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 6071 { 6072 struct hns_roce_aeqe *aeqe; 6073 6074 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 6075 (eq->cons_index & (eq->entries - 1)) * 6076 eq->eqe_size); 6077 6078 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 6079 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6080 } 6081 6082 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6083 struct hns_roce_eq *eq) 6084 { 6085 struct device *dev = hr_dev->dev; 6086 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6087 irqreturn_t aeqe_found = IRQ_NONE; 6088 int event_type; 6089 u32 queue_num; 6090 int sub_type; 6091 6092 while (aeqe) { 6093 /* Make sure we read AEQ entry after we have checked the 6094 * ownership bit 6095 */ 6096 dma_rmb(); 6097 6098 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6099 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6100 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6101 6102 switch (event_type) { 6103 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6104 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6105 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6106 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6107 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6108 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6109 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6110 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6111 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6112 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6113 hns_roce_qp_event(hr_dev, queue_num, event_type); 6114 break; 6115 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6116 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6117 hns_roce_srq_event(hr_dev, queue_num, event_type); 6118 break; 6119 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6120 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6121 hns_roce_cq_event(hr_dev, queue_num, event_type); 6122 break; 6123 case HNS_ROCE_EVENT_TYPE_MB: 6124 hns_roce_cmd_event(hr_dev, 6125 le16_to_cpu(aeqe->event.cmd.token), 6126 aeqe->event.cmd.status, 6127 le64_to_cpu(aeqe->event.cmd.out_param)); 6128 break; 6129 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6130 case HNS_ROCE_EVENT_TYPE_FLR: 6131 break; 6132 default: 6133 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n", 6134 event_type, eq->eqn, eq->cons_index); 6135 break; 6136 } 6137 6138 eq->event_type = event_type; 6139 eq->sub_type = sub_type; 6140 ++eq->cons_index; 6141 aeqe_found = IRQ_HANDLED; 6142 6143 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]); 6144 6145 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6146 6147 aeqe = next_aeqe_sw_v2(eq); 6148 } 6149 6150 update_eq_db(eq); 6151 6152 return IRQ_RETVAL(aeqe_found); 6153 } 6154 6155 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6156 { 6157 struct hns_roce_ceqe *ceqe; 6158 6159 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6160 (eq->cons_index & (eq->entries - 1)) * 6161 eq->eqe_size); 6162 6163 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6164 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6165 } 6166 6167 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq) 6168 { 6169 queue_work(system_bh_wq, &eq->work); 6170 6171 return IRQ_HANDLED; 6172 } 6173 6174 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6175 { 6176 struct hns_roce_eq *eq = eq_ptr; 6177 struct hns_roce_dev *hr_dev = eq->hr_dev; 6178 irqreturn_t int_work; 6179 6180 if (eq->type_flag == HNS_ROCE_CEQ) 6181 /* Completion event interrupt */ 6182 int_work = hns_roce_v2_ceq_int(eq); 6183 else 6184 /* Asynchronous event interrupt */ 6185 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6186 6187 return IRQ_RETVAL(int_work); 6188 } 6189 6190 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6191 u32 int_st) 6192 { 6193 struct pci_dev *pdev = hr_dev->pci_dev; 6194 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6195 const struct hnae3_ae_ops *ops = ae_dev->ops; 6196 irqreturn_t int_work = IRQ_NONE; 6197 u32 int_en; 6198 6199 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6200 6201 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6202 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6203 6204 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6205 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6206 6207 /* Set reset level for reset_event() */ 6208 if (ops->set_default_reset_request) 6209 ops->set_default_reset_request(ae_dev, 6210 HNAE3_FUNC_RESET); 6211 if (ops->reset_event) 6212 ops->reset_event(pdev, NULL); 6213 6214 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6215 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6216 6217 int_work = IRQ_HANDLED; 6218 } else { 6219 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6220 } 6221 6222 return IRQ_RETVAL(int_work); 6223 } 6224 6225 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6226 struct fmea_ram_ecc *ecc_info) 6227 { 6228 struct hns_roce_cmq_desc desc; 6229 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6230 int ret; 6231 6232 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6233 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6234 if (ret) 6235 return ret; 6236 6237 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6238 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6239 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6240 6241 return 0; 6242 } 6243 6244 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6245 { 6246 struct hns_roce_cmq_desc desc; 6247 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6248 u32 addr_upper; 6249 u32 addr_low; 6250 int ret; 6251 6252 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6253 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6254 6255 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6256 if (ret) { 6257 dev_err(hr_dev->dev, 6258 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6259 return ret; 6260 } 6261 6262 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6263 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6264 6265 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6266 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6267 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6268 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6269 6270 return hns_roce_cmq_send(hr_dev, &desc, 1); 6271 } 6272 6273 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6274 { 6275 if (res_type == ECC_RESOURCE_QPC_TIMER || 6276 res_type == ECC_RESOURCE_CQC_TIMER || 6277 res_type == ECC_RESOURCE_SCCC) 6278 return le64_to_cpu(*data); 6279 6280 return le64_to_cpu(*data) << PAGE_SHIFT; 6281 } 6282 6283 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6284 u32 index) 6285 { 6286 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6287 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6288 struct hns_roce_cmd_mailbox *mailbox; 6289 u64 addr; 6290 int ret; 6291 6292 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6293 if (IS_ERR(mailbox)) 6294 return PTR_ERR(mailbox); 6295 6296 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6297 if (ret) { 6298 dev_err(hr_dev->dev, 6299 "failed to execute cmd to read fmea ram, ret = %d.\n", 6300 ret); 6301 goto out; 6302 } 6303 6304 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6305 6306 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6307 if (ret) 6308 dev_err(hr_dev->dev, 6309 "failed to execute cmd to write fmea ram, ret = %d.\n", 6310 ret); 6311 6312 out: 6313 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6314 return ret; 6315 } 6316 6317 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6318 struct fmea_ram_ecc *ecc_info) 6319 { 6320 u32 res_type = ecc_info->res_type; 6321 u32 index = ecc_info->index; 6322 int ret; 6323 6324 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6325 6326 if (res_type >= ECC_RESOURCE_COUNT) { 6327 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6328 res_type); 6329 return; 6330 } 6331 6332 if (res_type == ECC_RESOURCE_GMV) 6333 ret = fmea_recover_gmv(hr_dev, index); 6334 else 6335 ret = fmea_recover_others(hr_dev, res_type, index); 6336 if (ret) 6337 dev_err(hr_dev->dev, 6338 "failed to recover %s, index = %u, ret = %d.\n", 6339 fmea_ram_res[res_type].name, index, ret); 6340 } 6341 6342 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6343 { 6344 struct hns_roce_dev *hr_dev = 6345 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6346 struct fmea_ram_ecc ecc_info = {}; 6347 6348 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6349 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6350 return; 6351 } 6352 6353 if (!ecc_info.is_ecc_err) { 6354 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6355 return; 6356 } 6357 6358 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6359 } 6360 6361 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6362 { 6363 struct hns_roce_dev *hr_dev = dev_id; 6364 irqreturn_t int_work = IRQ_NONE; 6365 u32 int_st; 6366 6367 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6368 6369 if (int_st) { 6370 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6371 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6372 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6373 int_work = IRQ_HANDLED; 6374 } else { 6375 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6376 } 6377 6378 return IRQ_RETVAL(int_work); 6379 } 6380 6381 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6382 int eq_num, u32 enable_flag) 6383 { 6384 int i; 6385 6386 for (i = 0; i < eq_num; i++) 6387 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6388 i * EQ_REG_OFFSET, enable_flag); 6389 6390 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6391 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6392 } 6393 6394 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6395 { 6396 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6397 } 6398 6399 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, 6400 struct hns_roce_eq *eq) 6401 { 6402 struct device *dev = hr_dev->dev; 6403 int eqn = eq->eqn; 6404 int ret; 6405 u8 cmd; 6406 6407 if (eqn < hr_dev->caps.num_comp_vectors) 6408 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6409 else 6410 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6411 6412 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6413 if (ret) 6414 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 6415 6416 free_eq_buf(hr_dev, eq); 6417 } 6418 6419 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6420 { 6421 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6422 eq->cons_index = 0; 6423 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6424 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6425 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6426 eq->shift = ilog2((unsigned int)eq->entries); 6427 } 6428 6429 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6430 void *mb_buf) 6431 { 6432 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6433 struct hns_roce_eq_context *eqc; 6434 u64 bt_ba = 0; 6435 int ret; 6436 6437 eqc = mb_buf; 6438 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6439 6440 init_eq_config(hr_dev, eq); 6441 6442 /* if not multi-hop, eqe buffer only use one trunk */ 6443 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, 6444 ARRAY_SIZE(eqe_ba)); 6445 if (ret) { 6446 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret); 6447 return ret; 6448 } 6449 6450 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); 6451 6452 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6453 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6454 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6455 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6456 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6457 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6458 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6459 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6460 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6461 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6462 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6463 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6464 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6465 6466 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6467 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6468 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6469 eq->eq_period); 6470 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6471 } 6472 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6473 } 6474 6475 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6476 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6477 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6478 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6479 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6480 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6481 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6482 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6483 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6484 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6485 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6486 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6487 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6488 6489 return 0; 6490 } 6491 6492 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6493 { 6494 struct hns_roce_buf_attr buf_attr = {}; 6495 int err; 6496 6497 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6498 eq->hop_num = 0; 6499 else 6500 eq->hop_num = hr_dev->caps.eqe_hop_num; 6501 6502 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6503 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6504 buf_attr.region[0].hopnum = eq->hop_num; 6505 buf_attr.region_count = 1; 6506 6507 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6508 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6509 0); 6510 if (err) 6511 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6512 6513 return err; 6514 } 6515 6516 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6517 struct hns_roce_eq *eq, u8 eq_cmd) 6518 { 6519 struct hns_roce_cmd_mailbox *mailbox; 6520 int ret; 6521 6522 /* Allocate mailbox memory */ 6523 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6524 if (IS_ERR(mailbox)) 6525 return PTR_ERR(mailbox); 6526 6527 ret = alloc_eq_buf(hr_dev, eq); 6528 if (ret) 6529 goto free_cmd_mbox; 6530 6531 ret = config_eqc(hr_dev, eq, mailbox->buf); 6532 if (ret) 6533 goto err_cmd_mbox; 6534 6535 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6536 if (ret) { 6537 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6538 goto err_cmd_mbox; 6539 } 6540 6541 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6542 6543 return 0; 6544 6545 err_cmd_mbox: 6546 free_eq_buf(hr_dev, eq); 6547 6548 free_cmd_mbox: 6549 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6550 6551 return ret; 6552 } 6553 6554 static void hns_roce_ceq_work(struct work_struct *work) 6555 { 6556 struct hns_roce_eq *eq = from_work(eq, work, work); 6557 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6558 struct hns_roce_dev *hr_dev = eq->hr_dev; 6559 int ceqe_num = 0; 6560 u32 cqn; 6561 6562 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) { 6563 /* Make sure we read CEQ entry after we have checked the 6564 * ownership bit 6565 */ 6566 dma_rmb(); 6567 6568 cqn = hr_reg_read(ceqe, CEQE_CQN); 6569 6570 hns_roce_cq_completion(hr_dev, cqn); 6571 6572 ++eq->cons_index; 6573 ++ceqe_num; 6574 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]); 6575 6576 ceqe = next_ceqe_sw_v2(eq); 6577 } 6578 6579 update_eq_db(eq); 6580 } 6581 6582 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6583 int comp_num, int aeq_num, int other_num) 6584 { 6585 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6586 int i, j; 6587 int ret; 6588 6589 for (i = 0; i < irq_num; i++) { 6590 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6591 GFP_KERNEL); 6592 if (!hr_dev->irq_names[i]) { 6593 ret = -ENOMEM; 6594 goto err_kzalloc_failed; 6595 } 6596 } 6597 6598 /* irq contains: abnormal + AEQ + CEQ */ 6599 for (j = 0; j < other_num; j++) 6600 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6601 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j); 6602 6603 for (j = other_num; j < (other_num + aeq_num); j++) 6604 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6605 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num); 6606 6607 for (j = (other_num + aeq_num); j < irq_num; j++) 6608 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6609 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev), 6610 j - other_num - aeq_num); 6611 6612 for (j = 0; j < irq_num; j++) { 6613 if (j < other_num) { 6614 ret = request_irq(hr_dev->irq[j], 6615 hns_roce_v2_msix_interrupt_abn, 6616 0, hr_dev->irq_names[j], hr_dev); 6617 } else if (j < (other_num + comp_num)) { 6618 INIT_WORK(&eq_table->eq[j - other_num].work, 6619 hns_roce_ceq_work); 6620 ret = request_irq(eq_table->eq[j - other_num].irq, 6621 hns_roce_v2_msix_interrupt_eq, 6622 0, hr_dev->irq_names[j + aeq_num], 6623 &eq_table->eq[j - other_num]); 6624 } else { 6625 ret = request_irq(eq_table->eq[j - other_num].irq, 6626 hns_roce_v2_msix_interrupt_eq, 6627 0, hr_dev->irq_names[j - comp_num], 6628 &eq_table->eq[j - other_num]); 6629 } 6630 6631 if (ret) { 6632 dev_err(hr_dev->dev, "request irq error!\n"); 6633 goto err_request_failed; 6634 } 6635 } 6636 6637 return 0; 6638 6639 err_request_failed: 6640 for (j -= 1; j >= 0; j--) { 6641 if (j < other_num) { 6642 free_irq(hr_dev->irq[j], hr_dev); 6643 continue; 6644 } 6645 free_irq(eq_table->eq[j - other_num].irq, 6646 &eq_table->eq[j - other_num]); 6647 if (j < other_num + comp_num) 6648 cancel_work_sync(&eq_table->eq[j - other_num].work); 6649 } 6650 6651 err_kzalloc_failed: 6652 for (i -= 1; i >= 0; i--) 6653 kfree(hr_dev->irq_names[i]); 6654 6655 return ret; 6656 } 6657 6658 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6659 { 6660 int irq_num; 6661 int eq_num; 6662 int i; 6663 6664 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6665 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6666 6667 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6668 free_irq(hr_dev->irq[i], hr_dev); 6669 6670 for (i = 0; i < eq_num; i++) { 6671 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6672 if (i < hr_dev->caps.num_comp_vectors) 6673 cancel_work_sync(&hr_dev->eq_table.eq[i].work); 6674 } 6675 6676 for (i = 0; i < irq_num; i++) 6677 kfree(hr_dev->irq_names[i]); 6678 } 6679 6680 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6681 { 6682 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6683 struct device *dev = hr_dev->dev; 6684 struct hns_roce_eq *eq; 6685 int other_num; 6686 int comp_num; 6687 int aeq_num; 6688 int irq_num; 6689 int eq_num; 6690 u8 eq_cmd; 6691 int ret; 6692 int i; 6693 6694 other_num = hr_dev->caps.num_other_vectors; 6695 comp_num = hr_dev->caps.num_comp_vectors; 6696 aeq_num = hr_dev->caps.num_aeq_vectors; 6697 6698 eq_num = comp_num + aeq_num; 6699 irq_num = eq_num + other_num; 6700 6701 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6702 if (!eq_table->eq) 6703 return -ENOMEM; 6704 6705 /* create eq */ 6706 for (i = 0; i < eq_num; i++) { 6707 eq = &eq_table->eq[i]; 6708 eq->hr_dev = hr_dev; 6709 eq->eqn = i; 6710 if (i < comp_num) { 6711 /* CEQ */ 6712 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6713 eq->type_flag = HNS_ROCE_CEQ; 6714 eq->entries = hr_dev->caps.ceqe_depth; 6715 eq->eqe_size = hr_dev->caps.ceqe_size; 6716 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6717 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6718 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6719 } else { 6720 /* AEQ */ 6721 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6722 eq->type_flag = HNS_ROCE_AEQ; 6723 eq->entries = hr_dev->caps.aeqe_depth; 6724 eq->eqe_size = hr_dev->caps.aeqe_size; 6725 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6726 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6727 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6728 } 6729 6730 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6731 if (ret) { 6732 dev_err(dev, "failed to create eq.\n"); 6733 goto err_create_eq_fail; 6734 } 6735 } 6736 6737 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6738 6739 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6740 if (!hr_dev->irq_workq) { 6741 dev_err(dev, "failed to create irq workqueue.\n"); 6742 ret = -ENOMEM; 6743 goto err_create_eq_fail; 6744 } 6745 6746 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6747 other_num); 6748 if (ret) { 6749 dev_err(dev, "failed to request irq.\n"); 6750 goto err_request_irq_fail; 6751 } 6752 6753 /* enable irq */ 6754 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6755 6756 return 0; 6757 6758 err_request_irq_fail: 6759 destroy_workqueue(hr_dev->irq_workq); 6760 6761 err_create_eq_fail: 6762 for (i -= 1; i >= 0; i--) 6763 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6764 kfree(eq_table->eq); 6765 6766 return ret; 6767 } 6768 6769 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6770 { 6771 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6772 int eq_num; 6773 int i; 6774 6775 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6776 6777 /* Disable irq */ 6778 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6779 6780 __hns_roce_free_irq(hr_dev); 6781 destroy_workqueue(hr_dev->irq_workq); 6782 6783 for (i = 0; i < eq_num; i++) 6784 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6785 6786 kfree(eq_table->eq); 6787 } 6788 6789 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6790 .destroy_qp = hns_roce_v2_destroy_qp, 6791 .modify_cq = hns_roce_v2_modify_cq, 6792 .poll_cq = hns_roce_v2_poll_cq, 6793 .post_recv = hns_roce_v2_post_recv, 6794 .post_send = hns_roce_v2_post_send, 6795 .query_qp = hns_roce_v2_query_qp, 6796 .req_notify_cq = hns_roce_v2_req_notify_cq, 6797 }; 6798 6799 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6800 .modify_srq = hns_roce_v2_modify_srq, 6801 .post_srq_recv = hns_roce_v2_post_srq_recv, 6802 .query_srq = hns_roce_v2_query_srq, 6803 }; 6804 6805 static const struct hns_roce_hw hns_roce_hw_v2 = { 6806 .cmq_init = hns_roce_v2_cmq_init, 6807 .cmq_exit = hns_roce_v2_cmq_exit, 6808 .hw_profile = hns_roce_v2_profile, 6809 .hw_init = hns_roce_v2_init, 6810 .hw_exit = hns_roce_v2_exit, 6811 .post_mbox = v2_post_mbox, 6812 .poll_mbox_done = v2_poll_mbox_done, 6813 .chk_mbox_avail = v2_chk_mbox_is_avail, 6814 .set_gid = hns_roce_v2_set_gid, 6815 .set_mac = hns_roce_v2_set_mac, 6816 .write_mtpt = hns_roce_v2_write_mtpt, 6817 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6818 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6819 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6820 .write_cqc = hns_roce_v2_write_cqc, 6821 .set_hem = hns_roce_v2_set_hem, 6822 .clear_hem = hns_roce_v2_clear_hem, 6823 .modify_qp = hns_roce_v2_modify_qp, 6824 .dereg_mr = hns_roce_v2_dereg_mr, 6825 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6826 .init_eq = hns_roce_v2_init_eq_table, 6827 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6828 .write_srqc = hns_roce_v2_write_srqc, 6829 .query_cqc = hns_roce_v2_query_cqc, 6830 .query_qpc = hns_roce_v2_query_qpc, 6831 .query_mpt = hns_roce_v2_query_mpt, 6832 .query_srqc = hns_roce_v2_query_srqc, 6833 .query_sccc = hns_roce_v2_query_sccc, 6834 .query_hw_counter = hns_roce_hw_v2_query_counter, 6835 .get_dscp = hns_roce_hw_v2_get_dscp, 6836 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6837 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6838 }; 6839 6840 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6841 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6842 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6843 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6844 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6845 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6846 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6847 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6848 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6849 /* required last entry */ 6850 {0, } 6851 }; 6852 6853 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6854 6855 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6856 struct hnae3_handle *handle) 6857 { 6858 struct hns_roce_v2_priv *priv = hr_dev->priv; 6859 const struct pci_device_id *id; 6860 int i; 6861 6862 hr_dev->pci_dev = handle->pdev; 6863 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6864 hr_dev->is_vf = id->driver_data; 6865 hr_dev->dev = &handle->pdev->dev; 6866 hr_dev->hw = &hns_roce_hw_v2; 6867 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6868 hr_dev->odb_offset = hr_dev->sdb_offset; 6869 6870 /* Get info from NIC driver. */ 6871 hr_dev->reg_base = handle->rinfo.roce_io_base; 6872 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6873 hr_dev->caps.num_ports = 1; 6874 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6875 hr_dev->iboe.phy_port[0] = 0; 6876 6877 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6878 hr_dev->iboe.netdevs[0]->dev_addr); 6879 6880 for (i = 0; i < handle->rinfo.num_vectors; i++) 6881 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6882 i + handle->rinfo.base_vector); 6883 6884 /* cmd issue mode: 0 is poll, 1 is event */ 6885 hr_dev->cmd_mod = 1; 6886 hr_dev->loop_idc = 0; 6887 6888 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6889 priv->handle = handle; 6890 } 6891 6892 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6893 { 6894 struct hns_roce_dev *hr_dev; 6895 int ret; 6896 6897 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6898 if (!hr_dev) 6899 return -ENOMEM; 6900 6901 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6902 if (!hr_dev->priv) { 6903 ret = -ENOMEM; 6904 goto error_failed_kzalloc; 6905 } 6906 6907 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6908 6909 ret = hns_roce_init(hr_dev); 6910 if (ret) { 6911 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6912 goto error_failed_roce_init; 6913 } 6914 6915 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6916 ret = free_mr_init(hr_dev); 6917 if (ret) { 6918 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6919 goto error_failed_free_mr_init; 6920 } 6921 } 6922 6923 handle->priv = hr_dev; 6924 6925 return 0; 6926 6927 error_failed_free_mr_init: 6928 hns_roce_exit(hr_dev); 6929 6930 error_failed_roce_init: 6931 kfree(hr_dev->priv); 6932 6933 error_failed_kzalloc: 6934 ib_dealloc_device(&hr_dev->ib_dev); 6935 6936 return ret; 6937 } 6938 6939 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6940 bool reset) 6941 { 6942 struct hns_roce_dev *hr_dev = handle->priv; 6943 6944 if (!hr_dev) 6945 return; 6946 6947 handle->priv = NULL; 6948 6949 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6950 hns_roce_handle_device_err(hr_dev); 6951 6952 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6953 free_mr_exit(hr_dev); 6954 6955 hns_roce_exit(hr_dev); 6956 kfree(hr_dev->priv); 6957 ib_dealloc_device(&hr_dev->ib_dev); 6958 } 6959 6960 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6961 { 6962 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6963 const struct pci_device_id *id; 6964 struct device *dev = &handle->pdev->dev; 6965 int ret; 6966 6967 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6968 6969 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6970 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6971 goto reset_chk_err; 6972 } 6973 6974 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6975 if (!id) 6976 return 0; 6977 6978 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6979 return 0; 6980 6981 ret = __hns_roce_hw_v2_init_instance(handle); 6982 if (ret) { 6983 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6984 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6985 if (ops->ae_dev_resetting(handle) || 6986 ops->get_hw_reset_stat(handle)) 6987 goto reset_chk_err; 6988 else 6989 return ret; 6990 } 6991 6992 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6993 6994 return 0; 6995 6996 reset_chk_err: 6997 dev_err(dev, "Device is busy in resetting state.\n" 6998 "please retry later.\n"); 6999 7000 return -EBUSY; 7001 } 7002 7003 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7004 bool reset) 7005 { 7006 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7007 return; 7008 7009 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 7010 7011 __hns_roce_hw_v2_uninit_instance(handle, reset); 7012 7013 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7014 } 7015 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 7016 { 7017 struct hns_roce_dev *hr_dev; 7018 7019 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 7020 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7021 return 0; 7022 } 7023 7024 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 7025 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7026 7027 hr_dev = handle->priv; 7028 if (!hr_dev) 7029 return 0; 7030 7031 hr_dev->active = false; 7032 hr_dev->dis_db = true; 7033 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 7034 7035 return 0; 7036 } 7037 7038 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 7039 { 7040 struct device *dev = &handle->pdev->dev; 7041 int ret; 7042 7043 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 7044 &handle->rinfo.state)) { 7045 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7046 return 0; 7047 } 7048 7049 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 7050 7051 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 7052 ret = __hns_roce_hw_v2_init_instance(handle); 7053 if (ret) { 7054 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 7055 * callback function, RoCE Engine reinitialize. If RoCE reinit 7056 * failed, we should inform NIC driver. 7057 */ 7058 handle->priv = NULL; 7059 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 7060 } else { 7061 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7062 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 7063 } 7064 7065 return ret; 7066 } 7067 7068 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 7069 { 7070 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 7071 return 0; 7072 7073 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 7074 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 7075 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 7076 __hns_roce_hw_v2_uninit_instance(handle, false); 7077 7078 return 0; 7079 } 7080 7081 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 7082 enum hnae3_reset_notify_type type) 7083 { 7084 int ret = 0; 7085 7086 switch (type) { 7087 case HNAE3_DOWN_CLIENT: 7088 ret = hns_roce_hw_v2_reset_notify_down(handle); 7089 break; 7090 case HNAE3_INIT_CLIENT: 7091 ret = hns_roce_hw_v2_reset_notify_init(handle); 7092 break; 7093 case HNAE3_UNINIT_CLIENT: 7094 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 7095 break; 7096 default: 7097 break; 7098 } 7099 7100 return ret; 7101 } 7102 7103 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7104 .init_instance = hns_roce_hw_v2_init_instance, 7105 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7106 .reset_notify = hns_roce_hw_v2_reset_notify, 7107 }; 7108 7109 static struct hnae3_client hns_roce_hw_v2_client = { 7110 .name = "hns_roce_hw_v2", 7111 .type = HNAE3_CLIENT_ROCE, 7112 .ops = &hns_roce_hw_v2_ops, 7113 }; 7114 7115 static int __init hns_roce_hw_v2_init(void) 7116 { 7117 hns_roce_init_debugfs(); 7118 return hnae3_register_client(&hns_roce_hw_v2_client); 7119 } 7120 7121 static void __exit hns_roce_hw_v2_exit(void) 7122 { 7123 hnae3_unregister_client(&hns_roce_hw_v2_client); 7124 hns_roce_cleanup_debugfs(); 7125 } 7126 7127 module_init(hns_roce_hw_v2_init); 7128 module_exit(hns_roce_hw_v2_exit); 7129 7130 MODULE_LICENSE("Dual BSD/GPL"); 7131 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7132 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7133 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7134 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7135