1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Texas Instruments Keystone SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments., Ltd. 6 * https://www.ti.com 7 * 8 * Author: Murali Karicheri <m-karicheri2@ti.com> 9 * Implementation based on pci-exynos.c and pcie-designware.c 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/msi.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_pci.h> 24 #include <linux/phy/phy.h> 25 #include <linux/platform_device.h> 26 #include <linux/regmap.h> 27 #include <linux/resource.h> 28 #include <linux/signal.h> 29 30 #include "../../pci.h" 31 #include "pcie-designware.h" 32 33 #define PCIE_VENDORID_MASK 0xffff 34 #define PCIE_DEVICEID_SHIFT 16 35 36 /* Application registers */ 37 #define PID 0x000 38 #define RTL GENMASK(15, 11) 39 #define RTL_SHIFT 11 40 #define AM6_PCI_PG1_RTL_VER 0x15 41 42 #define CMD_STATUS 0x004 43 #define LTSSM_EN_VAL BIT(0) 44 #define OB_XLAT_EN_VAL BIT(1) 45 #define DBI_CS2 BIT(5) 46 47 #define CFG_SETUP 0x008 48 #define CFG_BUS(x) (((x) & 0xff) << 16) 49 #define CFG_DEVICE(x) (((x) & 0x1f) << 8) 50 #define CFG_FUNC(x) ((x) & 0x7) 51 #define CFG_TYPE1 BIT(24) 52 53 #define OB_SIZE 0x030 54 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 55 #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 56 #define OB_ENABLEN BIT(0) 57 #define OB_WIN_SIZE 8 /* 8MB */ 58 59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) 60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) 61 #define PCIE_EP_IRQ_SET 0x64 62 #define PCIE_EP_IRQ_CLR 0x68 63 #define INT_ENABLE BIT(0) 64 65 /* IRQ register defines */ 66 #define IRQ_EOI 0x050 67 68 #define MSI_IRQ 0x054 69 #define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) 70 #define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) 71 #define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) 72 #define MSI_IRQ_OFFSET 4 73 74 #define IRQ_STATUS(n) (0x184 + ((n) << 4)) 75 #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) 76 #define INTx_EN BIT(0) 77 78 #define ERR_IRQ_STATUS 0x1c4 79 #define ERR_IRQ_ENABLE_SET 0x1c8 80 #define ERR_AER BIT(5) /* ECRC error */ 81 #define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ 82 #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ 83 #define ERR_CORR BIT(3) /* Correctable error */ 84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */ 85 #define ERR_FATAL BIT(1) /* Fatal error */ 86 #define ERR_SYS BIT(0) /* System error */ 87 #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ 88 ERR_NONFATAL | ERR_FATAL | ERR_SYS) 89 90 /* PCIE controller device IDs */ 91 #define PCIE_RC_K2HK 0xb008 92 #define PCIE_RC_K2E 0xb009 93 #define PCIE_RC_K2L 0xb00a 94 #define PCIE_RC_K2G 0xb00b 95 96 #define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) 97 #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) 98 99 #define EP 0x0 100 #define LEG_EP 0x1 101 #define RC 0x2 102 103 #define KS_PCIE_SYSCLOCKOUTEN BIT(0) 104 105 #define AM654_PCIE_DEV_TYPE_MASK 0x3 106 #define AM654_WIN_SIZE SZ_64K 107 108 #define APP_ADDR_SPACE_0 (16 * SZ_1K) 109 110 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 111 112 #define PCI_DEVICE_ID_TI_AM654X 0xb00c 113 114 struct ks_pcie_of_data { 115 enum dw_pcie_device_mode mode; 116 const struct dw_pcie_host_ops *host_ops; 117 const struct dw_pcie_ep_ops *ep_ops; 118 u32 version; 119 }; 120 121 struct keystone_pcie { 122 struct dw_pcie *pci; 123 /* PCI Device ID */ 124 u32 device_id; 125 int intx_host_irqs[PCI_NUM_INTX]; 126 127 int msi_host_irq; 128 int num_lanes; 129 u32 num_viewport; 130 struct phy **phy; 131 struct device_link **link; 132 struct device_node *msi_intc_np; 133 struct irq_domain *intx_irq_domain; 134 struct device_node *np; 135 136 /* Application register space */ 137 void __iomem *va_app_base; /* DT 1st resource */ 138 struct resource app; 139 bool is_am6; 140 }; 141 142 static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) 143 { 144 return readl(ks_pcie->va_app_base + offset); 145 } 146 147 static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, 148 u32 val) 149 { 150 writel(val, ks_pcie->va_app_base + offset); 151 } 152 153 static void ks_pcie_msi_irq_ack(struct irq_data *data) 154 { 155 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 156 struct keystone_pcie *ks_pcie; 157 u32 irq = data->hwirq; 158 struct dw_pcie *pci; 159 u32 reg_offset; 160 u32 bit_pos; 161 162 pci = to_dw_pcie_from_pp(pp); 163 ks_pcie = to_keystone_pcie(pci); 164 165 reg_offset = irq % 8; 166 bit_pos = irq >> 3; 167 168 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), 169 BIT(bit_pos)); 170 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); 171 } 172 173 static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 174 { 175 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 176 struct keystone_pcie *ks_pcie; 177 struct dw_pcie *pci; 178 u64 msi_target; 179 180 pci = to_dw_pcie_from_pp(pp); 181 ks_pcie = to_keystone_pcie(pci); 182 183 msi_target = ks_pcie->app.start + MSI_IRQ; 184 msg->address_lo = lower_32_bits(msi_target); 185 msg->address_hi = upper_32_bits(msi_target); 186 msg->data = data->hwirq; 187 188 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 189 (int)data->hwirq, msg->address_hi, msg->address_lo); 190 } 191 192 static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, 193 const struct cpumask *mask, bool force) 194 { 195 return -EINVAL; 196 } 197 198 static void ks_pcie_msi_mask(struct irq_data *data) 199 { 200 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 201 struct keystone_pcie *ks_pcie; 202 u32 irq = data->hwirq; 203 struct dw_pcie *pci; 204 unsigned long flags; 205 u32 reg_offset; 206 u32 bit_pos; 207 208 raw_spin_lock_irqsave(&pp->lock, flags); 209 210 pci = to_dw_pcie_from_pp(pp); 211 ks_pcie = to_keystone_pcie(pci); 212 213 reg_offset = irq % 8; 214 bit_pos = irq >> 3; 215 216 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), 217 BIT(bit_pos)); 218 219 raw_spin_unlock_irqrestore(&pp->lock, flags); 220 } 221 222 static void ks_pcie_msi_unmask(struct irq_data *data) 223 { 224 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 225 struct keystone_pcie *ks_pcie; 226 u32 irq = data->hwirq; 227 struct dw_pcie *pci; 228 unsigned long flags; 229 u32 reg_offset; 230 u32 bit_pos; 231 232 raw_spin_lock_irqsave(&pp->lock, flags); 233 234 pci = to_dw_pcie_from_pp(pp); 235 ks_pcie = to_keystone_pcie(pci); 236 237 reg_offset = irq % 8; 238 bit_pos = irq >> 3; 239 240 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), 241 BIT(bit_pos)); 242 243 raw_spin_unlock_irqrestore(&pp->lock, flags); 244 } 245 246 static struct irq_chip ks_pcie_msi_irq_chip = { 247 .name = "KEYSTONE-PCI-MSI", 248 .irq_ack = ks_pcie_msi_irq_ack, 249 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 250 .irq_set_affinity = ks_pcie_msi_set_affinity, 251 .irq_mask = ks_pcie_msi_mask, 252 .irq_unmask = ks_pcie_msi_unmask, 253 }; 254 255 /** 256 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers 257 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 258 * PCIe host controller driver information. 259 * 260 * Since modification of dbi_cs2 involves different clock domain, read the 261 * status back to ensure the transition is complete. 262 */ 263 static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) 264 { 265 u32 val; 266 267 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 268 val |= DBI_CS2; 269 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 270 271 do { 272 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 273 } while (!(val & DBI_CS2)); 274 } 275 276 /** 277 * ks_pcie_clear_dbi_mode() - Disable DBI mode 278 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 279 * PCIe host controller driver information. 280 * 281 * Since modification of dbi_cs2 involves different clock domain, read the 282 * status back to ensure the transition is complete. 283 */ 284 static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 285 { 286 u32 val; 287 288 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 289 val &= ~DBI_CS2; 290 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 291 292 do { 293 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 294 } while (val & DBI_CS2); 295 } 296 297 static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) 298 { 299 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 300 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 301 302 /* Configure and set up BAR0 */ 303 ks_pcie_set_dbi_mode(ks_pcie); 304 305 /* Enable BAR0 */ 306 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 307 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 308 309 ks_pcie_clear_dbi_mode(ks_pcie); 310 311 /* 312 * For BAR0, just setting bus address for inbound writes (MSI) should 313 * be sufficient. Use physical address to avoid any conflicts. 314 */ 315 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 316 317 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; 318 return dw_pcie_allocate_domains(pp); 319 } 320 321 static void ks_pcie_handle_intx_irq(struct keystone_pcie *ks_pcie, 322 int offset) 323 { 324 struct dw_pcie *pci = ks_pcie->pci; 325 struct device *dev = pci->dev; 326 u32 pending; 327 328 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); 329 330 if (BIT(0) & pending) { 331 dev_dbg(dev, ": irq: irq_offset %d", offset); 332 generic_handle_domain_irq(ks_pcie->intx_irq_domain, offset); 333 } 334 335 /* EOI the INTx interrupt */ 336 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 337 } 338 339 static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 340 { 341 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 342 } 343 344 static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) 345 { 346 u32 reg; 347 struct device *dev = ks_pcie->pci->dev; 348 349 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); 350 if (!reg) 351 return IRQ_NONE; 352 353 if (reg & ERR_SYS) 354 dev_err(dev, "System Error\n"); 355 356 if (reg & ERR_FATAL) 357 dev_err(dev, "Fatal Error\n"); 358 359 if (reg & ERR_NONFATAL) 360 dev_dbg(dev, "Non Fatal Error\n"); 361 362 if (reg & ERR_CORR) 363 dev_dbg(dev, "Correctable Error\n"); 364 365 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) 366 dev_err(dev, "AXI tag lookup fatal Error\n"); 367 368 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) 369 dev_err(dev, "ECRC Error\n"); 370 371 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); 372 373 return IRQ_HANDLED; 374 } 375 376 static void ks_pcie_ack_intx_irq(struct irq_data *d) 377 { 378 } 379 380 static void ks_pcie_mask_intx_irq(struct irq_data *d) 381 { 382 } 383 384 static void ks_pcie_unmask_intx_irq(struct irq_data *d) 385 { 386 } 387 388 static struct irq_chip ks_pcie_intx_irq_chip = { 389 .name = "Keystone-PCI-INTX-IRQ", 390 .irq_ack = ks_pcie_ack_intx_irq, 391 .irq_mask = ks_pcie_mask_intx_irq, 392 .irq_unmask = ks_pcie_unmask_intx_irq, 393 }; 394 395 static int ks_pcie_init_intx_irq_map(struct irq_domain *d, 396 unsigned int irq, irq_hw_number_t hw_irq) 397 { 398 irq_set_chip_and_handler(irq, &ks_pcie_intx_irq_chip, 399 handle_level_irq); 400 irq_set_chip_data(irq, d->host_data); 401 402 return 0; 403 } 404 405 static const struct irq_domain_ops ks_pcie_intx_irq_domain_ops = { 406 .map = ks_pcie_init_intx_irq_map, 407 .xlate = irq_domain_xlate_onetwocell, 408 }; 409 410 static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 411 { 412 u32 val; 413 u32 num_viewport = ks_pcie->num_viewport; 414 struct dw_pcie *pci = ks_pcie->pci; 415 struct dw_pcie_rp *pp = &pci->pp; 416 struct resource_entry *entry; 417 struct resource *mem; 418 u64 start, end; 419 int i; 420 421 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); 422 if (!entry) 423 return -ENODEV; 424 425 mem = entry->res; 426 start = mem->start; 427 end = mem->end; 428 429 /* Disable BARs for inbound access */ 430 ks_pcie_set_dbi_mode(ks_pcie); 431 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 432 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 433 ks_pcie_clear_dbi_mode(ks_pcie); 434 435 if (ks_pcie->is_am6) 436 return 0; 437 438 val = ilog2(OB_WIN_SIZE); 439 ks_pcie_app_writel(ks_pcie, OB_SIZE, val); 440 441 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 442 for (i = 0; i < num_viewport && (start < end); i++) { 443 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), 444 lower_32_bits(start) | OB_ENABLEN); 445 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 446 upper_32_bits(start)); 447 start += OB_WIN_SIZE * SZ_1M; 448 } 449 450 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 451 val |= OB_XLAT_EN_VAL; 452 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 453 454 return 0; 455 } 456 457 static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, 458 unsigned int devfn, int where) 459 { 460 struct dw_pcie_rp *pp = bus->sysdata; 461 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 462 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 463 u32 reg; 464 465 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 466 CFG_FUNC(PCI_FUNC(devfn)); 467 if (!pci_is_root_bus(bus->parent)) 468 reg |= CFG_TYPE1; 469 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 470 471 return pp->va_cfg0_base + where; 472 } 473 474 static struct pci_ops ks_child_pcie_ops = { 475 .map_bus = ks_pcie_other_map_bus, 476 .read = pci_generic_config_read, 477 .write = pci_generic_config_write, 478 }; 479 480 static struct pci_ops ks_pcie_ops = { 481 .map_bus = dw_pcie_own_conf_map_bus, 482 .read = pci_generic_config_read, 483 .write = pci_generic_config_write, 484 }; 485 486 /** 487 * ks_pcie_link_up() - Check if link up 488 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host 489 * controller driver information. 490 */ 491 static int ks_pcie_link_up(struct dw_pcie *pci) 492 { 493 u32 val; 494 495 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); 496 val &= PORT_LOGIC_LTSSM_STATE_MASK; 497 return (val == PORT_LOGIC_LTSSM_STATE_L0); 498 } 499 500 static void ks_pcie_stop_link(struct dw_pcie *pci) 501 { 502 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 503 u32 val; 504 505 /* Disable Link training */ 506 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 507 val &= ~LTSSM_EN_VAL; 508 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 509 } 510 511 static int ks_pcie_start_link(struct dw_pcie *pci) 512 { 513 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 514 u32 val; 515 516 /* Initiate Link Training */ 517 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 518 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); 519 520 return 0; 521 } 522 523 static void ks_pcie_quirk(struct pci_dev *dev) 524 { 525 struct pci_bus *bus = dev->bus; 526 struct keystone_pcie *ks_pcie; 527 struct device *bridge_dev; 528 struct pci_dev *bridge; 529 u32 val; 530 531 static const struct pci_device_id rc_pci_devids[] = { 532 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 533 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 534 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), 535 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 536 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 537 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 538 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), 539 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 540 { 0, }, 541 }; 542 static const struct pci_device_id am6_pci_devids[] = { 543 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), 544 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 545 { 0, }, 546 }; 547 548 if (pci_is_root_bus(bus)) 549 bridge = dev; 550 551 /* look for the host bridge */ 552 while (!pci_is_root_bus(bus)) { 553 bridge = bus->self; 554 bus = bus->parent; 555 } 556 557 if (!bridge) 558 return; 559 560 /* 561 * Keystone PCI controller has a h/w limitation of 562 * 256 bytes maximum read request size. It can't handle 563 * anything higher than this. So force this limit on 564 * all downstream devices. 565 */ 566 if (pci_match_id(rc_pci_devids, bridge)) { 567 if (pcie_get_readrq(dev) > 256) { 568 dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); 569 pcie_set_readrq(dev, 256); 570 } 571 } 572 573 /* 574 * Memory transactions fail with PCI controller in AM654 PG1.0 575 * when MRRS is set to more than 128 bytes. Force the MRRS to 576 * 128 bytes in all downstream devices. 577 */ 578 if (pci_match_id(am6_pci_devids, bridge)) { 579 bridge_dev = pci_get_host_bridge_device(dev); 580 if (!bridge_dev && !bridge_dev->parent) 581 return; 582 583 ks_pcie = dev_get_drvdata(bridge_dev->parent); 584 if (!ks_pcie) 585 return; 586 587 val = ks_pcie_app_readl(ks_pcie, PID); 588 val &= RTL; 589 val >>= RTL_SHIFT; 590 if (val != AM6_PCI_PG1_RTL_VER) 591 return; 592 593 if (pcie_get_readrq(dev) > 128) { 594 dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); 595 pcie_set_readrq(dev, 128); 596 } 597 } 598 } 599 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); 600 601 static void ks_pcie_msi_irq_handler(struct irq_desc *desc) 602 { 603 unsigned int irq = desc->irq_data.hwirq; 604 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 605 u32 offset = irq - ks_pcie->msi_host_irq; 606 struct dw_pcie *pci = ks_pcie->pci; 607 struct dw_pcie_rp *pp = &pci->pp; 608 struct device *dev = pci->dev; 609 struct irq_chip *chip = irq_desc_get_chip(desc); 610 u32 vector, reg, pos; 611 612 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 613 614 /* 615 * The chained irq handler installation would have replaced normal 616 * interrupt driver handler so we need to take care of mask/unmask and 617 * ack operation. 618 */ 619 chained_irq_enter(chip, desc); 620 621 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); 622 /* 623 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit 624 * shows 1, 9, 17, 25 and so forth 625 */ 626 for (pos = 0; pos < 4; pos++) { 627 if (!(reg & BIT(pos))) 628 continue; 629 630 vector = offset + (pos << 3); 631 dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector); 632 generic_handle_domain_irq(pp->irq_domain, vector); 633 } 634 635 chained_irq_exit(chip, desc); 636 } 637 638 /** 639 * ks_pcie_intx_irq_handler() - Handle INTX interrupt 640 * @desc: Pointer to irq descriptor 641 * 642 * Traverse through pending INTX interrupts and invoke handler for each. Also 643 * takes care of interrupt controller level mask/ack operation. 644 */ 645 static void ks_pcie_intx_irq_handler(struct irq_desc *desc) 646 { 647 unsigned int irq = irq_desc_get_irq(desc); 648 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 649 struct dw_pcie *pci = ks_pcie->pci; 650 struct device *dev = pci->dev; 651 u32 irq_offset = irq - ks_pcie->intx_host_irqs[0]; 652 struct irq_chip *chip = irq_desc_get_chip(desc); 653 654 dev_dbg(dev, ": Handling INTX irq %d\n", irq); 655 656 /* 657 * The chained irq handler installation would have replaced normal 658 * interrupt driver handler so we need to take care of mask/unmask and 659 * ack operation. 660 */ 661 chained_irq_enter(chip, desc); 662 ks_pcie_handle_intx_irq(ks_pcie, irq_offset); 663 chained_irq_exit(chip, desc); 664 } 665 666 static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) 667 { 668 struct device *dev = ks_pcie->pci->dev; 669 struct device_node *np = ks_pcie->np; 670 struct device_node *intc_np; 671 struct irq_data *irq_data; 672 int irq_count, irq, ret, i; 673 674 if (!IS_ENABLED(CONFIG_PCI_MSI)) 675 return 0; 676 677 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); 678 if (!intc_np) { 679 if (ks_pcie->is_am6) 680 return 0; 681 dev_warn(dev, "msi-interrupt-controller node is absent\n"); 682 return -EINVAL; 683 } 684 685 irq_count = of_irq_count(intc_np); 686 if (!irq_count) { 687 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); 688 ret = -EINVAL; 689 goto err; 690 } 691 692 for (i = 0; i < irq_count; i++) { 693 irq = irq_of_parse_and_map(intc_np, i); 694 if (!irq) { 695 ret = -EINVAL; 696 goto err; 697 } 698 699 if (!ks_pcie->msi_host_irq) { 700 irq_data = irq_get_irq_data(irq); 701 if (!irq_data) { 702 ret = -EINVAL; 703 goto err; 704 } 705 ks_pcie->msi_host_irq = irq_data->hwirq; 706 } 707 708 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, 709 ks_pcie); 710 } 711 712 of_node_put(intc_np); 713 return 0; 714 715 err: 716 of_node_put(intc_np); 717 return ret; 718 } 719 720 static int ks_pcie_config_intx_irq(struct keystone_pcie *ks_pcie) 721 { 722 struct device *dev = ks_pcie->pci->dev; 723 struct irq_domain *intx_irq_domain; 724 struct device_node *np = ks_pcie->np; 725 struct device_node *intc_np; 726 int irq_count, irq, ret = 0, i; 727 728 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); 729 if (!intc_np) { 730 /* 731 * Since INTX interrupts are modeled as edge-interrupts in 732 * AM6, keep it disabled for now. 733 */ 734 if (ks_pcie->is_am6) 735 return 0; 736 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); 737 return -EINVAL; 738 } 739 740 irq_count = of_irq_count(intc_np); 741 if (!irq_count) { 742 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); 743 ret = -EINVAL; 744 goto err; 745 } 746 747 for (i = 0; i < irq_count; i++) { 748 irq = irq_of_parse_and_map(intc_np, i); 749 if (!irq) { 750 ret = -EINVAL; 751 goto err; 752 } 753 ks_pcie->intx_host_irqs[i] = irq; 754 755 irq_set_chained_handler_and_data(irq, 756 ks_pcie_intx_irq_handler, 757 ks_pcie); 758 } 759 760 intx_irq_domain = irq_domain_add_linear(intc_np, PCI_NUM_INTX, 761 &ks_pcie_intx_irq_domain_ops, NULL); 762 if (!intx_irq_domain) { 763 dev_err(dev, "Failed to add irq domain for INTX irqs\n"); 764 ret = -EINVAL; 765 goto err; 766 } 767 ks_pcie->intx_irq_domain = intx_irq_domain; 768 769 for (i = 0; i < PCI_NUM_INTX; i++) 770 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); 771 772 err: 773 of_node_put(intc_np); 774 return ret; 775 } 776 777 #ifdef CONFIG_ARM 778 /* 779 * When a PCI device does not exist during config cycles, keystone host 780 * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE). 781 * This handler always returns 0 for this kind of fault. 782 */ 783 static int ks_pcie_fault(unsigned long addr, unsigned int fsr, 784 struct pt_regs *regs) 785 { 786 unsigned long instr = *(unsigned long *) instruction_pointer(regs); 787 788 if ((instr & 0x0e100090) == 0x00100090) { 789 int reg = (instr >> 12) & 15; 790 791 regs->uregs[reg] = -1; 792 regs->ARM_pc += 4; 793 } 794 795 return 0; 796 } 797 #endif 798 799 static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) 800 { 801 int ret; 802 unsigned int id; 803 struct regmap *devctrl_regs; 804 struct dw_pcie *pci = ks_pcie->pci; 805 struct device *dev = pci->dev; 806 struct device_node *np = dev->of_node; 807 struct of_phandle_args args; 808 unsigned int offset = 0; 809 810 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); 811 if (IS_ERR(devctrl_regs)) 812 return PTR_ERR(devctrl_regs); 813 814 /* Do not error out to maintain old DT compatibility */ 815 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); 816 if (!ret) 817 offset = args.args[0]; 818 819 ret = regmap_read(devctrl_regs, offset, &id); 820 if (ret) 821 return ret; 822 823 dw_pcie_dbi_ro_wr_en(pci); 824 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); 825 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); 826 dw_pcie_dbi_ro_wr_dis(pci); 827 828 return 0; 829 } 830 831 static int __init ks_pcie_host_init(struct dw_pcie_rp *pp) 832 { 833 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 834 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 835 int ret; 836 837 pp->bridge->ops = &ks_pcie_ops; 838 if (!ks_pcie->is_am6) 839 pp->bridge->child_ops = &ks_child_pcie_ops; 840 841 ret = ks_pcie_config_intx_irq(ks_pcie); 842 if (ret) 843 return ret; 844 845 ret = ks_pcie_config_msi_irq(ks_pcie); 846 if (ret) 847 return ret; 848 849 ks_pcie_stop_link(pci); 850 ret = ks_pcie_setup_rc_app_regs(ks_pcie); 851 if (ret) 852 return ret; 853 854 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 855 pci->dbi_base + PCI_IO_BASE); 856 857 ret = ks_pcie_init_id(ks_pcie); 858 if (ret < 0) 859 return ret; 860 861 #ifdef CONFIG_ARM 862 /* 863 * PCIe access errors that result into OCP errors are caught by ARM as 864 * "External aborts" 865 */ 866 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, 867 "Asynchronous external abort"); 868 #endif 869 870 return 0; 871 } 872 873 static const struct dw_pcie_host_ops ks_pcie_host_ops = { 874 .init = ks_pcie_host_init, 875 .msi_init = ks_pcie_msi_host_init, 876 }; 877 878 static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 879 .init = ks_pcie_host_init, 880 }; 881 882 static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) 883 { 884 struct keystone_pcie *ks_pcie = priv; 885 886 return ks_pcie_handle_error_irq(ks_pcie); 887 } 888 889 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, 890 u32 reg, size_t size, u32 val) 891 { 892 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 893 894 ks_pcie_set_dbi_mode(ks_pcie); 895 dw_pcie_write(base + reg, size, val); 896 ks_pcie_clear_dbi_mode(ks_pcie); 897 } 898 899 static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { 900 .start_link = ks_pcie_start_link, 901 .stop_link = ks_pcie_stop_link, 902 .link_up = ks_pcie_link_up, 903 .write_dbi2 = ks_pcie_am654_write_dbi2, 904 }; 905 906 static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) 907 { 908 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 909 int flags; 910 911 ep->page_size = AM654_WIN_SIZE; 912 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; 913 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); 914 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); 915 } 916 917 static void ks_pcie_am654_raise_intx_irq(struct keystone_pcie *ks_pcie) 918 { 919 struct dw_pcie *pci = ks_pcie->pci; 920 u8 int_pin; 921 922 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); 923 if (int_pin == 0 || int_pin > 4) 924 return; 925 926 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), 927 INT_ENABLE); 928 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); 929 mdelay(1); 930 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); 931 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), 932 INT_ENABLE); 933 } 934 935 static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 936 unsigned int type, u16 interrupt_num) 937 { 938 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 939 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 940 941 switch (type) { 942 case PCI_IRQ_INTX: 943 ks_pcie_am654_raise_intx_irq(ks_pcie); 944 break; 945 case PCI_IRQ_MSI: 946 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 947 break; 948 case PCI_IRQ_MSIX: 949 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 950 break; 951 default: 952 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 953 return -EINVAL; 954 } 955 956 return 0; 957 } 958 959 static const struct pci_epc_features ks_pcie_am654_epc_features = { 960 .linkup_notifier = false, 961 .msi_capable = true, 962 .msix_capable = true, 963 .bar[BAR_0] = { .type = BAR_RESERVED, }, 964 .bar[BAR_1] = { .type = BAR_RESERVED, }, 965 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, 966 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, 967 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256, }, 968 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, 969 .align = SZ_1M, 970 }; 971 972 static const struct pci_epc_features* 973 ks_pcie_am654_get_features(struct dw_pcie_ep *ep) 974 { 975 return &ks_pcie_am654_epc_features; 976 } 977 978 static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { 979 .init = ks_pcie_am654_ep_init, 980 .raise_irq = ks_pcie_am654_raise_irq, 981 .get_features = &ks_pcie_am654_get_features, 982 }; 983 984 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 985 { 986 int num_lanes = ks_pcie->num_lanes; 987 988 while (num_lanes--) { 989 phy_power_off(ks_pcie->phy[num_lanes]); 990 phy_exit(ks_pcie->phy[num_lanes]); 991 } 992 } 993 994 static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) 995 { 996 int i; 997 int ret; 998 int num_lanes = ks_pcie->num_lanes; 999 1000 for (i = 0; i < num_lanes; i++) { 1001 ret = phy_reset(ks_pcie->phy[i]); 1002 if (ret < 0) 1003 goto err_phy; 1004 1005 ret = phy_init(ks_pcie->phy[i]); 1006 if (ret < 0) 1007 goto err_phy; 1008 1009 ret = phy_power_on(ks_pcie->phy[i]); 1010 if (ret < 0) { 1011 phy_exit(ks_pcie->phy[i]); 1012 goto err_phy; 1013 } 1014 } 1015 1016 return 0; 1017 1018 err_phy: 1019 while (--i >= 0) { 1020 phy_power_off(ks_pcie->phy[i]); 1021 phy_exit(ks_pcie->phy[i]); 1022 } 1023 1024 return ret; 1025 } 1026 1027 static int ks_pcie_set_mode(struct device *dev) 1028 { 1029 struct device_node *np = dev->of_node; 1030 struct of_phandle_args args; 1031 unsigned int offset = 0; 1032 struct regmap *syscon; 1033 u32 val; 1034 u32 mask; 1035 int ret = 0; 1036 1037 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1038 if (IS_ERR(syscon)) 1039 return 0; 1040 1041 /* Do not error out to maintain old DT compatibility */ 1042 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1043 if (!ret) 1044 offset = args.args[0]; 1045 1046 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; 1047 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; 1048 1049 ret = regmap_update_bits(syscon, offset, mask, val); 1050 if (ret) { 1051 dev_err(dev, "failed to set pcie mode\n"); 1052 return ret; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int ks_pcie_am654_set_mode(struct device *dev, 1059 enum dw_pcie_device_mode mode) 1060 { 1061 struct device_node *np = dev->of_node; 1062 struct of_phandle_args args; 1063 unsigned int offset = 0; 1064 struct regmap *syscon; 1065 u32 val; 1066 u32 mask; 1067 int ret = 0; 1068 1069 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1070 if (IS_ERR(syscon)) 1071 return 0; 1072 1073 /* Do not error out to maintain old DT compatibility */ 1074 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1075 if (!ret) 1076 offset = args.args[0]; 1077 1078 mask = AM654_PCIE_DEV_TYPE_MASK; 1079 1080 switch (mode) { 1081 case DW_PCIE_RC_TYPE: 1082 val = RC; 1083 break; 1084 case DW_PCIE_EP_TYPE: 1085 val = EP; 1086 break; 1087 default: 1088 dev_err(dev, "INVALID device type %d\n", mode); 1089 return -EINVAL; 1090 } 1091 1092 ret = regmap_update_bits(syscon, offset, mask, val); 1093 if (ret) { 1094 dev_err(dev, "failed to set pcie mode\n"); 1095 return ret; 1096 } 1097 1098 return 0; 1099 } 1100 1101 static const struct ks_pcie_of_data ks_pcie_rc_of_data = { 1102 .host_ops = &ks_pcie_host_ops, 1103 .version = DW_PCIE_VER_365A, 1104 }; 1105 1106 static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { 1107 .host_ops = &ks_pcie_am654_host_ops, 1108 .mode = DW_PCIE_RC_TYPE, 1109 .version = DW_PCIE_VER_490A, 1110 }; 1111 1112 static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { 1113 .ep_ops = &ks_pcie_am654_ep_ops, 1114 .mode = DW_PCIE_EP_TYPE, 1115 .version = DW_PCIE_VER_490A, 1116 }; 1117 1118 static const struct of_device_id ks_pcie_of_match[] = { 1119 { 1120 .type = "pci", 1121 .data = &ks_pcie_rc_of_data, 1122 .compatible = "ti,keystone-pcie", 1123 }, 1124 { 1125 .data = &ks_pcie_am654_rc_of_data, 1126 .compatible = "ti,am654-pcie-rc", 1127 }, 1128 { 1129 .data = &ks_pcie_am654_ep_of_data, 1130 .compatible = "ti,am654-pcie-ep", 1131 }, 1132 { }, 1133 }; 1134 1135 static int ks_pcie_probe(struct platform_device *pdev) 1136 { 1137 const struct dw_pcie_host_ops *host_ops; 1138 const struct dw_pcie_ep_ops *ep_ops; 1139 struct device *dev = &pdev->dev; 1140 struct device_node *np = dev->of_node; 1141 const struct ks_pcie_of_data *data; 1142 enum dw_pcie_device_mode mode; 1143 struct dw_pcie *pci; 1144 struct keystone_pcie *ks_pcie; 1145 struct device_link **link; 1146 struct gpio_desc *gpiod; 1147 struct resource *res; 1148 void __iomem *base; 1149 u32 num_viewport; 1150 struct phy **phy; 1151 u32 num_lanes; 1152 char name[10]; 1153 u32 version; 1154 int ret; 1155 int irq; 1156 int i; 1157 1158 data = of_device_get_match_data(dev); 1159 if (!data) 1160 return -EINVAL; 1161 1162 version = data->version; 1163 host_ops = data->host_ops; 1164 ep_ops = data->ep_ops; 1165 mode = data->mode; 1166 1167 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 1168 if (!ks_pcie) 1169 return -ENOMEM; 1170 1171 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1172 if (!pci) 1173 return -ENOMEM; 1174 1175 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); 1176 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 1177 if (IS_ERR(ks_pcie->va_app_base)) 1178 return PTR_ERR(ks_pcie->va_app_base); 1179 1180 ks_pcie->app = *res; 1181 1182 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); 1183 base = devm_pci_remap_cfg_resource(dev, res); 1184 if (IS_ERR(base)) 1185 return PTR_ERR(base); 1186 1187 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) 1188 ks_pcie->is_am6 = true; 1189 1190 pci->dbi_base = base; 1191 pci->dbi_base2 = base; 1192 pci->dev = dev; 1193 pci->ops = &ks_pcie_dw_pcie_ops; 1194 pci->version = version; 1195 1196 irq = platform_get_irq(pdev, 0); 1197 if (irq < 0) 1198 return irq; 1199 1200 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, 1201 "ks-pcie-error-irq", ks_pcie); 1202 if (ret < 0) { 1203 dev_err(dev, "failed to request error IRQ %d\n", 1204 irq); 1205 return ret; 1206 } 1207 1208 ret = of_property_read_u32(np, "num-lanes", &num_lanes); 1209 if (ret) 1210 num_lanes = 1; 1211 1212 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); 1213 if (!phy) 1214 return -ENOMEM; 1215 1216 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); 1217 if (!link) 1218 return -ENOMEM; 1219 1220 for (i = 0; i < num_lanes; i++) { 1221 snprintf(name, sizeof(name), "pcie-phy%d", i); 1222 phy[i] = devm_phy_optional_get(dev, name); 1223 if (IS_ERR(phy[i])) { 1224 ret = PTR_ERR(phy[i]); 1225 goto err_link; 1226 } 1227 1228 if (!phy[i]) 1229 continue; 1230 1231 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 1232 if (!link[i]) { 1233 ret = -EINVAL; 1234 goto err_link; 1235 } 1236 } 1237 1238 ks_pcie->np = np; 1239 ks_pcie->pci = pci; 1240 ks_pcie->link = link; 1241 ks_pcie->num_lanes = num_lanes; 1242 ks_pcie->phy = phy; 1243 1244 gpiod = devm_gpiod_get_optional(dev, "reset", 1245 GPIOD_OUT_LOW); 1246 if (IS_ERR(gpiod)) { 1247 ret = PTR_ERR(gpiod); 1248 if (ret != -EPROBE_DEFER) 1249 dev_err(dev, "Failed to get reset GPIO\n"); 1250 goto err_link; 1251 } 1252 1253 /* Obtain references to the PHYs */ 1254 for (i = 0; i < num_lanes; i++) 1255 phy_pm_runtime_get_sync(ks_pcie->phy[i]); 1256 1257 ret = ks_pcie_enable_phy(ks_pcie); 1258 1259 /* Release references to the PHYs */ 1260 for (i = 0; i < num_lanes; i++) 1261 phy_pm_runtime_put_sync(ks_pcie->phy[i]); 1262 1263 if (ret) { 1264 dev_err(dev, "failed to enable phy\n"); 1265 goto err_link; 1266 } 1267 1268 platform_set_drvdata(pdev, ks_pcie); 1269 pm_runtime_enable(dev); 1270 ret = pm_runtime_get_sync(dev); 1271 if (ret < 0) { 1272 dev_err(dev, "pm_runtime_get_sync failed\n"); 1273 goto err_get_sync; 1274 } 1275 1276 if (dw_pcie_ver_is_ge(pci, 480A)) 1277 ret = ks_pcie_am654_set_mode(dev, mode); 1278 else 1279 ret = ks_pcie_set_mode(dev); 1280 if (ret < 0) 1281 goto err_get_sync; 1282 1283 switch (mode) { 1284 case DW_PCIE_RC_TYPE: 1285 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { 1286 ret = -ENODEV; 1287 goto err_get_sync; 1288 } 1289 1290 ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1291 if (ret < 0) { 1292 dev_err(dev, "unable to read *num-viewport* property\n"); 1293 goto err_get_sync; 1294 } 1295 1296 /* 1297 * "Power Sequencing and Reset Signal Timings" table in 1298 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 1299 * indicates PERST# should be deasserted after minimum of 100us 1300 * once REFCLK is stable. The REFCLK to the connector in RC 1301 * mode is selected while enabling the PHY. So deassert PERST# 1302 * after 100 us. 1303 */ 1304 if (gpiod) { 1305 usleep_range(100, 200); 1306 gpiod_set_value_cansleep(gpiod, 1); 1307 } 1308 1309 ks_pcie->num_viewport = num_viewport; 1310 pci->pp.ops = host_ops; 1311 ret = dw_pcie_host_init(&pci->pp); 1312 if (ret < 0) 1313 goto err_get_sync; 1314 break; 1315 case DW_PCIE_EP_TYPE: 1316 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { 1317 ret = -ENODEV; 1318 goto err_get_sync; 1319 } 1320 1321 pci->ep.ops = ep_ops; 1322 ret = dw_pcie_ep_init(&pci->ep); 1323 if (ret < 0) 1324 goto err_get_sync; 1325 1326 ret = dw_pcie_ep_init_registers(&pci->ep); 1327 if (ret) { 1328 dev_err(dev, "Failed to initialize DWC endpoint registers\n"); 1329 goto err_ep_init; 1330 } 1331 1332 pci_epc_init_notify(pci->ep.epc); 1333 1334 break; 1335 default: 1336 dev_err(dev, "INVALID device type %d\n", mode); 1337 } 1338 1339 ks_pcie_enable_error_irq(ks_pcie); 1340 1341 return 0; 1342 1343 err_ep_init: 1344 dw_pcie_ep_deinit(&pci->ep); 1345 err_get_sync: 1346 pm_runtime_put(dev); 1347 pm_runtime_disable(dev); 1348 ks_pcie_disable_phy(ks_pcie); 1349 1350 err_link: 1351 while (--i >= 0 && link[i]) 1352 device_link_del(link[i]); 1353 1354 return ret; 1355 } 1356 1357 static void ks_pcie_remove(struct platform_device *pdev) 1358 { 1359 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 1360 struct device_link **link = ks_pcie->link; 1361 int num_lanes = ks_pcie->num_lanes; 1362 struct device *dev = &pdev->dev; 1363 1364 pm_runtime_put(dev); 1365 pm_runtime_disable(dev); 1366 ks_pcie_disable_phy(ks_pcie); 1367 while (num_lanes--) 1368 device_link_del(link[num_lanes]); 1369 } 1370 1371 static struct platform_driver ks_pcie_driver = { 1372 .probe = ks_pcie_probe, 1373 .remove_new = ks_pcie_remove, 1374 .driver = { 1375 .name = "keystone-pcie", 1376 .of_match_table = ks_pcie_of_match, 1377 }, 1378 }; 1379 builtin_platform_driver(ks_pcie_driver); 1380