1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 9#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 11#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 clock-frequency = <76800000>; 36 #clock-cells = <0>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 clock-frequency = <32000>; 42 #clock-cells = <0>; 43 }; 44 45 bi_tcxo_div2: bi-tcxo-div2-clk { 46 compatible = "fixed-factor-clock"; 47 #clock-cells = <0>; 48 49 clocks = <&rpmhcc RPMH_CXO_CLK>; 50 clock-mult = <1>; 51 clock-div = <2>; 52 }; 53 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 55 compatible = "fixed-factor-clock"; 56 #clock-cells = <0>; 57 58 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 59 clock-mult = <1>; 60 clock-div = <2>; 61 }; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 CPU0: cpu@0 { 69 device_type = "cpu"; 70 compatible = "qcom,oryon"; 71 reg = <0x0 0x0>; 72 enable-method = "psci"; 73 next-level-cache = <&L2_0>; 74 power-domains = <&CPU_PD0>; 75 power-domain-names = "psci"; 76 cpu-idle-states = <&CLUSTER_C4>; 77 78 L2_0: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 }; 83 }; 84 85 CPU1: cpu@100 { 86 device_type = "cpu"; 87 compatible = "qcom,oryon"; 88 reg = <0x0 0x100>; 89 enable-method = "psci"; 90 next-level-cache = <&L2_0>; 91 power-domains = <&CPU_PD1>; 92 power-domain-names = "psci"; 93 cpu-idle-states = <&CLUSTER_C4>; 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "qcom,oryon"; 99 reg = <0x0 0x200>; 100 enable-method = "psci"; 101 next-level-cache = <&L2_0>; 102 power-domains = <&CPU_PD2>; 103 power-domain-names = "psci"; 104 cpu-idle-states = <&CLUSTER_C4>; 105 }; 106 107 CPU3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "qcom,oryon"; 110 reg = <0x0 0x300>; 111 enable-method = "psci"; 112 next-level-cache = <&L2_0>; 113 power-domains = <&CPU_PD3>; 114 power-domain-names = "psci"; 115 cpu-idle-states = <&CLUSTER_C4>; 116 }; 117 118 CPU4: cpu@10000 { 119 device_type = "cpu"; 120 compatible = "qcom,oryon"; 121 reg = <0x0 0x10000>; 122 enable-method = "psci"; 123 next-level-cache = <&L2_1>; 124 power-domains = <&CPU_PD4>; 125 power-domain-names = "psci"; 126 cpu-idle-states = <&CLUSTER_C4>; 127 128 L2_1: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 }; 133 }; 134 135 CPU5: cpu@10100 { 136 device_type = "cpu"; 137 compatible = "qcom,oryon"; 138 reg = <0x0 0x10100>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_1>; 141 power-domains = <&CPU_PD5>; 142 power-domain-names = "psci"; 143 cpu-idle-states = <&CLUSTER_C4>; 144 }; 145 146 CPU6: cpu@10200 { 147 device_type = "cpu"; 148 compatible = "qcom,oryon"; 149 reg = <0x0 0x10200>; 150 enable-method = "psci"; 151 next-level-cache = <&L2_1>; 152 power-domains = <&CPU_PD6>; 153 power-domain-names = "psci"; 154 cpu-idle-states = <&CLUSTER_C4>; 155 }; 156 157 CPU7: cpu@10300 { 158 device_type = "cpu"; 159 compatible = "qcom,oryon"; 160 reg = <0x0 0x10300>; 161 enable-method = "psci"; 162 next-level-cache = <&L2_1>; 163 power-domains = <&CPU_PD7>; 164 power-domain-names = "psci"; 165 cpu-idle-states = <&CLUSTER_C4>; 166 }; 167 168 CPU8: cpu@20000 { 169 device_type = "cpu"; 170 compatible = "qcom,oryon"; 171 reg = <0x0 0x20000>; 172 enable-method = "psci"; 173 next-level-cache = <&L2_2>; 174 power-domains = <&CPU_PD8>; 175 power-domain-names = "psci"; 176 cpu-idle-states = <&CLUSTER_C4>; 177 178 L2_2: l2-cache { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-unified; 182 }; 183 }; 184 185 CPU9: cpu@20100 { 186 device_type = "cpu"; 187 compatible = "qcom,oryon"; 188 reg = <0x0 0x20100>; 189 enable-method = "psci"; 190 next-level-cache = <&L2_2>; 191 power-domains = <&CPU_PD9>; 192 power-domain-names = "psci"; 193 cpu-idle-states = <&CLUSTER_C4>; 194 }; 195 196 CPU10: cpu@20200 { 197 device_type = "cpu"; 198 compatible = "qcom,oryon"; 199 reg = <0x0 0x20200>; 200 enable-method = "psci"; 201 next-level-cache = <&L2_2>; 202 power-domains = <&CPU_PD10>; 203 power-domain-names = "psci"; 204 cpu-idle-states = <&CLUSTER_C4>; 205 }; 206 207 CPU11: cpu@20300 { 208 device_type = "cpu"; 209 compatible = "qcom,oryon"; 210 reg = <0x0 0x20300>; 211 enable-method = "psci"; 212 next-level-cache = <&L2_2>; 213 power-domains = <&CPU_PD11>; 214 power-domain-names = "psci"; 215 cpu-idle-states = <&CLUSTER_C4>; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&CPU0>; 222 }; 223 224 core1 { 225 cpu = <&CPU1>; 226 }; 227 228 core2 { 229 cpu = <&CPU2>; 230 }; 231 232 core3 { 233 cpu = <&CPU3>; 234 }; 235 }; 236 237 cluster1 { 238 core0 { 239 cpu = <&CPU4>; 240 }; 241 242 core1 { 243 cpu = <&CPU5>; 244 }; 245 246 core2 { 247 cpu = <&CPU6>; 248 }; 249 250 core3 { 251 cpu = <&CPU7>; 252 }; 253 }; 254 255 cluster2 { 256 core0 { 257 cpu = <&CPU8>; 258 }; 259 260 core1 { 261 cpu = <&CPU9>; 262 }; 263 264 core2 { 265 cpu = <&CPU10>; 266 }; 267 268 core3 { 269 cpu = <&CPU11>; 270 }; 271 }; 272 }; 273 274 idle-states { 275 entry-method = "psci"; 276 277 CLUSTER_C4: cpu-sleep-0 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "ret"; 280 arm,psci-suspend-param = <0x00000004>; 281 entry-latency-us = <180>; 282 exit-latency-us = <320>; 283 min-residency-us = <1000>; 284 }; 285 }; 286 287 domain-idle-states { 288 CLUSTER_CL4: cluster-sleep-0 { 289 compatible = "domain-idle-state"; 290 idle-state-name = "l2-ret"; 291 arm,psci-suspend-param = <0x01000044>; 292 entry-latency-us = <350>; 293 exit-latency-us = <500>; 294 min-residency-us = <2500>; 295 }; 296 297 CLUSTER_CL5: cluster-sleep-1 { 298 compatible = "domain-idle-state"; 299 idle-state-name = "ret-pll-off"; 300 arm,psci-suspend-param = <0x01000054>; 301 entry-latency-us = <2200>; 302 exit-latency-us = <2500>; 303 min-residency-us = <7000>; 304 }; 305 }; 306 }; 307 308 firmware { 309 scm: scm { 310 compatible = "qcom,scm-x1e80100", "qcom,scm"; 311 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 313 }; 314 }; 315 316 clk_virt: interconnect-0 { 317 compatible = "qcom,x1e80100-clk-virt"; 318 #interconnect-cells = <2>; 319 qcom,bcm-voters = <&apps_bcm_voter>; 320 }; 321 322 mc_virt: interconnect-1 { 323 compatible = "qcom,x1e80100-mc-virt"; 324 #interconnect-cells = <2>; 325 qcom,bcm-voters = <&apps_bcm_voter>; 326 }; 327 328 memory@80000000 { 329 device_type = "memory"; 330 /* We expect the bootloader to fill in the size */ 331 reg = <0 0x80000000 0 0>; 332 }; 333 334 pmu { 335 compatible = "arm,armv8-pmuv3"; 336 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 337 }; 338 339 psci { 340 compatible = "arm,psci-1.0"; 341 method = "smc"; 342 343 CPU_PD0: power-domain-cpu0 { 344 #power-domain-cells = <0>; 345 power-domains = <&CLUSTER_PD0>; 346 }; 347 348 CPU_PD1: power-domain-cpu1 { 349 #power-domain-cells = <0>; 350 power-domains = <&CLUSTER_PD0>; 351 }; 352 353 CPU_PD2: power-domain-cpu2 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD0>; 356 }; 357 358 CPU_PD3: power-domain-cpu3 { 359 #power-domain-cells = <0>; 360 power-domains = <&CLUSTER_PD0>; 361 }; 362 363 CPU_PD4: power-domain-cpu4 { 364 #power-domain-cells = <0>; 365 power-domains = <&CLUSTER_PD1>; 366 }; 367 368 CPU_PD5: power-domain-cpu5 { 369 #power-domain-cells = <0>; 370 power-domains = <&CLUSTER_PD1>; 371 }; 372 373 CPU_PD6: power-domain-cpu6 { 374 #power-domain-cells = <0>; 375 power-domains = <&CLUSTER_PD1>; 376 }; 377 378 CPU_PD7: power-domain-cpu7 { 379 #power-domain-cells = <0>; 380 power-domains = <&CLUSTER_PD1>; 381 }; 382 383 CPU_PD8: power-domain-cpu8 { 384 #power-domain-cells = <0>; 385 power-domains = <&CLUSTER_PD2>; 386 }; 387 388 CPU_PD9: power-domain-cpu9 { 389 #power-domain-cells = <0>; 390 power-domains = <&CLUSTER_PD2>; 391 }; 392 393 CPU_PD10: power-domain-cpu10 { 394 #power-domain-cells = <0>; 395 power-domains = <&CLUSTER_PD2>; 396 }; 397 398 CPU_PD11: power-domain-cpu11 { 399 #power-domain-cells = <0>; 400 power-domains = <&CLUSTER_PD2>; 401 }; 402 403 CLUSTER_PD0: power-domain-cpu-cluster0 { 404 #power-domain-cells = <0>; 405 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 406 power-domains = <&SYSTEM_PD>; 407 }; 408 409 CLUSTER_PD1: power-domain-cpu-cluster1 { 410 #power-domain-cells = <0>; 411 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 412 power-domains = <&SYSTEM_PD>; 413 }; 414 415 CLUSTER_PD2: power-domain-cpu-cluster2 { 416 #power-domain-cells = <0>; 417 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 418 power-domains = <&SYSTEM_PD>; 419 }; 420 421 SYSTEM_PD: power-domain-system { 422 #power-domain-cells = <0>; 423 /* TODO: system-wide idle states */ 424 }; 425 }; 426 427 reserved-memory { 428 #address-cells = <2>; 429 #size-cells = <2>; 430 ranges; 431 432 gunyah_hyp_mem: gunyah-hyp@80000000 { 433 reg = <0x0 0x80000000 0x0 0x800000>; 434 no-map; 435 }; 436 437 hyp_elf_package_mem: hyp-elf-package@80800000 { 438 reg = <0x0 0x80800000 0x0 0x200000>; 439 no-map; 440 }; 441 442 ncc_mem: ncc@80a00000 { 443 reg = <0x0 0x80a00000 0x0 0x400000>; 444 no-map; 445 }; 446 447 cpucp_log_mem: cpucp-log@80e00000 { 448 reg = <0x0 0x80e00000 0x0 0x40000>; 449 no-map; 450 }; 451 452 cpucp_mem: cpucp@80e40000 { 453 reg = <0x0 0x80e40000 0x0 0x540000>; 454 no-map; 455 }; 456 457 reserved-region@81380000 { 458 reg = <0x0 0x81380000 0x0 0x80000>; 459 no-map; 460 }; 461 462 tags_mem: tags-region@81400000 { 463 reg = <0x0 0x81400000 0x0 0x1a0000>; 464 no-map; 465 }; 466 467 xbl_dtlog_mem: xbl-dtlog@81a00000 { 468 reg = <0x0 0x81a00000 0x0 0x40000>; 469 no-map; 470 }; 471 472 xbl_ramdump_mem: xbl-ramdump@81a40000 { 473 reg = <0x0 0x81a40000 0x0 0x1c0000>; 474 no-map; 475 }; 476 477 aop_image_mem: aop-image@81c00000 { 478 reg = <0x0 0x81c00000 0x0 0x60000>; 479 no-map; 480 }; 481 482 aop_cmd_db_mem: aop-cmd-db@81c60000 { 483 compatible = "qcom,cmd-db"; 484 reg = <0x0 0x81c60000 0x0 0x20000>; 485 no-map; 486 }; 487 488 aop_config_mem: aop-config@81c80000 { 489 reg = <0x0 0x81c80000 0x0 0x20000>; 490 no-map; 491 }; 492 493 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 494 reg = <0x0 0x81ca0000 0x0 0x40000>; 495 no-map; 496 }; 497 498 tme_log_mem: tme-log@81ce0000 { 499 reg = <0x0 0x81ce0000 0x0 0x4000>; 500 no-map; 501 }; 502 503 uefi_log_mem: uefi-log@81ce4000 { 504 reg = <0x0 0x81ce4000 0x0 0x10000>; 505 no-map; 506 }; 507 508 secdata_apss_mem: secdata-apss@81cff000 { 509 reg = <0x0 0x81cff000 0x0 0x1000>; 510 no-map; 511 }; 512 513 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 514 reg = <0x0 0x81e00000 0x0 0x100000>; 515 no-map; 516 }; 517 518 gpu_prr_mem: gpu-prr@81f00000 { 519 reg = <0x0 0x81f00000 0x0 0x10000>; 520 no-map; 521 }; 522 523 tpm_control_mem: tpm-control@81f10000 { 524 reg = <0x0 0x81f10000 0x0 0x10000>; 525 no-map; 526 }; 527 528 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 529 reg = <0x0 0x81f20000 0x0 0x10000>; 530 no-map; 531 }; 532 533 pld_pep_mem: pld-pep@81f30000 { 534 reg = <0x0 0x81f30000 0x0 0x6000>; 535 no-map; 536 }; 537 538 pld_gmu_mem: pld-gmu@81f36000 { 539 reg = <0x0 0x81f36000 0x0 0x1000>; 540 no-map; 541 }; 542 543 pld_pdp_mem: pld-pdp@81f37000 { 544 reg = <0x0 0x81f37000 0x0 0x1000>; 545 no-map; 546 }; 547 548 tz_stat_mem: tz-stat@82700000 { 549 reg = <0x0 0x82700000 0x0 0x100000>; 550 no-map; 551 }; 552 553 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 554 reg = <0x0 0x82800000 0x0 0xc00000>; 555 no-map; 556 }; 557 558 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 559 reg = <0x0 0x84b00000 0x0 0x800000>; 560 no-map; 561 }; 562 563 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 564 reg = <0x0 0x85300000 0x0 0x80000>; 565 no-map; 566 }; 567 568 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 569 reg = <0x0 0x866c0000 0x0 0x40000>; 570 no-map; 571 }; 572 573 spss_region_mem: spss-region@86700000 { 574 reg = <0x0 0x86700000 0x0 0x400000>; 575 no-map; 576 }; 577 578 adsp_boot_mem: adsp-boot@86b00000 { 579 reg = <0x0 0x86b00000 0x0 0xc00000>; 580 no-map; 581 }; 582 583 video_mem: video@87700000 { 584 reg = <0x0 0x87700000 0x0 0x700000>; 585 no-map; 586 }; 587 588 adspslpi_mem: adspslpi@87e00000 { 589 reg = <0x0 0x87e00000 0x0 0x3a00000>; 590 no-map; 591 }; 592 593 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 594 reg = <0x0 0x8b800000 0x0 0x80000>; 595 no-map; 596 }; 597 598 cdsp_mem: cdsp@8b900000 { 599 reg = <0x0 0x8b900000 0x0 0x2000000>; 600 no-map; 601 }; 602 603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 604 reg = <0x0 0x8d900000 0x0 0x80000>; 605 no-map; 606 }; 607 608 gpu_microcode_mem: gpu-microcode@8d9fe000 { 609 reg = <0x0 0x8d9fe000 0x0 0x2000>; 610 no-map; 611 }; 612 613 cvp_mem: cvp@8da00000 { 614 reg = <0x0 0x8da00000 0x0 0x700000>; 615 no-map; 616 }; 617 618 camera_mem: camera@8e100000 { 619 reg = <0x0 0x8e100000 0x0 0x800000>; 620 no-map; 621 }; 622 623 av1_encoder_mem: av1-encoder@8e900000 { 624 reg = <0x0 0x8e900000 0x0 0x700000>; 625 no-map; 626 }; 627 628 reserved-region@8f000000 { 629 reg = <0x0 0x8f000000 0x0 0xa00000>; 630 no-map; 631 }; 632 633 wpss_mem: wpss@8fa00000 { 634 reg = <0x0 0x8fa00000 0x0 0x1900000>; 635 no-map; 636 }; 637 638 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 639 reg = <0x0 0x91300000 0x0 0x80000>; 640 no-map; 641 }; 642 643 xbl_sc_mem: xbl-sc@d8000000 { 644 reg = <0x0 0xd8000000 0x0 0x40000>; 645 no-map; 646 }; 647 648 reserved-region@d8040000 { 649 reg = <0x0 0xd8040000 0x0 0xa0000>; 650 no-map; 651 }; 652 653 qtee_mem: qtee@d80e0000 { 654 reg = <0x0 0xd80e0000 0x0 0x520000>; 655 no-map; 656 }; 657 658 ta_mem: ta@d8600000 { 659 reg = <0x0 0xd8600000 0x0 0x8a00000>; 660 no-map; 661 }; 662 663 tags_mem1: tags@e1000000 { 664 reg = <0x0 0xe1000000 0x0 0x26a0000>; 665 no-map; 666 }; 667 668 llcc_lpi_mem: llcc-lpi@ff800000 { 669 reg = <0x0 0xff800000 0x0 0x600000>; 670 no-map; 671 }; 672 673 smem_mem: smem@ffe00000 { 674 compatible = "qcom,smem"; 675 reg = <0x0 0xffe00000 0x0 0x200000>; 676 hwlocks = <&tcsr_mutex 3>; 677 no-map; 678 }; 679 }; 680 681 smp2p-adsp { 682 compatible = "qcom,smp2p"; 683 684 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 685 IPCC_MPROC_SIGNAL_SMP2P 686 IRQ_TYPE_EDGE_RISING>; 687 688 mboxes = <&ipcc IPCC_CLIENT_LPASS 689 IPCC_MPROC_SIGNAL_SMP2P>; 690 691 qcom,smem = <443>, <429>; 692 qcom,local-pid = <0>; 693 qcom,remote-pid = <2>; 694 695 smp2p_adsp_out: master-kernel { 696 qcom,entry-name = "master-kernel"; 697 #qcom,smem-state-cells = <1>; 698 }; 699 700 smp2p_adsp_in: slave-kernel { 701 qcom,entry-name = "slave-kernel"; 702 interrupt-controller; 703 #interrupt-cells = <2>; 704 }; 705 }; 706 707 smp2p-cdsp { 708 compatible = "qcom,smp2p"; 709 710 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 711 IPCC_MPROC_SIGNAL_SMP2P 712 IRQ_TYPE_EDGE_RISING>; 713 714 mboxes = <&ipcc IPCC_CLIENT_CDSP 715 IPCC_MPROC_SIGNAL_SMP2P>; 716 717 qcom,smem = <94>, <432>; 718 qcom,local-pid = <0>; 719 qcom,remote-pid = <5>; 720 721 smp2p_cdsp_out: master-kernel { 722 qcom,entry-name = "master-kernel"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 smp2p_cdsp_in: slave-kernel { 727 qcom,entry-name = "slave-kernel"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 soc: soc@0 { 734 compatible = "simple-bus"; 735 736 #address-cells = <2>; 737 #size-cells = <2>; 738 dma-ranges = <0 0 0 0 0x10 0>; 739 ranges = <0 0 0 0 0x10 0>; 740 741 gcc: clock-controller@100000 { 742 compatible = "qcom,x1e80100-gcc"; 743 reg = <0 0x00100000 0 0x200000>; 744 745 clocks = <&bi_tcxo_div2>, 746 <&sleep_clk>, 747 <0>, 748 <&pcie4_phy>, 749 <&pcie5_phy>, 750 <&pcie6a_phy>, 751 <0>, 752 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 753 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 754 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 755 756 power-domains = <&rpmhpd RPMHPD_CX>; 757 #clock-cells = <1>; 758 #reset-cells = <1>; 759 #power-domain-cells = <1>; 760 }; 761 762 ipcc: mailbox@408000 { 763 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 764 reg = <0 0x00408000 0 0x1000>; 765 766 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 767 interrupt-controller; 768 #interrupt-cells = <3>; 769 770 #mbox-cells = <2>; 771 }; 772 773 gpi_dma2: dma-controller@800000 { 774 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 775 reg = <0 0x00800000 0 0x60000>; 776 777 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 789 790 dma-channels = <12>; 791 dma-channel-mask = <0x3e>; 792 #dma-cells = <3>; 793 794 iommus = <&apps_smmu 0x436 0x0>; 795 796 status = "disabled"; 797 }; 798 799 qupv3_2: geniqup@8c0000 { 800 compatible = "qcom,geni-se-qup"; 801 reg = <0 0x008c0000 0 0x2000>; 802 803 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 804 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 805 clock-names = "m-ahb", 806 "s-ahb"; 807 808 iommus = <&apps_smmu 0x423 0x0>; 809 810 #address-cells = <2>; 811 #size-cells = <2>; 812 ranges; 813 814 status = "disabled"; 815 816 i2c16: i2c@880000 { 817 compatible = "qcom,geni-i2c"; 818 reg = <0 0x00880000 0 0x4000>; 819 820 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 821 822 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 823 clock-names = "se"; 824 825 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 826 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 827 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 828 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 829 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 830 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 831 interconnect-names = "qup-core", 832 "qup-config", 833 "qup-memory"; 834 835 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 836 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 837 dma-names = "tx", 838 "rx"; 839 840 pinctrl-0 = <&qup_i2c16_data_clk>; 841 pinctrl-names = "default"; 842 843 #address-cells = <1>; 844 #size-cells = <0>; 845 846 status = "disabled"; 847 }; 848 849 spi16: spi@880000 { 850 compatible = "qcom,geni-spi"; 851 reg = <0 0x00880000 0 0x4000>; 852 853 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 854 855 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 856 clock-names = "se"; 857 858 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 859 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 860 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 861 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 862 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 863 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 864 interconnect-names = "qup-core", 865 "qup-config", 866 "qup-memory"; 867 868 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 869 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 870 dma-names = "tx", 871 "rx"; 872 873 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 874 pinctrl-names = "default"; 875 876 #address-cells = <1>; 877 #size-cells = <0>; 878 879 status = "disabled"; 880 }; 881 882 i2c17: i2c@884000 { 883 compatible = "qcom,geni-i2c"; 884 reg = <0 0x00884000 0 0x4000>; 885 886 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 887 888 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 889 clock-names = "se"; 890 891 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 892 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 893 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 894 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 895 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 896 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 897 interconnect-names = "qup-core", 898 "qup-config", 899 "qup-memory"; 900 901 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 902 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 903 dma-names = "tx", 904 "rx"; 905 906 pinctrl-0 = <&qup_i2c17_data_clk>; 907 pinctrl-names = "default"; 908 909 #address-cells = <1>; 910 #size-cells = <0>; 911 912 status = "disabled"; 913 }; 914 915 spi17: spi@884000 { 916 compatible = "qcom,geni-spi"; 917 reg = <0 0x00884000 0 0x4000>; 918 919 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 920 921 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 922 clock-names = "se"; 923 924 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 925 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 926 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 927 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 928 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 930 interconnect-names = "qup-core", 931 "qup-config", 932 "qup-memory"; 933 934 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 935 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 936 dma-names = "tx", 937 "rx"; 938 939 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 940 pinctrl-names = "default"; 941 942 #address-cells = <1>; 943 #size-cells = <0>; 944 945 status = "disabled"; 946 }; 947 948 i2c18: i2c@888000 { 949 compatible = "qcom,geni-i2c"; 950 reg = <0 0x00888000 0 0x4000>; 951 952 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 953 954 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 955 clock-names = "se"; 956 957 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 958 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 959 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 960 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 961 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 962 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 963 interconnect-names = "qup-core", 964 "qup-config", 965 "qup-memory"; 966 967 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 968 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 969 dma-names = "tx", 970 "rx"; 971 972 pinctrl-0 = <&qup_i2c18_data_clk>; 973 pinctrl-names = "default"; 974 975 #address-cells = <1>; 976 #size-cells = <0>; 977 978 status = "disabled"; 979 }; 980 981 spi18: spi@888000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0 0x00888000 0 0x4000>; 984 985 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 986 987 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 988 clock-names = "se"; 989 990 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 991 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 993 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 994 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 996 interconnect-names = "qup-core", 997 "qup-config", 998 "qup-memory"; 999 1000 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1001 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1002 dma-names = "tx", 1003 "rx"; 1004 1005 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1006 pinctrl-names = "default"; 1007 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 1011 status = "disabled"; 1012 }; 1013 1014 i2c19: i2c@88c000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x0088c000 0 0x4000>; 1017 1018 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1019 1020 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1021 clock-names = "se"; 1022 1023 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1024 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1025 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1026 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1027 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1029 interconnect-names = "qup-core", 1030 "qup-config", 1031 "qup-memory"; 1032 1033 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1034 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1035 dma-names = "tx", 1036 "rx"; 1037 1038 pinctrl-0 = <&qup_i2c19_data_clk>; 1039 pinctrl-names = "default"; 1040 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 1044 status = "disabled"; 1045 }; 1046 1047 spi19: spi@88c000 { 1048 compatible = "qcom,geni-spi"; 1049 reg = <0 0x0088c000 0 0x4000>; 1050 1051 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1052 1053 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1054 clock-names = "se"; 1055 1056 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1057 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1058 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1059 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1060 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1062 interconnect-names = "qup-core", 1063 "qup-config", 1064 "qup-memory"; 1065 1066 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1067 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1068 dma-names = "tx", 1069 "rx"; 1070 1071 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1072 pinctrl-names = "default"; 1073 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 1077 status = "disabled"; 1078 }; 1079 1080 i2c20: i2c@890000 { 1081 compatible = "qcom,geni-i2c"; 1082 reg = <0 0x00890000 0 0x4000>; 1083 1084 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1085 1086 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1087 clock-names = "se"; 1088 1089 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1090 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1091 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1092 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1093 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1095 interconnect-names = "qup-core", 1096 "qup-config", 1097 "qup-memory"; 1098 1099 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1100 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1101 dma-names = "tx", 1102 "rx"; 1103 1104 pinctrl-0 = <&qup_i2c20_data_clk>; 1105 pinctrl-names = "default"; 1106 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 1110 status = "disabled"; 1111 }; 1112 1113 spi20: spi@890000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x00890000 0 0x4000>; 1116 1117 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1118 1119 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1120 clock-names = "se"; 1121 1122 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1123 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1124 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1125 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1126 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1128 interconnect-names = "qup-core", 1129 "qup-config", 1130 "qup-memory"; 1131 1132 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1133 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1134 dma-names = "tx", 1135 "rx"; 1136 1137 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1138 pinctrl-names = "default"; 1139 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 1143 status = "disabled"; 1144 }; 1145 1146 i2c21: i2c@894000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x00894000 0 0x4000>; 1149 1150 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1151 1152 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1153 clock-names = "se"; 1154 1155 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1156 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1157 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1158 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1159 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1160 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1161 interconnect-names = "qup-core", 1162 "qup-config", 1163 "qup-memory"; 1164 1165 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1167 dma-names = "tx", 1168 "rx"; 1169 1170 pinctrl-0 = <&qup_i2c21_data_clk>; 1171 pinctrl-names = "default"; 1172 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 1176 status = "disabled"; 1177 }; 1178 1179 spi21: spi@894000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0 0x00894000 0 0x4000>; 1182 1183 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1184 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1186 clock-names = "se"; 1187 1188 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1189 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1190 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1191 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1192 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1193 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1194 interconnect-names = "qup-core", 1195 "qup-config", 1196 "qup-memory"; 1197 1198 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1199 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1200 dma-names = "tx", 1201 "rx"; 1202 1203 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1204 pinctrl-names = "default"; 1205 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 1209 status = "disabled"; 1210 }; 1211 1212 uart21: serial@894000 { 1213 compatible = "qcom,geni-uart"; 1214 reg = <0 0x00894000 0 0x4000>; 1215 1216 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1217 1218 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1219 clock-names = "se"; 1220 1221 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1222 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1223 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1224 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1225 interconnect-names = "qup-core", 1226 "qup-config"; 1227 1228 pinctrl-0 = <&qup_uart21_default>; 1229 pinctrl-names = "default"; 1230 1231 status = "disabled"; 1232 }; 1233 1234 i2c22: i2c@898000 { 1235 compatible = "qcom,geni-i2c"; 1236 reg = <0 0x00898000 0 0x4000>; 1237 1238 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1239 1240 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1241 clock-names = "se"; 1242 1243 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1244 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1245 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1246 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1247 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1249 interconnect-names = "qup-core", 1250 "qup-config", 1251 "qup-memory"; 1252 1253 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1254 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1255 dma-names = "tx", 1256 "rx"; 1257 1258 pinctrl-0 = <&qup_i2c22_data_clk>; 1259 pinctrl-names = "default"; 1260 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 1264 status = "disabled"; 1265 }; 1266 1267 spi22: spi@898000 { 1268 compatible = "qcom,geni-spi"; 1269 reg = <0 0x00898000 0 0x4000>; 1270 1271 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1272 1273 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1274 clock-names = "se"; 1275 1276 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1277 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1278 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1279 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1280 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1281 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1282 interconnect-names = "qup-core", 1283 "qup-config", 1284 "qup-memory"; 1285 1286 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1287 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1288 dma-names = "tx", 1289 "rx"; 1290 1291 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1292 pinctrl-names = "default"; 1293 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 1297 status = "disabled"; 1298 }; 1299 1300 i2c23: i2c@89c000 { 1301 compatible = "qcom,geni-i2c"; 1302 reg = <0 0x0089c000 0 0x4000>; 1303 1304 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1305 1306 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1307 clock-names = "se"; 1308 1309 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1310 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1311 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1312 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1313 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1314 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1315 interconnect-names = "qup-core", 1316 "qup-config", 1317 "qup-memory"; 1318 1319 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1320 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1321 dma-names = "tx", 1322 "rx"; 1323 1324 pinctrl-0 = <&qup_i2c23_data_clk>; 1325 pinctrl-names = "default"; 1326 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 1330 status = "disabled"; 1331 }; 1332 1333 spi23: spi@89c000 { 1334 compatible = "qcom,geni-spi"; 1335 reg = <0 0x0089c000 0 0x4000>; 1336 1337 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1338 1339 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1340 clock-names = "se"; 1341 1342 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1343 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1345 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1346 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1347 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1348 interconnect-names = "qup-core", 1349 "qup-config", 1350 "qup-memory"; 1351 1352 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1353 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1354 dma-names = "tx", 1355 "rx"; 1356 1357 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1358 pinctrl-names = "default"; 1359 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 1363 status = "disabled"; 1364 }; 1365 }; 1366 1367 gpi_dma1: dma-controller@a00000 { 1368 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1369 reg = <0 0x00a00000 0 0x60000>; 1370 1371 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1383 1384 dma-channels = <12>; 1385 dma-channel-mask = <0x3e>; 1386 #dma-cells = <3>; 1387 1388 iommus = <&apps_smmu 0x136 0x0>; 1389 1390 status = "disabled"; 1391 }; 1392 1393 qupv3_1: geniqup@ac0000 { 1394 compatible = "qcom,geni-se-qup"; 1395 reg = <0 0x00ac0000 0 0x2000>; 1396 1397 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1398 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1399 clock-names = "m-ahb", 1400 "s-ahb"; 1401 1402 iommus = <&apps_smmu 0x123 0x0>; 1403 1404 #address-cells = <2>; 1405 #size-cells = <2>; 1406 ranges; 1407 1408 status = "disabled"; 1409 1410 i2c8: i2c@a80000 { 1411 compatible = "qcom,geni-i2c"; 1412 reg = <0 0x00a80000 0 0x4000>; 1413 1414 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1415 1416 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1417 clock-names = "se"; 1418 1419 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1420 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1421 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1422 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1423 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1424 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1425 interconnect-names = "qup-core", 1426 "qup-config", 1427 "qup-memory"; 1428 1429 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1430 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1431 dma-names = "tx", 1432 "rx"; 1433 1434 pinctrl-0 = <&qup_i2c8_data_clk>; 1435 pinctrl-names = "default"; 1436 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 1440 status = "disabled"; 1441 }; 1442 1443 spi8: spi@a80000 { 1444 compatible = "qcom,geni-spi"; 1445 reg = <0 0x00a80000 0 0x4000>; 1446 1447 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1448 1449 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1450 clock-names = "se"; 1451 1452 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1453 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1454 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1455 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1456 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1457 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1458 interconnect-names = "qup-core", 1459 "qup-config", 1460 "qup-memory"; 1461 1462 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1463 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1464 dma-names = "tx", 1465 "rx"; 1466 1467 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1468 pinctrl-names = "default"; 1469 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 1473 status = "disabled"; 1474 }; 1475 1476 i2c9: i2c@a84000 { 1477 compatible = "qcom,geni-i2c"; 1478 reg = <0 0x00a84000 0 0x4000>; 1479 1480 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1481 1482 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1483 clock-names = "se"; 1484 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1486 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1487 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1488 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1489 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1490 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1491 interconnect-names = "qup-core", 1492 "qup-config", 1493 "qup-memory"; 1494 1495 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1496 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1497 dma-names = "tx", 1498 "rx"; 1499 1500 pinctrl-0 = <&qup_i2c9_data_clk>; 1501 pinctrl-names = "default"; 1502 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 1506 status = "disabled"; 1507 }; 1508 1509 spi9: spi@a84000 { 1510 compatible = "qcom,geni-spi"; 1511 reg = <0 0x00a84000 0 0x4000>; 1512 1513 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1514 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1516 clock-names = "se"; 1517 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1522 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1524 interconnect-names = "qup-core", 1525 "qup-config", 1526 "qup-memory"; 1527 1528 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1529 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1530 dma-names = "tx", 1531 "rx"; 1532 1533 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1534 pinctrl-names = "default"; 1535 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 1539 status = "disabled"; 1540 }; 1541 1542 i2c10: i2c@a88000 { 1543 compatible = "qcom,geni-i2c"; 1544 reg = <0 0x00a88000 0 0x4000>; 1545 1546 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1547 1548 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1549 clock-names = "se"; 1550 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1552 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1553 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1554 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1555 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1556 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1557 interconnect-names = "qup-core", 1558 "qup-config", 1559 "qup-memory"; 1560 1561 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1562 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1563 dma-names = "tx", 1564 "rx"; 1565 1566 pinctrl-0 = <&qup_i2c10_data_clk>; 1567 pinctrl-names = "default"; 1568 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 1572 status = "disabled"; 1573 }; 1574 1575 spi10: spi@a88000 { 1576 compatible = "qcom,geni-spi"; 1577 reg = <0 0x00a88000 0 0x4000>; 1578 1579 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1580 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1582 clock-names = "se"; 1583 1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1585 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1586 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1587 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1588 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1589 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1590 interconnect-names = "qup-core", 1591 "qup-config", 1592 "qup-memory"; 1593 1594 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1595 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1596 dma-names = "tx", 1597 "rx"; 1598 1599 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1600 pinctrl-names = "default"; 1601 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 1605 status = "disabled"; 1606 }; 1607 1608 i2c11: i2c@a8c000 { 1609 compatible = "qcom,geni-i2c"; 1610 reg = <0 0x00a8c000 0 0x4000>; 1611 1612 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1613 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1615 clock-names = "se"; 1616 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1618 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1620 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1621 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1623 interconnect-names = "qup-core", 1624 "qup-config", 1625 "qup-memory"; 1626 1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1628 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1629 dma-names = "tx", 1630 "rx"; 1631 1632 pinctrl-0 = <&qup_i2c11_data_clk>; 1633 pinctrl-names = "default"; 1634 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 1638 status = "disabled"; 1639 }; 1640 1641 spi11: spi@a8c000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00a8c000 0 0x4000>; 1644 1645 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1646 1647 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1648 clock-names = "se"; 1649 1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1651 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1653 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1654 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1656 interconnect-names = "qup-core", 1657 "qup-config", 1658 "qup-memory"; 1659 1660 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1661 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1662 dma-names = "tx", 1663 "rx"; 1664 1665 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1666 pinctrl-names = "default"; 1667 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 1671 status = "disabled"; 1672 }; 1673 1674 i2c12: i2c@a90000 { 1675 compatible = "qcom,geni-i2c"; 1676 reg = <0 0x00a90000 0 0x4000>; 1677 1678 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1679 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1681 clock-names = "se"; 1682 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1684 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1685 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1686 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1687 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1688 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1689 interconnect-names = "qup-core", 1690 "qup-config", 1691 "qup-memory"; 1692 1693 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1694 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1695 dma-names = "tx", 1696 "rx"; 1697 1698 pinctrl-0 = <&qup_i2c12_data_clk>; 1699 pinctrl-names = "default"; 1700 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 1704 status = "disabled"; 1705 }; 1706 1707 spi12: spi@a90000 { 1708 compatible = "qcom,geni-spi"; 1709 reg = <0 0x00a90000 0 0x4000>; 1710 1711 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1712 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1714 clock-names = "se"; 1715 1716 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1717 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1718 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1719 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1720 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1721 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1722 interconnect-names = "qup-core", 1723 "qup-config", 1724 "qup-memory"; 1725 1726 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1727 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1728 dma-names = "tx", 1729 "rx"; 1730 1731 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1732 pinctrl-names = "default"; 1733 1734 #address-cells = <1>; 1735 #size-cells = <0>; 1736 1737 status = "disabled"; 1738 }; 1739 1740 i2c13: i2c@a94000 { 1741 compatible = "qcom,geni-i2c"; 1742 reg = <0 0x00a94000 0 0x4000>; 1743 1744 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1745 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1747 clock-names = "se"; 1748 1749 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1750 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1752 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1753 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1755 interconnect-names = "qup-core", 1756 "qup-config", 1757 "qup-memory"; 1758 1759 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1760 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1761 dma-names = "tx", 1762 "rx"; 1763 1764 pinctrl-0 = <&qup_i2c13_data_clk>; 1765 pinctrl-names = "default"; 1766 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 1770 status = "disabled"; 1771 }; 1772 1773 spi13: spi@a94000 { 1774 compatible = "qcom,geni-spi"; 1775 reg = <0 0x00a94000 0 0x4000>; 1776 1777 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1778 1779 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1780 clock-names = "se"; 1781 1782 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1783 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1784 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1785 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1786 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1787 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1788 interconnect-names = "qup-core", 1789 "qup-config", 1790 "qup-memory"; 1791 1792 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1793 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1794 dma-names = "tx", 1795 "rx"; 1796 1797 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1798 pinctrl-names = "default"; 1799 1800 #address-cells = <1>; 1801 #size-cells = <0>; 1802 1803 status = "disabled"; 1804 }; 1805 1806 i2c14: i2c@a98000 { 1807 compatible = "qcom,geni-i2c"; 1808 reg = <0 0x00a98000 0 0x4000>; 1809 1810 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1811 1812 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1813 clock-names = "se"; 1814 1815 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1816 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1818 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1819 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1821 interconnect-names = "qup-core", 1822 "qup-config", 1823 "qup-memory"; 1824 1825 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1826 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1827 dma-names = "tx", 1828 "rx"; 1829 1830 pinctrl-0 = <&qup_i2c14_data_clk>; 1831 pinctrl-names = "default"; 1832 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 1836 status = "disabled"; 1837 }; 1838 1839 spi14: spi@a98000 { 1840 compatible = "qcom,geni-spi"; 1841 reg = <0 0x00a98000 0 0x4000>; 1842 1843 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1844 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1846 clock-names = "se"; 1847 1848 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1849 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1850 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1851 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1852 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1853 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1854 interconnect-names = "qup-core", 1855 "qup-config", 1856 "qup-memory"; 1857 1858 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1859 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1860 dma-names = "tx", 1861 "rx"; 1862 1863 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1864 pinctrl-names = "default"; 1865 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 1869 status = "disabled"; 1870 }; 1871 1872 i2c15: i2c@a9c000 { 1873 compatible = "qcom,geni-i2c"; 1874 reg = <0 0x00a9c000 0 0x4000>; 1875 1876 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1877 1878 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1879 clock-names = "se"; 1880 1881 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1882 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1884 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1885 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1886 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1887 interconnect-names = "qup-core", 1888 "qup-config", 1889 "qup-memory"; 1890 1891 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1892 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1893 dma-names = "tx", 1894 "rx"; 1895 1896 pinctrl-0 = <&qup_i2c15_data_clk>; 1897 pinctrl-names = "default"; 1898 1899 #address-cells = <1>; 1900 #size-cells = <0>; 1901 1902 status = "disabled"; 1903 }; 1904 1905 spi15: spi@a9c000 { 1906 compatible = "qcom,geni-spi"; 1907 reg = <0 0x00a9c000 0 0x4000>; 1908 1909 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1910 1911 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1912 clock-names = "se"; 1913 1914 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1915 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1917 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1918 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1920 interconnect-names = "qup-core", 1921 "qup-config", 1922 "qup-memory"; 1923 1924 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1925 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1926 dma-names = "tx", 1927 "rx"; 1928 1929 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1930 pinctrl-names = "default"; 1931 1932 #address-cells = <1>; 1933 #size-cells = <0>; 1934 1935 status = "disabled"; 1936 }; 1937 }; 1938 1939 gpi_dma0: dma-controller@b00000 { 1940 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1941 reg = <0 0x00b00000 0 0x60000>; 1942 1943 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1955 1956 dma-channels = <12>; 1957 dma-channel-mask = <0x3e>; 1958 #dma-cells = <3>; 1959 1960 iommus = <&apps_smmu 0x456 0x0>; 1961 1962 status = "disabled"; 1963 }; 1964 1965 qupv3_0: geniqup@bc0000 { 1966 compatible = "qcom,geni-se-qup"; 1967 reg = <0 0x00bc0000 0 0x2000>; 1968 1969 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1970 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1971 clock-names = "m-ahb", 1972 "s-ahb"; 1973 1974 iommus = <&apps_smmu 0x443 0x0>; 1975 #address-cells = <2>; 1976 #size-cells = <2>; 1977 ranges; 1978 1979 status = "disabled"; 1980 1981 i2c0: i2c@b80000 { 1982 compatible = "qcom,geni-i2c"; 1983 reg = <0 0x00b80000 0 0x4000>; 1984 1985 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1986 1987 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1988 clock-names = "se"; 1989 1990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1996 interconnect-names = "qup-core", 1997 "qup-config", 1998 "qup-memory"; 1999 2000 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2001 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2002 dma-names = "tx", 2003 "rx"; 2004 2005 pinctrl-0 = <&qup_i2c0_data_clk>; 2006 pinctrl-names = "default"; 2007 2008 #address-cells = <1>; 2009 #size-cells = <0>; 2010 2011 status = "disabled"; 2012 }; 2013 2014 spi0: spi@b80000 { 2015 compatible = "qcom,geni-spi"; 2016 reg = <0 0x00b80000 0 0x4000>; 2017 2018 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2019 2020 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2021 clock-names = "se"; 2022 2023 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2024 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2025 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2026 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2027 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2029 interconnect-names = "qup-core", 2030 "qup-config", 2031 "qup-memory"; 2032 2033 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2034 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2035 dma-names = "tx", 2036 "rx"; 2037 2038 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2039 pinctrl-names = "default"; 2040 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 2044 status = "disabled"; 2045 }; 2046 2047 i2c1: i2c@b84000 { 2048 compatible = "qcom,geni-i2c"; 2049 reg = <0 0x00b84000 0 0x4000>; 2050 2051 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2052 2053 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2054 clock-names = "se"; 2055 2056 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2057 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2058 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2059 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2060 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2062 interconnect-names = "qup-core", 2063 "qup-config", 2064 "qup-memory"; 2065 2066 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2067 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2068 dma-names = "tx", 2069 "rx"; 2070 2071 pinctrl-0 = <&qup_i2c1_data_clk>; 2072 pinctrl-names = "default"; 2073 2074 #address-cells = <1>; 2075 #size-cells = <0>; 2076 2077 status = "disabled"; 2078 }; 2079 2080 spi1: spi@b84000 { 2081 compatible = "qcom,geni-spi"; 2082 reg = <0 0x00b84000 0 0x4000>; 2083 2084 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2085 2086 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2087 clock-names = "se"; 2088 2089 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2090 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2091 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2092 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2093 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2095 interconnect-names = "qup-core", 2096 "qup-config", 2097 "qup-memory"; 2098 2099 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2100 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2101 dma-names = "tx", 2102 "rx"; 2103 2104 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2105 pinctrl-names = "default"; 2106 2107 #address-cells = <1>; 2108 #size-cells = <0>; 2109 2110 status = "disabled"; 2111 }; 2112 2113 i2c2: i2c@b88000 { 2114 compatible = "qcom,geni-i2c"; 2115 reg = <0 0x00b88000 0 0x4000>; 2116 2117 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2118 2119 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2120 clock-names = "se"; 2121 2122 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2123 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2124 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2125 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2126 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2128 interconnect-names = "qup-core", 2129 "qup-config", 2130 "qup-memory"; 2131 2132 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2133 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2134 dma-names = "tx", 2135 "rx"; 2136 2137 pinctrl-0 = <&qup_i2c2_data_clk>; 2138 pinctrl-names = "default"; 2139 2140 #address-cells = <1>; 2141 #size-cells = <0>; 2142 2143 status = "disabled"; 2144 }; 2145 2146 uart2: serial@b88000 { 2147 compatible = "qcom,geni-uart"; 2148 reg = <0 0x00b88000 0 0x4000>; 2149 2150 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2151 2152 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2153 clock-names = "se"; 2154 2155 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2156 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2157 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2158 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2159 interconnect-names = "qup-core", 2160 "qup-config"; 2161 2162 pinctrl-0 = <&qup_uart2_default>; 2163 pinctrl-names = "default"; 2164 2165 status = "disabled"; 2166 }; 2167 2168 spi2: spi@b88000 { 2169 compatible = "qcom,geni-spi"; 2170 reg = <0 0x00b88000 0 0x4000>; 2171 2172 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2173 2174 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2175 clock-names = "se"; 2176 2177 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2178 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2179 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2180 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2181 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2182 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2183 interconnect-names = "qup-core", 2184 "qup-config", 2185 "qup-memory"; 2186 2187 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2188 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2189 dma-names = "tx", 2190 "rx"; 2191 2192 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2193 pinctrl-names = "default"; 2194 2195 #address-cells = <1>; 2196 #size-cells = <0>; 2197 2198 status = "disabled"; 2199 }; 2200 2201 i2c3: i2c@b8c000 { 2202 compatible = "qcom,geni-i2c"; 2203 reg = <0 0x00b8c000 0 0x4000>; 2204 2205 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2206 2207 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2208 clock-names = "se"; 2209 2210 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2211 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2212 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2213 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2214 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2215 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2216 interconnect-names = "qup-core", 2217 "qup-config", 2218 "qup-memory"; 2219 2220 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2221 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2222 dma-names = "tx", 2223 "rx"; 2224 2225 pinctrl-0 = <&qup_i2c3_data_clk>; 2226 pinctrl-names = "default"; 2227 2228 #address-cells = <1>; 2229 #size-cells = <0>; 2230 2231 status = "disabled"; 2232 }; 2233 2234 spi3: spi@b8c000 { 2235 compatible = "qcom,geni-spi"; 2236 reg = <0 0x00b8c000 0 0x4000>; 2237 2238 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2239 2240 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2241 clock-names = "se"; 2242 2243 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2244 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2245 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2246 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2247 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2249 interconnect-names = "qup-core", 2250 "qup-config", 2251 "qup-memory"; 2252 2253 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2254 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2255 dma-names = "tx", 2256 "rx"; 2257 2258 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2259 pinctrl-names = "default"; 2260 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 2264 status = "disabled"; 2265 }; 2266 2267 i2c4: i2c@b90000 { 2268 compatible = "qcom,geni-i2c"; 2269 reg = <0 0x00b90000 0 0x4000>; 2270 2271 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2272 2273 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2274 clock-names = "se"; 2275 2276 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2277 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2278 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2279 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2280 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2281 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2282 interconnect-names = "qup-core", 2283 "qup-config", 2284 "qup-memory"; 2285 2286 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2287 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2288 dma-names = "tx", 2289 "rx"; 2290 2291 pinctrl-0 = <&qup_i2c4_data_clk>; 2292 pinctrl-names = "default"; 2293 2294 #address-cells = <1>; 2295 #size-cells = <0>; 2296 2297 status = "disabled"; 2298 }; 2299 2300 spi4: spi@b90000 { 2301 compatible = "qcom,geni-spi"; 2302 reg = <0 0x00b90000 0 0x4000>; 2303 2304 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2305 2306 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2307 clock-names = "se"; 2308 2309 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2310 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2311 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2312 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2313 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2314 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2315 interconnect-names = "qup-core", 2316 "qup-config", 2317 "qup-memory"; 2318 2319 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2320 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2321 dma-names = "tx", 2322 "rx"; 2323 2324 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2325 pinctrl-names = "default"; 2326 2327 #address-cells = <1>; 2328 #size-cells = <0>; 2329 2330 status = "disabled"; 2331 }; 2332 2333 i2c5: i2c@b94000 { 2334 compatible = "qcom,geni-i2c"; 2335 reg = <0 0x00b94000 0 0x4000>; 2336 2337 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2338 2339 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2340 clock-names = "se"; 2341 2342 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2343 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2345 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2346 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2347 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2348 interconnect-names = "qup-core", 2349 "qup-config", 2350 "qup-memory"; 2351 2352 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2353 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2354 dma-names = "tx", 2355 "rx"; 2356 2357 pinctrl-0 = <&qup_i2c5_data_clk>; 2358 pinctrl-names = "default"; 2359 2360 #address-cells = <1>; 2361 #size-cells = <0>; 2362 2363 status = "disabled"; 2364 }; 2365 2366 spi5: spi@b94000 { 2367 compatible = "qcom,geni-spi"; 2368 reg = <0 0x00b94000 0 0x4000>; 2369 2370 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2371 2372 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2373 clock-names = "se"; 2374 2375 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2376 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2377 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2378 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2379 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2380 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2381 interconnect-names = "qup-core", 2382 "qup-config", 2383 "qup-memory"; 2384 2385 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2386 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2387 dma-names = "tx", 2388 "rx"; 2389 2390 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2391 pinctrl-names = "default"; 2392 2393 #address-cells = <1>; 2394 #size-cells = <0>; 2395 2396 status = "disabled"; 2397 }; 2398 2399 i2c6: i2c@b98000 { 2400 compatible = "qcom,geni-i2c"; 2401 reg = <0 0x00b98000 0 0x4000>; 2402 2403 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2404 2405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2406 clock-names = "se"; 2407 2408 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2409 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2410 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2411 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2412 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2413 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2414 interconnect-names = "qup-core", 2415 "qup-config", 2416 "qup-memory"; 2417 2418 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2419 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2420 dma-names = "tx", 2421 "rx"; 2422 2423 pinctrl-0 = <&qup_i2c6_data_clk>; 2424 pinctrl-names = "default"; 2425 2426 #address-cells = <1>; 2427 #size-cells = <0>; 2428 2429 status = "disabled"; 2430 }; 2431 2432 spi6: spi@b98000 { 2433 compatible = "qcom,geni-spi"; 2434 reg = <0 0x00b98000 0 0x4000>; 2435 2436 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2437 2438 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2439 clock-names = "se"; 2440 2441 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2442 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2443 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2444 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2445 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2446 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2447 interconnect-names = "qup-core", 2448 "qup-config", 2449 "qup-memory"; 2450 2451 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2452 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2453 dma-names = "tx", 2454 "rx"; 2455 2456 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2457 pinctrl-names = "default"; 2458 2459 #address-cells = <1>; 2460 #size-cells = <0>; 2461 2462 status = "disabled"; 2463 }; 2464 2465 i2c7: i2c@b9c000 { 2466 compatible = "qcom,geni-i2c"; 2467 reg = <0 0x00b9c000 0 0x4000>; 2468 2469 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2470 2471 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2472 clock-names = "se"; 2473 2474 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2475 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2476 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2477 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2478 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2479 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2480 interconnect-names = "qup-core", 2481 "qup-config", 2482 "qup-memory"; 2483 2484 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2485 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2486 dma-names = "tx", 2487 "rx"; 2488 2489 pinctrl-0 = <&qup_i2c7_data_clk>; 2490 pinctrl-names = "default"; 2491 2492 #address-cells = <1>; 2493 #size-cells = <0>; 2494 2495 status = "disabled"; 2496 }; 2497 2498 spi7: spi@b9c000 { 2499 compatible = "qcom,geni-spi"; 2500 reg = <0 0x00b9c000 0 0x4000>; 2501 2502 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2503 2504 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2505 clock-names = "se"; 2506 2507 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2508 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2509 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2510 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2511 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2512 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2513 interconnect-names = "qup-core", 2514 "qup-config", 2515 "qup-memory"; 2516 2517 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2518 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2519 dma-names = "tx", 2520 "rx"; 2521 2522 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2523 pinctrl-names = "default"; 2524 2525 #address-cells = <1>; 2526 #size-cells = <0>; 2527 2528 status = "disabled"; 2529 }; 2530 }; 2531 2532 tsens0: thermal-sensor@c271000 { 2533 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2534 reg = <0 0x0c271000 0 0x1000>, 2535 <0 0x0c222000 0 0x1000>; 2536 2537 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2538 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2539 interrupt-names = "uplow", 2540 "critical"; 2541 2542 #qcom,sensors = <16>; 2543 2544 #thermal-sensor-cells = <1>; 2545 }; 2546 2547 tsens1: thermal-sensor@c272000 { 2548 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2549 reg = <0 0x0c272000 0 0x1000>, 2550 <0 0x0c223000 0 0x1000>; 2551 2552 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2553 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2554 interrupt-names = "uplow", 2555 "critical"; 2556 2557 #qcom,sensors = <16>; 2558 2559 #thermal-sensor-cells = <1>; 2560 }; 2561 2562 tsens2: thermal-sensor@c273000 { 2563 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2564 reg = <0 0x0c273000 0 0x1000>, 2565 <0 0x0c224000 0 0x1000>; 2566 2567 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2568 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2569 interrupt-names = "uplow", 2570 "critical"; 2571 2572 #qcom,sensors = <16>; 2573 2574 #thermal-sensor-cells = <1>; 2575 }; 2576 2577 tsens3: thermal-sensor@c274000 { 2578 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2579 reg = <0 0x0c274000 0 0x1000>, 2580 <0 0x0c225000 0 0x1000>; 2581 2582 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2583 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2584 interrupt-names = "uplow", 2585 "critical"; 2586 2587 #qcom,sensors = <16>; 2588 2589 #thermal-sensor-cells = <1>; 2590 }; 2591 2592 usb_1_ss0_hsphy: phy@fd3000 { 2593 compatible = "qcom,x1e80100-snps-eusb2-phy", 2594 "qcom,sm8550-snps-eusb2-phy"; 2595 reg = <0 0x00fd3000 0 0x154>; 2596 #phy-cells = <0>; 2597 2598 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2599 clock-names = "ref"; 2600 2601 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2602 2603 status = "disabled"; 2604 }; 2605 2606 usb_1_ss0_qmpphy: phy@fd5000 { 2607 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2608 reg = <0 0x00fd5000 0 0x4000>; 2609 2610 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2611 <&rpmhcc RPMH_CXO_CLK>, 2612 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2613 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2614 clock-names = "aux", 2615 "ref", 2616 "com_aux", 2617 "usb3_pipe"; 2618 2619 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2620 2621 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2622 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2623 reset-names = "phy", 2624 "common"; 2625 2626 #clock-cells = <1>; 2627 #phy-cells = <1>; 2628 2629 orientation-switch; 2630 2631 status = "disabled"; 2632 2633 ports { 2634 #address-cells = <1>; 2635 #size-cells = <0>; 2636 2637 port@0 { 2638 reg = <0>; 2639 2640 usb_1_ss0_qmpphy_out: endpoint { 2641 }; 2642 }; 2643 2644 port@1 { 2645 reg = <1>; 2646 2647 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2648 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2649 }; 2650 }; 2651 2652 port@2 { 2653 reg = <2>; 2654 2655 usb_1_ss0_qmpphy_dp_in: endpoint { 2656 remote-endpoint = <&mdss_dp0_out>; 2657 }; 2658 }; 2659 }; 2660 }; 2661 2662 usb_1_ss1_hsphy: phy@fd9000 { 2663 compatible = "qcom,x1e80100-snps-eusb2-phy", 2664 "qcom,sm8550-snps-eusb2-phy"; 2665 reg = <0 0x00fd9000 0 0x154>; 2666 #phy-cells = <0>; 2667 2668 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2669 clock-names = "ref"; 2670 2671 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2672 2673 status = "disabled"; 2674 }; 2675 2676 usb_1_ss1_qmpphy: phy@fda000 { 2677 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2678 reg = <0 0x00fda000 0 0x4000>; 2679 2680 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2681 <&rpmhcc RPMH_CXO_CLK>, 2682 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2683 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2684 clock-names = "aux", 2685 "ref", 2686 "com_aux", 2687 "usb3_pipe"; 2688 2689 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2690 2691 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2692 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2693 reset-names = "phy", 2694 "common"; 2695 2696 #clock-cells = <1>; 2697 #phy-cells = <1>; 2698 2699 orientation-switch; 2700 2701 status = "disabled"; 2702 2703 ports { 2704 #address-cells = <1>; 2705 #size-cells = <0>; 2706 2707 port@0 { 2708 reg = <0>; 2709 2710 usb_1_ss1_qmpphy_out: endpoint { 2711 }; 2712 }; 2713 2714 port@1 { 2715 reg = <1>; 2716 2717 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2718 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2719 }; 2720 }; 2721 2722 port@2 { 2723 reg = <2>; 2724 2725 usb_1_ss1_qmpphy_dp_in: endpoint { 2726 remote-endpoint = <&mdss_dp1_out>; 2727 }; 2728 }; 2729 }; 2730 }; 2731 2732 usb_1_ss2_hsphy: phy@fde000 { 2733 compatible = "qcom,x1e80100-snps-eusb2-phy", 2734 "qcom,sm8550-snps-eusb2-phy"; 2735 reg = <0 0x00fde000 0 0x154>; 2736 #phy-cells = <0>; 2737 2738 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2739 clock-names = "ref"; 2740 2741 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2742 2743 status = "disabled"; 2744 }; 2745 2746 usb_1_ss2_qmpphy: phy@fdf000 { 2747 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2748 reg = <0 0x00fdf000 0 0x4000>; 2749 2750 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2751 <&rpmhcc RPMH_CXO_CLK>, 2752 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2753 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2754 clock-names = "aux", 2755 "ref", 2756 "com_aux", 2757 "usb3_pipe"; 2758 2759 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2760 2761 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2762 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2763 reset-names = "phy", 2764 "common"; 2765 2766 #clock-cells = <1>; 2767 #phy-cells = <1>; 2768 2769 orientation-switch; 2770 2771 status = "disabled"; 2772 2773 ports { 2774 #address-cells = <1>; 2775 #size-cells = <0>; 2776 2777 port@0 { 2778 reg = <0>; 2779 2780 usb_1_ss2_qmpphy_out: endpoint { 2781 }; 2782 }; 2783 2784 port@1 { 2785 reg = <1>; 2786 2787 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 2788 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 2789 }; 2790 }; 2791 2792 port@2 { 2793 reg = <2>; 2794 2795 usb_1_ss2_qmpphy_dp_in: endpoint { 2796 remote-endpoint = <&mdss_dp2_out>; 2797 }; 2798 }; 2799 }; 2800 }; 2801 2802 cnoc_main: interconnect@1500000 { 2803 compatible = "qcom,x1e80100-cnoc-main"; 2804 reg = <0 0x01500000 0 0x14400>; 2805 2806 qcom,bcm-voters = <&apps_bcm_voter>; 2807 2808 #interconnect-cells = <2>; 2809 }; 2810 2811 config_noc: interconnect@1600000 { 2812 compatible = "qcom,x1e80100-cnoc-cfg"; 2813 reg = <0 0x01600000 0 0x6600>; 2814 2815 qcom,bcm-voters = <&apps_bcm_voter>; 2816 2817 #interconnect-cells = <2>; 2818 }; 2819 2820 system_noc: interconnect@1680000 { 2821 compatible = "qcom,x1e80100-system-noc"; 2822 reg = <0 0x01680000 0 0x1c080>; 2823 2824 qcom,bcm-voters = <&apps_bcm_voter>; 2825 2826 #interconnect-cells = <2>; 2827 }; 2828 2829 pcie_south_anoc: interconnect@16c0000 { 2830 compatible = "qcom,x1e80100-pcie-south-anoc"; 2831 reg = <0 0x016c0000 0 0xd080>; 2832 2833 qcom,bcm-voters = <&apps_bcm_voter>; 2834 2835 #interconnect-cells = <2>; 2836 }; 2837 2838 pcie_center_anoc: interconnect@16d0000 { 2839 compatible = "qcom,x1e80100-pcie-center-anoc"; 2840 reg = <0 0x016d0000 0 0x7000>; 2841 2842 qcom,bcm-voters = <&apps_bcm_voter>; 2843 2844 #interconnect-cells = <2>; 2845 }; 2846 2847 aggre1_noc: interconnect@16e0000 { 2848 compatible = "qcom,x1e80100-aggre1-noc"; 2849 reg = <0 0x016e0000 0 0x14400>; 2850 2851 qcom,bcm-voters = <&apps_bcm_voter>; 2852 2853 #interconnect-cells = <2>; 2854 }; 2855 2856 aggre2_noc: interconnect@1700000 { 2857 compatible = "qcom,x1e80100-aggre2-noc"; 2858 reg = <0 0x01700000 0 0x1c400>; 2859 2860 qcom,bcm-voters = <&apps_bcm_voter>; 2861 2862 #interconnect-cells = <2>; 2863 }; 2864 2865 pcie_north_anoc: interconnect@1740000 { 2866 compatible = "qcom,x1e80100-pcie-north-anoc"; 2867 reg = <0 0x01740000 0 0x9080>; 2868 2869 qcom,bcm-voters = <&apps_bcm_voter>; 2870 2871 #interconnect-cells = <2>; 2872 }; 2873 2874 usb_center_anoc: interconnect@1750000 { 2875 compatible = "qcom,x1e80100-usb-center-anoc"; 2876 reg = <0 0x01750000 0 0x8800>; 2877 2878 qcom,bcm-voters = <&apps_bcm_voter>; 2879 2880 #interconnect-cells = <2>; 2881 }; 2882 2883 usb_north_anoc: interconnect@1760000 { 2884 compatible = "qcom,x1e80100-usb-north-anoc"; 2885 reg = <0 0x01760000 0 0x7080>; 2886 2887 qcom,bcm-voters = <&apps_bcm_voter>; 2888 2889 #interconnect-cells = <2>; 2890 }; 2891 2892 usb_south_anoc: interconnect@1770000 { 2893 compatible = "qcom,x1e80100-usb-south-anoc"; 2894 reg = <0 0x01770000 0 0xf080>; 2895 2896 qcom,bcm-voters = <&apps_bcm_voter>; 2897 2898 #interconnect-cells = <2>; 2899 }; 2900 2901 mmss_noc: interconnect@1780000 { 2902 compatible = "qcom,x1e80100-mmss-noc"; 2903 reg = <0 0x01780000 0 0x5B800>; 2904 2905 qcom,bcm-voters = <&apps_bcm_voter>; 2906 2907 #interconnect-cells = <2>; 2908 }; 2909 2910 pcie6a: pci@1bf8000 { 2911 device_type = "pci"; 2912 compatible = "qcom,pcie-x1e80100"; 2913 reg = <0 0x01bf8000 0 0x3000>, 2914 <0 0x70000000 0 0xf20>, 2915 <0 0x70000f40 0 0xa8>, 2916 <0 0x70001000 0 0x1000>, 2917 <0 0x70100000 0 0x100000>, 2918 <0 0x01bfb000 0 0x1000>; 2919 reg-names = "parf", 2920 "dbi", 2921 "elbi", 2922 "atu", 2923 "config", 2924 "mhi"; 2925 #address-cells = <3>; 2926 #size-cells = <2>; 2927 ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, 2928 <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; 2929 bus-range = <0 0xff>; 2930 2931 dma-coherent; 2932 2933 linux,pci-domain = <6>; 2934 num-lanes = <2>; 2935 2936 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 2937 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 2938 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 2944 interrupt-names = "msi0", 2945 "msi1", 2946 "msi2", 2947 "msi3", 2948 "msi4", 2949 "msi5", 2950 "msi6", 2951 "msi7"; 2952 2953 #interrupt-cells = <1>; 2954 interrupt-map-mask = <0 0 0 0x7>; 2955 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, 2956 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, 2957 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, 2958 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; 2959 2960 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 2961 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 2962 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 2963 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 2964 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 2965 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 2966 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 2967 clock-names = "aux", 2968 "cfg", 2969 "bus_master", 2970 "bus_slave", 2971 "slave_q2a", 2972 "noc_aggr", 2973 "cnoc_sf_axi"; 2974 2975 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 2976 assigned-clock-rates = <19200000>; 2977 2978 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 2979 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2980 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2981 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; 2982 interconnect-names = "pcie-mem", 2983 "cpu-pcie"; 2984 2985 resets = <&gcc GCC_PCIE_6A_BCR>, 2986 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 2987 reset-names = "pci", 2988 "link_down"; 2989 2990 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 2991 required-opps = <&rpmhpd_opp_nom>; 2992 2993 phys = <&pcie6a_phy>; 2994 phy-names = "pciephy"; 2995 2996 status = "disabled"; 2997 }; 2998 2999 pcie6a_phy: phy@1bfc000 { 3000 compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; 3001 reg = <0 0x01bfc000 0 0x2000>; 3002 3003 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3004 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3005 <&rpmhcc RPMH_CXO_CLK>, 3006 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3007 <&gcc GCC_PCIE_6A_PIPE_CLK>; 3008 clock-names = "aux", 3009 "cfg_ahb", 3010 "ref", 3011 "rchng", 3012 "pipe"; 3013 3014 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3015 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3016 reset-names = "phy", 3017 "phy_nocsr"; 3018 3019 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3020 assigned-clock-rates = <100000000>; 3021 3022 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3023 3024 #clock-cells = <0>; 3025 clock-output-names = "pcie6a_pipe_clk"; 3026 3027 #phy-cells = <0>; 3028 3029 status = "disabled"; 3030 }; 3031 3032 pcie5: pci@1c00000 { 3033 device_type = "pci"; 3034 compatible = "qcom,pcie-x1e80100"; 3035 reg = <0 0x01c00000 0 0x3000>, 3036 <0 0x7e000000 0 0xf1d>, 3037 <0 0x7e000f40 0 0xa8>, 3038 <0 0x7e001000 0 0x1000>, 3039 <0 0x7e100000 0 0x100000>, 3040 <0 0x01c03000 0 0x1000>; 3041 reg-names = "parf", 3042 "dbi", 3043 "elbi", 3044 "atu", 3045 "config", 3046 "mhi"; 3047 #address-cells = <3>; 3048 #size-cells = <2>; 3049 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3050 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3051 bus-range = <0x00 0xff>; 3052 3053 dma-coherent; 3054 3055 linux,pci-domain = <5>; 3056 num-lanes = <2>; 3057 3058 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3062 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 3066 interrupt-names = "msi0", 3067 "msi1", 3068 "msi2", 3069 "msi3", 3070 "msi4", 3071 "msi5", 3072 "msi6", 3073 "msi7"; 3074 3075 #interrupt-cells = <1>; 3076 interrupt-map-mask = <0 0 0 0x7>; 3077 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, 3078 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>, 3079 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>, 3080 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>; 3081 3082 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3083 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3084 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3085 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3086 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3087 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3088 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3089 clock-names = "aux", 3090 "cfg", 3091 "bus_master", 3092 "bus_slave", 3093 "slave_q2a", 3094 "noc_aggr", 3095 "cnoc_sf_axi"; 3096 3097 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3098 assigned-clock-rates = <19200000>; 3099 3100 interconnects = <&pcie_south_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3101 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3102 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3103 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3104 interconnect-names = "pcie-mem", 3105 "cpu-pcie"; 3106 3107 resets = <&gcc GCC_PCIE_5_BCR>, 3108 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3109 reset-names = "pci", 3110 "link_down"; 3111 3112 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3113 required-opps = <&rpmhpd_opp_nom>; 3114 3115 phys = <&pcie5_phy>; 3116 phy-names = "pciephy"; 3117 3118 status = "disabled"; 3119 }; 3120 3121 pcie5_phy: phy@1c06000 { 3122 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3123 reg = <0 0x01c06000 0 0x2000>; 3124 3125 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3126 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3127 <&rpmhcc RPMH_CXO_CLK>, 3128 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3129 <&gcc GCC_PCIE_5_PIPE_CLK>; 3130 clock-names = "aux", 3131 "cfg_ahb", 3132 "ref", 3133 "rchng", 3134 "pipe"; 3135 3136 resets = <&gcc GCC_PCIE_5_PHY_BCR>; 3137 reset-names = "phy"; 3138 3139 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3140 assigned-clock-rates = <100000000>; 3141 3142 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3143 3144 #clock-cells = <0>; 3145 clock-output-names = "pcie5_pipe_clk"; 3146 3147 #phy-cells = <0>; 3148 3149 status = "disabled"; 3150 }; 3151 3152 pcie4: pci@1c08000 { 3153 device_type = "pci"; 3154 compatible = "qcom,pcie-x1e80100"; 3155 reg = <0 0x01c08000 0 0x3000>, 3156 <0 0x7c000000 0 0xf1d>, 3157 <0 0x7c000f40 0 0xa8>, 3158 <0 0x7c001000 0 0x1000>, 3159 <0 0x7c100000 0 0x100000>, 3160 <0 0x01c0b000 0 0x1000>; 3161 reg-names = "parf", 3162 "dbi", 3163 "elbi", 3164 "atu", 3165 "config", 3166 "mhi"; 3167 #address-cells = <3>; 3168 #size-cells = <2>; 3169 ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, 3170 <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; 3171 bus-range = <0x00 0xff>; 3172 3173 dma-coherent; 3174 3175 linux,pci-domain = <4>; 3176 num-lanes = <2>; 3177 3178 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 3186 interrupt-names = "msi0", 3187 "msi1", 3188 "msi2", 3189 "msi3", 3190 "msi4", 3191 "msi5", 3192 "msi6", 3193 "msi7"; 3194 3195 #interrupt-cells = <1>; 3196 interrupt-map-mask = <0 0 0 0x7>; 3197 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 3198 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 3199 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 3200 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 3201 3202 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3203 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3204 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3205 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3206 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3207 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3208 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3209 clock-names = "aux", 3210 "cfg", 3211 "bus_master", 3212 "bus_slave", 3213 "slave_q2a", 3214 "noc_aggr", 3215 "cnoc_sf_axi"; 3216 3217 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3218 assigned-clock-rates = <19200000>; 3219 3220 interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3221 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3222 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3223 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 3224 interconnect-names = "pcie-mem", 3225 "cpu-pcie"; 3226 3227 resets = <&gcc GCC_PCIE_4_BCR>, 3228 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3229 reset-names = "pci", 3230 "link_down"; 3231 3232 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3233 required-opps = <&rpmhpd_opp_nom>; 3234 3235 phys = <&pcie4_phy>; 3236 phy-names = "pciephy"; 3237 3238 status = "disabled"; 3239 3240 pcie4_port0: pcie@0 { 3241 device_type = "pci"; 3242 reg = <0x0 0x0 0x0 0x0 0x0>; 3243 bus-range = <0x01 0xff>; 3244 3245 #address-cells = <3>; 3246 #size-cells = <2>; 3247 ranges; 3248 }; 3249 }; 3250 3251 pcie4_phy: phy@1c0e000 { 3252 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3253 reg = <0 0x01c0e000 0 0x2000>; 3254 3255 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3256 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3257 <&rpmhcc RPMH_CXO_CLK>, 3258 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3259 <&gcc GCC_PCIE_4_PIPE_CLK>; 3260 clock-names = "aux", 3261 "cfg_ahb", 3262 "ref", 3263 "rchng", 3264 "pipe"; 3265 3266 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 3267 reset-names = "phy"; 3268 3269 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3270 assigned-clock-rates = <100000000>; 3271 3272 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3273 3274 #clock-cells = <0>; 3275 clock-output-names = "pcie4_pipe_clk"; 3276 3277 #phy-cells = <0>; 3278 3279 status = "disabled"; 3280 }; 3281 3282 tcsr_mutex: hwlock@1f40000 { 3283 compatible = "qcom,tcsr-mutex"; 3284 reg = <0 0x01f40000 0 0x20000>; 3285 #hwlock-cells = <1>; 3286 }; 3287 3288 tcsr: clock-controller@1fc0000 { 3289 compatible = "qcom,x1e80100-tcsr", "syscon"; 3290 reg = <0 0x01fc0000 0 0x30000>; 3291 clocks = <&rpmhcc RPMH_CXO_CLK>; 3292 #clock-cells = <1>; 3293 #reset-cells = <1>; 3294 }; 3295 3296 gpu: gpu@3d00000 { 3297 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3298 reg = <0x0 0x03d00000 0x0 0x40000>, 3299 <0x0 0x03d9e000 0x0 0x1000>, 3300 <0x0 0x03d61000 0x0 0x800>; 3301 3302 reg-names = "kgsl_3d0_reg_memory", 3303 "cx_mem", 3304 "cx_dbgc"; 3305 3306 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3307 3308 iommus = <&adreno_smmu 0 0x0>, 3309 <&adreno_smmu 1 0x0>; 3310 3311 operating-points-v2 = <&gpu_opp_table>; 3312 3313 qcom,gmu = <&gmu>; 3314 #cooling-cells = <2>; 3315 3316 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3317 interconnect-names = "gfx-mem"; 3318 3319 status = "disabled"; 3320 3321 zap-shader { 3322 memory-region = <&gpu_microcode_mem>; 3323 }; 3324 3325 gpu_opp_table: opp-table { 3326 compatible = "operating-points-v2"; 3327 3328 opp-1100000000 { 3329 opp-hz = /bits/ 64 <1100000000>; 3330 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3331 opp-peak-kBps = <16500000>; 3332 }; 3333 3334 opp-1000000000 { 3335 opp-hz = /bits/ 64 <1000000000>; 3336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3337 opp-peak-kBps = <14398438>; 3338 }; 3339 3340 opp-925000000 { 3341 opp-hz = /bits/ 64 <925000000>; 3342 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3343 opp-peak-kBps = <14398438>; 3344 }; 3345 3346 opp-800000000 { 3347 opp-hz = /bits/ 64 <800000000>; 3348 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3349 opp-peak-kBps = <12449219>; 3350 }; 3351 3352 opp-744000000 { 3353 opp-hz = /bits/ 64 <744000000>; 3354 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3355 opp-peak-kBps = <10687500>; 3356 }; 3357 3358 opp-687000000 { 3359 opp-hz = /bits/ 64 <687000000>; 3360 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3361 opp-peak-kBps = <8171875>; 3362 }; 3363 3364 opp-550000000 { 3365 opp-hz = /bits/ 64 <550000000>; 3366 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3367 opp-peak-kBps = <6074219>; 3368 }; 3369 3370 opp-390000000 { 3371 opp-hz = /bits/ 64 <390000000>; 3372 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3373 opp-peak-kBps = <3000000>; 3374 }; 3375 3376 opp-300000000 { 3377 opp-hz = /bits/ 64 <300000000>; 3378 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3379 opp-peak-kBps = <2136719>; 3380 }; 3381 }; 3382 }; 3383 3384 gmu: gmu@3d6a000 { 3385 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 3386 reg = <0x0 0x03d6a000 0x0 0x35000>, 3387 <0x0 0x03d50000 0x0 0x10000>, 3388 <0x0 0x0b280000 0x0 0x10000>; 3389 reg-names = "gmu", "rscc", "gmu_pdc"; 3390 3391 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3393 interrupt-names = "hfi", "gmu"; 3394 3395 clocks = <&gpucc GPU_CC_AHB_CLK>, 3396 <&gpucc GPU_CC_CX_GMU_CLK>, 3397 <&gpucc GPU_CC_CXO_CLK>, 3398 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3399 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3400 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3401 <&gpucc GPU_CC_DEMET_CLK>; 3402 clock-names = "ahb", 3403 "gmu", 3404 "cxo", 3405 "axi", 3406 "memnoc", 3407 "hub", 3408 "demet"; 3409 3410 power-domains = <&gpucc GPU_CX_GDSC>, 3411 <&gpucc GPU_GX_GDSC>; 3412 power-domain-names = "cx", 3413 "gx"; 3414 3415 iommus = <&adreno_smmu 5 0x0>; 3416 3417 qcom,qmp = <&aoss_qmp>; 3418 3419 operating-points-v2 = <&gmu_opp_table>; 3420 3421 gmu_opp_table: opp-table { 3422 compatible = "operating-points-v2"; 3423 3424 opp-550000000 { 3425 opp-hz = /bits/ 64 <550000000>; 3426 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3427 }; 3428 3429 opp-220000000 { 3430 opp-hz = /bits/ 64 <220000000>; 3431 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3432 }; 3433 }; 3434 }; 3435 3436 gpucc: clock-controller@3d90000 { 3437 compatible = "qcom,x1e80100-gpucc"; 3438 reg = <0 0x03d90000 0 0xa000>; 3439 clocks = <&bi_tcxo_div2>, 3440 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 3441 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 3442 #clock-cells = <1>; 3443 #reset-cells = <1>; 3444 #power-domain-cells = <1>; 3445 }; 3446 3447 adreno_smmu: iommu@3da0000 { 3448 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 3449 "qcom,smmu-500", "arm,mmu-500"; 3450 reg = <0x0 0x03da0000 0x0 0x40000>; 3451 #iommu-cells = <2>; 3452 #global-interrupts = <1>; 3453 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 3479 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3480 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3481 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3482 <&gpucc GPU_CC_AHB_CLK>; 3483 clock-names = "hlos", 3484 "bus", 3485 "iface", 3486 "ahb"; 3487 power-domains = <&gpucc GPU_CX_GDSC>; 3488 dma-coherent; 3489 }; 3490 3491 gem_noc: interconnect@26400000 { 3492 compatible = "qcom,x1e80100-gem-noc"; 3493 reg = <0 0x26400000 0 0x311200>; 3494 3495 qcom,bcm-voters = <&apps_bcm_voter>; 3496 3497 #interconnect-cells = <2>; 3498 }; 3499 3500 nsp_noc: interconnect@320c0000 { 3501 compatible = "qcom,x1e80100-nsp-noc"; 3502 reg = <0 0x320C0000 0 0xe080>; 3503 3504 qcom,bcm-voters = <&apps_bcm_voter>; 3505 3506 #interconnect-cells = <2>; 3507 }; 3508 3509 lpass_wsa2macro: codec@6aa0000 { 3510 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3511 reg = <0 0x06aa0000 0 0x1000>; 3512 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3513 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3514 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3515 <&lpass_vamacro>; 3516 clock-names = "mclk", 3517 "macro", 3518 "dcodec", 3519 "fsgen"; 3520 3521 #clock-cells = <0>; 3522 clock-output-names = "wsa2-mclk"; 3523 #sound-dai-cells = <1>; 3524 sound-name-prefix = "WSA2"; 3525 }; 3526 3527 swr3: soundwire@6ab0000 { 3528 compatible = "qcom,soundwire-v2.0.0"; 3529 reg = <0 0x06ab0000 0 0x10000>; 3530 clocks = <&lpass_wsa2macro>; 3531 clock-names = "iface"; 3532 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 3533 label = "WSA2"; 3534 3535 pinctrl-0 = <&wsa2_swr_active>; 3536 pinctrl-names = "default"; 3537 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 3538 reset-names = "swr_audio_cgcr"; 3539 3540 qcom,din-ports = <4>; 3541 qcom,dout-ports = <9>; 3542 3543 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3544 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3545 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3546 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3547 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3548 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3549 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3550 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3551 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3552 3553 #address-cells = <2>; 3554 #size-cells = <0>; 3555 #sound-dai-cells = <1>; 3556 status = "disabled"; 3557 }; 3558 3559 lpass_rxmacro: codec@6ac0000 { 3560 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 3561 reg = <0 0x06ac0000 0 0x1000>; 3562 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3563 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3564 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3565 <&lpass_vamacro>; 3566 clock-names = "mclk", 3567 "macro", 3568 "dcodec", 3569 "fsgen"; 3570 3571 #clock-cells = <0>; 3572 clock-output-names = "mclk"; 3573 #sound-dai-cells = <1>; 3574 }; 3575 3576 swr1: soundwire@6ad0000 { 3577 compatible = "qcom,soundwire-v2.0.0"; 3578 reg = <0 0x06ad0000 0 0x10000>; 3579 clocks = <&lpass_rxmacro>; 3580 clock-names = "iface"; 3581 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3582 label = "RX"; 3583 3584 pinctrl-0 = <&rx_swr_active>; 3585 pinctrl-names = "default"; 3586 3587 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 3588 reset-names = "swr_audio_cgcr"; 3589 qcom,din-ports = <1>; 3590 qcom,dout-ports = <11>; 3591 3592 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3593 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3594 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3595 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3596 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3597 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3598 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3599 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3600 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3601 3602 #address-cells = <2>; 3603 #size-cells = <0>; 3604 #sound-dai-cells = <1>; 3605 status = "disabled"; 3606 }; 3607 3608 lpass_txmacro: codec@6ae0000 { 3609 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 3610 reg = <0 0x06ae0000 0 0x1000>; 3611 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3612 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3613 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3614 <&lpass_vamacro>; 3615 clock-names = "mclk", 3616 "macro", 3617 "dcodec", 3618 "fsgen"; 3619 3620 #clock-cells = <0>; 3621 clock-output-names = "mclk"; 3622 #sound-dai-cells = <1>; 3623 }; 3624 3625 lpass_wsamacro: codec@6b00000 { 3626 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3627 reg = <0 0x06b00000 0 0x1000>; 3628 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3629 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3630 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3631 <&lpass_vamacro>; 3632 clock-names = "mclk", 3633 "macro", 3634 "dcodec", 3635 "fsgen"; 3636 3637 #clock-cells = <0>; 3638 clock-output-names = "mclk"; 3639 #sound-dai-cells = <1>; 3640 sound-name-prefix = "WSA"; 3641 }; 3642 3643 swr0: soundwire@6b10000 { 3644 compatible = "qcom,soundwire-v2.0.0"; 3645 reg = <0 0x06b10000 0 0x10000>; 3646 clocks = <&lpass_wsamacro>; 3647 clock-names = "iface"; 3648 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3649 label = "WSA"; 3650 3651 pinctrl-0 = <&wsa_swr_active>; 3652 pinctrl-names = "default"; 3653 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 3654 reset-names = "swr_audio_cgcr"; 3655 3656 qcom,din-ports = <4>; 3657 qcom,dout-ports = <9>; 3658 3659 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3660 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3661 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3662 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3663 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3664 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3665 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3666 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3667 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3668 3669 #address-cells = <2>; 3670 #size-cells = <0>; 3671 #sound-dai-cells = <1>; 3672 status = "disabled"; 3673 }; 3674 3675 lpass_audiocc: clock-controller@6b6c000 { 3676 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 3677 reg = <0 0x06b6c000 0 0x1000>; 3678 #clock-cells = <1>; 3679 #reset-cells = <1>; 3680 }; 3681 3682 swr2: soundwire@6d30000 { 3683 compatible = "qcom,soundwire-v2.0.0"; 3684 reg = <0 0x06d30000 0 0x10000>; 3685 clocks = <&lpass_txmacro>; 3686 clock-names = "iface"; 3687 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3689 interrupt-names = "core", "wakeup"; 3690 label = "TX"; 3691 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 3692 reset-names = "swr_audio_cgcr"; 3693 3694 pinctrl-0 = <&tx_swr_active>; 3695 pinctrl-names = "default"; 3696 3697 qcom,din-ports = <4>; 3698 qcom,dout-ports = <1>; 3699 3700 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 3701 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 3702 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 3703 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3704 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3705 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3706 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3707 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3708 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 3709 3710 #address-cells = <2>; 3711 #size-cells = <0>; 3712 #sound-dai-cells = <1>; 3713 status = "disabled"; 3714 }; 3715 3716 lpass_vamacro: codec@6d44000 { 3717 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 3718 reg = <0 0x06d44000 0 0x1000>; 3719 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3720 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3721 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3722 clock-names = "mclk", 3723 "macro", 3724 "dcodec"; 3725 3726 #clock-cells = <0>; 3727 clock-output-names = "fsgen"; 3728 #sound-dai-cells = <1>; 3729 }; 3730 3731 lpass_tlmm: pinctrl@6e80000 { 3732 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 3733 reg = <0 0x06e80000 0 0x20000>, 3734 <0 0x07250000 0 0x10000>; 3735 3736 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3737 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3738 clock-names = "core", "audio"; 3739 3740 gpio-controller; 3741 #gpio-cells = <2>; 3742 gpio-ranges = <&lpass_tlmm 0 0 23>; 3743 3744 tx_swr_active: tx-swr-active-state { 3745 clk-pins { 3746 pins = "gpio0"; 3747 function = "swr_tx_clk"; 3748 drive-strength = <2>; 3749 slew-rate = <1>; 3750 bias-disable; 3751 }; 3752 3753 data-pins { 3754 pins = "gpio1", "gpio2"; 3755 function = "swr_tx_data"; 3756 drive-strength = <2>; 3757 slew-rate = <1>; 3758 bias-bus-hold; 3759 }; 3760 }; 3761 3762 rx_swr_active: rx-swr-active-state { 3763 clk-pins { 3764 pins = "gpio3"; 3765 function = "swr_rx_clk"; 3766 drive-strength = <2>; 3767 slew-rate = <1>; 3768 bias-disable; 3769 }; 3770 3771 data-pins { 3772 pins = "gpio4", "gpio5"; 3773 function = "swr_rx_data"; 3774 drive-strength = <2>; 3775 slew-rate = <1>; 3776 bias-bus-hold; 3777 }; 3778 }; 3779 3780 dmic01_default: dmic01-default-state { 3781 clk-pins { 3782 pins = "gpio6"; 3783 function = "dmic1_clk"; 3784 drive-strength = <8>; 3785 output-high; 3786 }; 3787 3788 data-pins { 3789 pins = "gpio7"; 3790 function = "dmic1_data"; 3791 drive-strength = <8>; 3792 input-enable; 3793 }; 3794 }; 3795 3796 dmic23_default: dmic23-default-state { 3797 clk-pins { 3798 pins = "gpio8"; 3799 function = "dmic2_clk"; 3800 drive-strength = <8>; 3801 output-high; 3802 }; 3803 3804 data-pins { 3805 pins = "gpio9"; 3806 function = "dmic2_data"; 3807 drive-strength = <8>; 3808 input-enable; 3809 }; 3810 }; 3811 3812 wsa_swr_active: wsa-swr-active-state { 3813 clk-pins { 3814 pins = "gpio10"; 3815 function = "wsa_swr_clk"; 3816 drive-strength = <2>; 3817 slew-rate = <1>; 3818 bias-disable; 3819 }; 3820 3821 data-pins { 3822 pins = "gpio11"; 3823 function = "wsa_swr_data"; 3824 drive-strength = <2>; 3825 slew-rate = <1>; 3826 bias-bus-hold; 3827 }; 3828 }; 3829 3830 wsa2_swr_active: wsa2-swr-active-state { 3831 clk-pins { 3832 pins = "gpio15"; 3833 function = "wsa2_swr_clk"; 3834 drive-strength = <2>; 3835 slew-rate = <1>; 3836 bias-disable; 3837 }; 3838 3839 data-pins { 3840 pins = "gpio16"; 3841 function = "wsa2_swr_data"; 3842 drive-strength = <2>; 3843 slew-rate = <1>; 3844 bias-bus-hold; 3845 }; 3846 }; 3847 }; 3848 3849 lpasscc: clock-controller@6ea0000 { 3850 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 3851 reg = <0 0x06ea0000 0 0x12000>; 3852 #clock-cells = <1>; 3853 #reset-cells = <1>; 3854 }; 3855 3856 lpass_ag_noc: interconnect@7e40000 { 3857 compatible = "qcom,x1e80100-lpass-ag-noc"; 3858 reg = <0 0x07e40000 0 0xe080>; 3859 3860 qcom,bcm-voters = <&apps_bcm_voter>; 3861 3862 #interconnect-cells = <2>; 3863 }; 3864 3865 lpass_lpiaon_noc: interconnect@7400000 { 3866 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 3867 reg = <0 0x07400000 0 0x19080>; 3868 3869 qcom,bcm-voters = <&apps_bcm_voter>; 3870 3871 #interconnect-cells = <2>; 3872 }; 3873 3874 lpass_lpicx_noc: interconnect@7430000 { 3875 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 3876 reg = <0 0x07430000 0 0x3A200>; 3877 3878 qcom,bcm-voters = <&apps_bcm_voter>; 3879 3880 #interconnect-cells = <2>; 3881 }; 3882 3883 usb_2_hsphy: phy@88e0000 { 3884 compatible = "qcom,x1e80100-snps-eusb2-phy", 3885 "qcom,sm8550-snps-eusb2-phy"; 3886 reg = <0 0x088e0000 0 0x154>; 3887 #phy-cells = <0>; 3888 3889 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 3890 clock-names = "ref"; 3891 3892 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 3893 3894 status = "disabled"; 3895 }; 3896 3897 usb_mp_hsphy0: phy@88e1000 { 3898 compatible = "qcom,x1e80100-snps-eusb2-phy", 3899 "qcom,sm8550-snps-eusb2-phy"; 3900 reg = <0 0x088e1000 0 0x154>; 3901 #phy-cells = <0>; 3902 3903 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 3904 clock-names = "ref"; 3905 3906 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 3907 3908 status = "disabled"; 3909 }; 3910 3911 usb_mp_hsphy1: phy@88e2000 { 3912 compatible = "qcom,x1e80100-snps-eusb2-phy", 3913 "qcom,sm8550-snps-eusb2-phy"; 3914 reg = <0 0x088e2000 0 0x154>; 3915 #phy-cells = <0>; 3916 3917 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 3918 clock-names = "ref"; 3919 3920 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 3921 3922 status = "disabled"; 3923 }; 3924 3925 usb_mp_qmpphy0: phy@88e3000 { 3926 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 3927 reg = <0 0x088e3000 0 0x2000>; 3928 3929 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3930 <&rpmhcc RPMH_CXO_CLK>, 3931 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3932 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 3933 clock-names = "aux", 3934 "ref", 3935 "com_aux", 3936 "pipe"; 3937 3938 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 3939 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 3940 reset-names = "phy", 3941 "phy_phy"; 3942 3943 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 3944 3945 #clock-cells = <0>; 3946 clock-output-names = "usb_mp_phy0_pipe_clk"; 3947 3948 #phy-cells = <0>; 3949 3950 status = "disabled"; 3951 }; 3952 3953 usb_mp_qmpphy1: phy@88e5000 { 3954 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 3955 reg = <0 0x088e5000 0 0x2000>; 3956 3957 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3958 <&rpmhcc RPMH_CXO_CLK>, 3959 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3960 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 3961 clock-names = "aux", 3962 "ref", 3963 "com_aux", 3964 "pipe"; 3965 3966 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 3967 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 3968 reset-names = "phy", 3969 "phy_phy"; 3970 3971 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 3972 3973 #clock-cells = <0>; 3974 clock-output-names = "usb_mp_phy1_pipe_clk"; 3975 3976 #phy-cells = <0>; 3977 3978 status = "disabled"; 3979 }; 3980 3981 usb_1_ss2: usb@a0f8800 { 3982 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3983 reg = <0 0x0a0f8800 0 0x400>; 3984 3985 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 3986 <&gcc GCC_USB30_TERT_MASTER_CLK>, 3987 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 3988 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 3989 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 3990 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3991 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 3992 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 3993 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3994 clock-names = "cfg_noc", 3995 "core", 3996 "iface", 3997 "sleep", 3998 "mock_utmi", 3999 "noc_aggr", 4000 "noc_aggr_north", 4001 "noc_aggr_south", 4002 "noc_sys"; 4003 4004 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4005 <&gcc GCC_USB30_TERT_MASTER_CLK>; 4006 assigned-clock-rates = <19200000>, 4007 <200000000>; 4008 4009 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4010 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 4011 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4012 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 4013 interrupt-names = "pwr_event", 4014 "dp_hs_phy_irq", 4015 "dm_hs_phy_irq", 4016 "ss_phy_irq"; 4017 4018 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4019 required-opps = <&rpmhpd_opp_nom>; 4020 4021 resets = <&gcc GCC_USB30_TERT_BCR>; 4022 4023 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 4024 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4025 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4026 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; 4027 interconnect-names = "usb-ddr", 4028 "apps-usb"; 4029 4030 wakeup-source; 4031 4032 #address-cells = <2>; 4033 #size-cells = <2>; 4034 ranges; 4035 4036 status = "disabled"; 4037 4038 usb_1_ss2_dwc3: usb@a000000 { 4039 compatible = "snps,dwc3"; 4040 reg = <0 0x0a000000 0 0xcd00>; 4041 4042 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 4043 4044 iommus = <&apps_smmu 0x14a0 0x0>; 4045 4046 phys = <&usb_1_ss2_hsphy>, 4047 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 4048 phy-names = "usb2-phy", 4049 "usb3-phy"; 4050 4051 snps,dis_u2_susphy_quirk; 4052 snps,dis_enblslpm_quirk; 4053 snps,usb3_lpm_capable; 4054 4055 dma-coherent; 4056 4057 ports { 4058 #address-cells = <1>; 4059 #size-cells = <0>; 4060 4061 port@0 { 4062 reg = <0>; 4063 4064 usb_1_ss2_dwc3_hs: endpoint { 4065 }; 4066 }; 4067 4068 port@1 { 4069 reg = <1>; 4070 4071 usb_1_ss2_dwc3_ss: endpoint { 4072 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 4073 }; 4074 }; 4075 }; 4076 }; 4077 }; 4078 4079 usb_2: usb@a2f8800 { 4080 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4081 reg = <0 0x0a2f8800 0 0x400>; 4082 #address-cells = <2>; 4083 #size-cells = <2>; 4084 ranges; 4085 4086 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4087 <&gcc GCC_USB20_MASTER_CLK>, 4088 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4089 <&gcc GCC_USB20_SLEEP_CLK>, 4090 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4091 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4092 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4093 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4094 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4095 clock-names = "cfg_noc", 4096 "core", 4097 "iface", 4098 "sleep", 4099 "mock_utmi", 4100 "noc_aggr", 4101 "noc_aggr_north", 4102 "noc_aggr_south", 4103 "noc_sys"; 4104 4105 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4106 <&gcc GCC_USB20_MASTER_CLK>; 4107 assigned-clock-rates = <19200000>, <200000000>; 4108 4109 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4110 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 4111 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 4112 interrupt-names = "pwr_event", 4113 "dp_hs_phy_irq", 4114 "dm_hs_phy_irq"; 4115 4116 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4117 required-opps = <&rpmhpd_opp_nom>; 4118 4119 resets = <&gcc GCC_USB20_PRIM_BCR>; 4120 4121 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4122 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4124 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 4125 interconnect-names = "usb-ddr", 4126 "apps-usb"; 4127 4128 wakeup-source; 4129 4130 status = "disabled"; 4131 4132 usb_2_dwc3: usb@a200000 { 4133 compatible = "snps,dwc3"; 4134 reg = <0 0x0a200000 0 0xcd00>; 4135 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 4136 iommus = <&apps_smmu 0x14e0 0x0>; 4137 phys = <&usb_2_hsphy>; 4138 phy-names = "usb2-phy"; 4139 maximum-speed = "high-speed"; 4140 4141 ports { 4142 #address-cells = <1>; 4143 #size-cells = <0>; 4144 4145 port@0 { 4146 reg = <0>; 4147 4148 usb_2_dwc3_hs: endpoint { 4149 }; 4150 }; 4151 }; 4152 }; 4153 }; 4154 4155 usb_mp: usb@a4f8800 { 4156 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; 4157 reg = <0 0x0a4f8800 0 0x400>; 4158 4159 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4160 <&gcc GCC_USB30_MP_MASTER_CLK>, 4161 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4162 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4163 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4164 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4165 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4166 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4167 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4168 clock-names = "cfg_noc", 4169 "core", 4170 "iface", 4171 "sleep", 4172 "mock_utmi", 4173 "noc_aggr", 4174 "noc_aggr_north", 4175 "noc_aggr_south", 4176 "noc_sys"; 4177 4178 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4179 <&gcc GCC_USB30_MP_MASTER_CLK>; 4180 assigned-clock-rates = <19200000>, 4181 <200000000>; 4182 4183 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 4184 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 4185 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 4186 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 4187 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 4188 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 4189 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 4190 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 4191 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 4192 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 4193 interrupt-names = "pwr_event_1", "pwr_event_2", 4194 "hs_phy_1", "hs_phy_2", 4195 "dp_hs_phy_1", "dm_hs_phy_1", 4196 "dp_hs_phy_2", "dm_hs_phy_2", 4197 "ss_phy_1", "ss_phy_2"; 4198 4199 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4200 required-opps = <&rpmhpd_opp_nom>; 4201 4202 resets = <&gcc GCC_USB30_MP_BCR>; 4203 4204 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 4205 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4206 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4207 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>; 4208 interconnect-names = "usb-ddr", 4209 "apps-usb"; 4210 4211 wakeup-source; 4212 4213 #address-cells = <2>; 4214 #size-cells = <2>; 4215 ranges; 4216 4217 status = "disabled"; 4218 4219 usb_mp_dwc3: usb@a400000 { 4220 compatible = "snps,dwc3"; 4221 reg = <0 0x0a400000 0 0xcd00>; 4222 4223 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 4224 4225 iommus = <&apps_smmu 0x1400 0x0>; 4226 4227 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 4228 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 4229 phy-names = "usb2-0", "usb3-0", 4230 "usb2-1", "usb3-1"; 4231 dr_mode = "host"; 4232 4233 snps,dis_u2_susphy_quirk; 4234 snps,dis_enblslpm_quirk; 4235 snps,usb3_lpm_capable; 4236 4237 dma-coherent; 4238 }; 4239 }; 4240 4241 usb_1_ss0: usb@a6f8800 { 4242 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4243 reg = <0 0x0a6f8800 0 0x400>; 4244 4245 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4246 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4247 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4248 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4249 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4250 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4251 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 4252 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 4253 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4254 clock-names = "cfg_noc", 4255 "core", 4256 "iface", 4257 "sleep", 4258 "mock_utmi", 4259 "noc_aggr", 4260 "noc_aggr_north", 4261 "noc_aggr_south", 4262 "noc_sys"; 4263 4264 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4265 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4266 assigned-clock-rates = <19200000>, 4267 <200000000>; 4268 4269 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4270 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 4271 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4272 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4273 interrupt-names = "pwr_event", 4274 "dp_hs_phy_irq", 4275 "dm_hs_phy_irq", 4276 "ss_phy_irq"; 4277 4278 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4279 required-opps = <&rpmhpd_opp_nom>; 4280 4281 resets = <&gcc GCC_USB30_PRIM_BCR>; 4282 4283 wakeup-source; 4284 4285 #address-cells = <2>; 4286 #size-cells = <2>; 4287 ranges; 4288 4289 status = "disabled"; 4290 4291 usb_1_ss0_dwc3: usb@a600000 { 4292 compatible = "snps,dwc3"; 4293 reg = <0 0x0a600000 0 0xcd00>; 4294 4295 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 4296 4297 iommus = <&apps_smmu 0x1420 0x0>; 4298 4299 phys = <&usb_1_ss0_hsphy>, 4300 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 4301 phy-names = "usb2-phy", 4302 "usb3-phy"; 4303 4304 snps,dis_u2_susphy_quirk; 4305 snps,dis_enblslpm_quirk; 4306 snps,usb3_lpm_capable; 4307 4308 dma-coherent; 4309 4310 ports { 4311 #address-cells = <1>; 4312 #size-cells = <0>; 4313 4314 port@0 { 4315 reg = <0>; 4316 4317 usb_1_ss0_dwc3_hs: endpoint { 4318 }; 4319 }; 4320 4321 port@1 { 4322 reg = <1>; 4323 4324 usb_1_ss0_dwc3_ss: endpoint { 4325 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 4326 }; 4327 }; 4328 }; 4329 }; 4330 }; 4331 4332 usb_1_ss1: usb@a8f8800 { 4333 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4334 reg = <0 0x0a8f8800 0 0x400>; 4335 4336 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4337 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4338 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4339 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4340 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4341 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4342 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4343 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4344 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4345 clock-names = "cfg_noc", 4346 "core", 4347 "iface", 4348 "sleep", 4349 "mock_utmi", 4350 "noc_aggr", 4351 "noc_aggr_north", 4352 "noc_aggr_south", 4353 "noc_sys"; 4354 4355 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4356 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4357 assigned-clock-rates = <19200000>, 4358 <200000000>; 4359 4360 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 4361 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 4362 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 4363 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 4364 interrupt-names = "pwr_event", 4365 "dp_hs_phy_irq", 4366 "dm_hs_phy_irq", 4367 "ss_phy_irq"; 4368 4369 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4370 required-opps = <&rpmhpd_opp_nom>; 4371 4372 resets = <&gcc GCC_USB30_SEC_BCR>; 4373 4374 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 4375 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4376 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4377 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; 4378 interconnect-names = "usb-ddr", 4379 "apps-usb"; 4380 4381 wakeup-source; 4382 4383 #address-cells = <2>; 4384 #size-cells = <2>; 4385 ranges; 4386 4387 status = "disabled"; 4388 4389 usb_1_ss1_dwc3: usb@a800000 { 4390 compatible = "snps,dwc3"; 4391 reg = <0 0x0a800000 0 0xcd00>; 4392 4393 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 4394 4395 iommus = <&apps_smmu 0x1460 0x0>; 4396 4397 phys = <&usb_1_ss1_hsphy>, 4398 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 4399 phy-names = "usb2-phy", 4400 "usb3-phy"; 4401 4402 snps,dis_u2_susphy_quirk; 4403 snps,dis_enblslpm_quirk; 4404 snps,usb3_lpm_capable; 4405 4406 dma-coherent; 4407 4408 ports { 4409 #address-cells = <1>; 4410 #size-cells = <0>; 4411 4412 port@0 { 4413 reg = <0>; 4414 4415 usb_1_ss1_dwc3_hs: endpoint { 4416 }; 4417 }; 4418 4419 port@1 { 4420 reg = <1>; 4421 4422 usb_1_ss1_dwc3_ss: endpoint { 4423 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 4424 }; 4425 }; 4426 }; 4427 }; 4428 }; 4429 4430 mdss: display-subsystem@ae00000 { 4431 compatible = "qcom,x1e80100-mdss"; 4432 reg = <0 0x0ae00000 0 0x1000>; 4433 reg-names = "mdss"; 4434 4435 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4436 4437 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4438 <&gcc GCC_DISP_HF_AXI_CLK>, 4439 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4440 4441 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4442 4443 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4444 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 4445 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 4446 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4448 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4449 interconnect-names = "mdp0-mem", 4450 "mdp1-mem", 4451 "cpu-cfg"; 4452 4453 power-domains = <&dispcc MDSS_GDSC>; 4454 4455 iommus = <&apps_smmu 0x1c00 0x2>; 4456 4457 interrupt-controller; 4458 #interrupt-cells = <1>; 4459 4460 #address-cells = <2>; 4461 #size-cells = <2>; 4462 ranges; 4463 4464 status = "disabled"; 4465 4466 mdss_mdp: display-controller@ae01000 { 4467 compatible = "qcom,x1e80100-dpu"; 4468 reg = <0 0x0ae01000 0 0x8f000>, 4469 <0 0x0aeb0000 0 0x2008>; 4470 reg-names = "mdp", 4471 "vbif"; 4472 4473 interrupts-extended = <&mdss 0>; 4474 4475 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4476 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4477 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4478 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4479 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4480 clock-names = "nrt_bus", 4481 "iface", 4482 "lut", 4483 "core", 4484 "vsync"; 4485 4486 operating-points-v2 = <&mdp_opp_table>; 4487 4488 power-domains = <&rpmhpd RPMHPD_MMCX>; 4489 4490 ports { 4491 #address-cells = <1>; 4492 #size-cells = <0>; 4493 4494 port@0 { 4495 reg = <0>; 4496 4497 mdss_intf0_out: endpoint { 4498 remote-endpoint = <&mdss_dp0_in>; 4499 }; 4500 }; 4501 4502 port@4 { 4503 reg = <4>; 4504 4505 mdss_intf4_out: endpoint { 4506 remote-endpoint = <&mdss_dp1_in>; 4507 }; 4508 }; 4509 4510 port@5 { 4511 reg = <5>; 4512 4513 mdss_intf5_out: endpoint { 4514 remote-endpoint = <&mdss_dp3_in>; 4515 }; 4516 }; 4517 4518 port@6 { 4519 reg = <6>; 4520 4521 mdss_intf6_out: endpoint { 4522 remote-endpoint = <&mdss_dp2_in>; 4523 }; 4524 }; 4525 }; 4526 4527 mdp_opp_table: opp-table { 4528 compatible = "operating-points-v2"; 4529 4530 opp-200000000 { 4531 opp-hz = /bits/ 64 <200000000>; 4532 required-opps = <&rpmhpd_opp_low_svs>; 4533 }; 4534 4535 opp-325000000 { 4536 opp-hz = /bits/ 64 <325000000>; 4537 required-opps = <&rpmhpd_opp_svs>; 4538 }; 4539 4540 opp-375000000 { 4541 opp-hz = /bits/ 64 <375000000>; 4542 required-opps = <&rpmhpd_opp_svs_l1>; 4543 }; 4544 4545 opp-514000000 { 4546 opp-hz = /bits/ 64 <514000000>; 4547 required-opps = <&rpmhpd_opp_nom>; 4548 }; 4549 4550 opp-575000000 { 4551 opp-hz = /bits/ 64 <575000000>; 4552 required-opps = <&rpmhpd_opp_nom_l1>; 4553 }; 4554 }; 4555 }; 4556 4557 mdss_dp0: displayport-controller@ae90000 { 4558 compatible = "qcom,x1e80100-dp"; 4559 reg = <0 0x0ae90000 0 0x200>, 4560 <0 0x0ae90200 0 0x200>, 4561 <0 0x0ae90400 0 0x600>, 4562 <0 0x0ae91000 0 0x400>, 4563 <0 0x0ae91400 0 0x400>; 4564 4565 interrupts-extended = <&mdss 12>; 4566 4567 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4568 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 4569 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 4570 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4571 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4572 clock-names = "core_iface", 4573 "core_aux", 4574 "ctrl_link", 4575 "ctrl_link_iface", 4576 "stream_pixel"; 4577 4578 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4579 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4580 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4581 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4582 4583 operating-points-v2 = <&mdss_dp0_opp_table>; 4584 4585 power-domains = <&rpmhpd RPMHPD_MMCX>; 4586 4587 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 4588 phy-names = "dp"; 4589 4590 #sound-dai-cells = <0>; 4591 4592 status = "disabled"; 4593 4594 ports { 4595 #address-cells = <1>; 4596 #size-cells = <0>; 4597 4598 port@0 { 4599 reg = <0>; 4600 4601 mdss_dp0_in: endpoint { 4602 remote-endpoint = <&mdss_intf0_out>; 4603 }; 4604 }; 4605 4606 port@1 { 4607 reg = <1>; 4608 4609 mdss_dp0_out: endpoint { 4610 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 4611 }; 4612 }; 4613 }; 4614 4615 mdss_dp0_opp_table: opp-table { 4616 compatible = "operating-points-v2"; 4617 4618 opp-160000000 { 4619 opp-hz = /bits/ 64 <160000000>; 4620 required-opps = <&rpmhpd_opp_low_svs>; 4621 }; 4622 4623 opp-270000000 { 4624 opp-hz = /bits/ 64 <270000000>; 4625 required-opps = <&rpmhpd_opp_svs>; 4626 }; 4627 4628 opp-540000000 { 4629 opp-hz = /bits/ 64 <540000000>; 4630 required-opps = <&rpmhpd_opp_svs_l1>; 4631 }; 4632 4633 opp-810000000 { 4634 opp-hz = /bits/ 64 <810000000>; 4635 required-opps = <&rpmhpd_opp_nom>; 4636 }; 4637 }; 4638 }; 4639 4640 mdss_dp1: displayport-controller@ae98000 { 4641 compatible = "qcom,x1e80100-dp"; 4642 reg = <0 0x0ae98000 0 0x200>, 4643 <0 0x0ae98200 0 0x200>, 4644 <0 0x0ae98400 0 0x600>, 4645 <0 0x0ae99000 0 0x400>, 4646 <0 0x0ae99400 0 0x400>; 4647 4648 interrupts-extended = <&mdss 13>; 4649 4650 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4651 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 4652 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 4653 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4654 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4655 clock-names = "core_iface", 4656 "core_aux", 4657 "ctrl_link", 4658 "ctrl_link_iface", 4659 "stream_pixel"; 4660 4661 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4662 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4663 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4664 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4665 4666 operating-points-v2 = <&mdss_dp1_opp_table>; 4667 4668 power-domains = <&rpmhpd RPMHPD_MMCX>; 4669 4670 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 4671 phy-names = "dp"; 4672 4673 #sound-dai-cells = <0>; 4674 4675 status = "disabled"; 4676 4677 ports { 4678 #address-cells = <1>; 4679 #size-cells = <0>; 4680 4681 port@0 { 4682 reg = <0>; 4683 4684 mdss_dp1_in: endpoint { 4685 remote-endpoint = <&mdss_intf4_out>; 4686 }; 4687 }; 4688 4689 port@1 { 4690 reg = <1>; 4691 4692 mdss_dp1_out: endpoint { 4693 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 4694 }; 4695 }; 4696 }; 4697 4698 mdss_dp1_opp_table: opp-table { 4699 compatible = "operating-points-v2"; 4700 4701 opp-160000000 { 4702 opp-hz = /bits/ 64 <160000000>; 4703 required-opps = <&rpmhpd_opp_low_svs>; 4704 }; 4705 4706 opp-270000000 { 4707 opp-hz = /bits/ 64 <270000000>; 4708 required-opps = <&rpmhpd_opp_svs>; 4709 }; 4710 4711 opp-540000000 { 4712 opp-hz = /bits/ 64 <540000000>; 4713 required-opps = <&rpmhpd_opp_svs_l1>; 4714 }; 4715 4716 opp-810000000 { 4717 opp-hz = /bits/ 64 <810000000>; 4718 required-opps = <&rpmhpd_opp_nom>; 4719 }; 4720 }; 4721 }; 4722 4723 mdss_dp2: displayport-controller@ae9a000 { 4724 compatible = "qcom,x1e80100-dp"; 4725 reg = <0 0x0ae9a000 0 0x200>, 4726 <0 0x0ae9a200 0 0x200>, 4727 <0 0x0ae9a400 0 0x600>, 4728 <0 0x0ae9b000 0 0x400>, 4729 <0 0x0ae9b400 0 0x400>; 4730 4731 interrupts-extended = <&mdss 14>; 4732 4733 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4734 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4735 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 4736 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4737 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4738 clock-names = "core_iface", 4739 "core_aux", 4740 "ctrl_link", 4741 "ctrl_link_iface", 4742 "stream_pixel"; 4743 4744 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4745 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4746 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4747 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4748 4749 operating-points-v2 = <&mdss_dp2_opp_table>; 4750 4751 power-domains = <&rpmhpd RPMHPD_MMCX>; 4752 4753 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 4754 phy-names = "dp"; 4755 4756 #sound-dai-cells = <0>; 4757 4758 status = "disabled"; 4759 4760 ports { 4761 #address-cells = <1>; 4762 #size-cells = <0>; 4763 4764 port@0 { 4765 reg = <0>; 4766 mdss_dp2_in: endpoint { 4767 remote-endpoint = <&mdss_intf6_out>; 4768 }; 4769 }; 4770 4771 port@1 { 4772 reg = <1>; 4773 4774 mdss_dp2_out: endpoint { 4775 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 4776 }; 4777 }; 4778 }; 4779 4780 mdss_dp2_opp_table: opp-table { 4781 compatible = "operating-points-v2"; 4782 4783 opp-160000000 { 4784 opp-hz = /bits/ 64 <160000000>; 4785 required-opps = <&rpmhpd_opp_low_svs>; 4786 }; 4787 4788 opp-270000000 { 4789 opp-hz = /bits/ 64 <270000000>; 4790 required-opps = <&rpmhpd_opp_svs>; 4791 }; 4792 4793 opp-540000000 { 4794 opp-hz = /bits/ 64 <540000000>; 4795 required-opps = <&rpmhpd_opp_svs_l1>; 4796 }; 4797 4798 opp-810000000 { 4799 opp-hz = /bits/ 64 <810000000>; 4800 required-opps = <&rpmhpd_opp_nom>; 4801 }; 4802 }; 4803 }; 4804 4805 mdss_dp3: displayport-controller@aea0000 { 4806 compatible = "qcom,x1e80100-dp"; 4807 reg = <0 0x0aea0000 0 0x200>, 4808 <0 0x0aea0200 0 0x200>, 4809 <0 0x0aea0400 0 0x600>, 4810 <0 0x0aea1000 0 0x400>, 4811 <0 0x0aea1400 0 0x400>; 4812 4813 interrupts-extended = <&mdss 15>; 4814 4815 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4816 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4817 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4818 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4819 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4820 clock-names = "core_iface", 4821 "core_aux", 4822 "ctrl_link", 4823 "ctrl_link_iface", 4824 "stream_pixel"; 4825 4826 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4827 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4828 assigned-clock-parents = <&mdss_dp3_phy 0>, 4829 <&mdss_dp3_phy 1>; 4830 4831 operating-points-v2 = <&mdss_dp3_opp_table>; 4832 4833 power-domains = <&rpmhpd RPMHPD_MMCX>; 4834 4835 phys = <&mdss_dp3_phy>; 4836 phy-names = "dp"; 4837 4838 #sound-dai-cells = <0>; 4839 4840 status = "disabled"; 4841 4842 ports { 4843 #address-cells = <1>; 4844 #size-cells = <0>; 4845 4846 port@0 { 4847 reg = <0>; 4848 4849 mdss_dp3_in: endpoint { 4850 remote-endpoint = <&mdss_intf5_out>; 4851 }; 4852 }; 4853 4854 port@1 { 4855 reg = <1>; 4856 }; 4857 }; 4858 4859 mdss_dp3_opp_table: opp-table { 4860 compatible = "operating-points-v2"; 4861 4862 opp-160000000 { 4863 opp-hz = /bits/ 64 <160000000>; 4864 required-opps = <&rpmhpd_opp_low_svs>; 4865 }; 4866 4867 opp-270000000 { 4868 opp-hz = /bits/ 64 <270000000>; 4869 required-opps = <&rpmhpd_opp_svs>; 4870 }; 4871 4872 opp-540000000 { 4873 opp-hz = /bits/ 64 <540000000>; 4874 required-opps = <&rpmhpd_opp_svs_l1>; 4875 }; 4876 4877 opp-810000000 { 4878 opp-hz = /bits/ 64 <810000000>; 4879 required-opps = <&rpmhpd_opp_nom>; 4880 }; 4881 }; 4882 }; 4883 4884 }; 4885 4886 mdss_dp2_phy: phy@aec2a00 { 4887 compatible = "qcom,x1e80100-dp-phy"; 4888 reg = <0 0x0aec2a00 0 0x19c>, 4889 <0 0x0aec2200 0 0xec>, 4890 <0 0x0aec2600 0 0xec>, 4891 <0 0x0aec2000 0 0x1c8>; 4892 4893 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4894 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4895 clock-names = "aux", 4896 "cfg_ahb"; 4897 4898 power-domains = <&rpmhpd RPMHPD_MX>; 4899 4900 #clock-cells = <1>; 4901 #phy-cells = <0>; 4902 4903 status = "disabled"; 4904 }; 4905 4906 mdss_dp3_phy: phy@aec5a00 { 4907 compatible = "qcom,x1e80100-dp-phy"; 4908 reg = <0 0x0aec5a00 0 0x19c>, 4909 <0 0x0aec5200 0 0xec>, 4910 <0 0x0aec5600 0 0xec>, 4911 <0 0x0aec5000 0 0x1c8>; 4912 4913 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4914 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4915 clock-names = "aux", 4916 "cfg_ahb"; 4917 4918 power-domains = <&rpmhpd RPMHPD_MX>; 4919 4920 #clock-cells = <1>; 4921 #phy-cells = <0>; 4922 4923 status = "disabled"; 4924 }; 4925 4926 dispcc: clock-controller@af00000 { 4927 compatible = "qcom,x1e80100-dispcc"; 4928 reg = <0 0x0af00000 0 0x20000>; 4929 clocks = <&bi_tcxo_div2>, 4930 <&bi_tcxo_ao_div2>, 4931 <&gcc GCC_DISP_AHB_CLK>, 4932 <&sleep_clk>, 4933 <0>, /* dsi0 */ 4934 <0>, 4935 <0>, /* dsi1 */ 4936 <0>, 4937 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 4938 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4939 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 4940 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4941 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 4942 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4943 <&mdss_dp3_phy 0>, /* dp3 */ 4944 <&mdss_dp3_phy 1>; 4945 power-domains = <&rpmhpd RPMHPD_MMCX>; 4946 required-opps = <&rpmhpd_opp_low_svs>; 4947 #clock-cells = <1>; 4948 #reset-cells = <1>; 4949 #power-domain-cells = <1>; 4950 }; 4951 4952 pdc: interrupt-controller@b220000 { 4953 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 4954 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4955 4956 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 4957 <47 522 52>, <99 609 32>, 4958 <131 717 12>, <143 816 19>; 4959 #interrupt-cells = <2>; 4960 interrupt-parent = <&intc>; 4961 interrupt-controller; 4962 }; 4963 4964 aoss_qmp: power-management@c300000 { 4965 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 4966 reg = <0 0x0c300000 0 0x400>; 4967 interrupt-parent = <&ipcc>; 4968 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4969 IRQ_TYPE_EDGE_RISING>; 4970 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4971 4972 #clock-cells = <0>; 4973 }; 4974 4975 sram@c3f0000 { 4976 compatible = "qcom,rpmh-stats"; 4977 reg = <0 0x0c3f0000 0 0x400>; 4978 }; 4979 4980 spmi: arbiter@c400000 { 4981 compatible = "qcom,x1e80100-spmi-pmic-arb"; 4982 reg = <0 0x0c400000 0 0x3000>, 4983 <0 0x0c500000 0 0x400000>, 4984 <0 0x0c440000 0 0x80000>; 4985 reg-names = "core", "chnls", "obsrvr"; 4986 4987 qcom,ee = <0>; 4988 qcom,channel = <0>; 4989 4990 #address-cells = <2>; 4991 #size-cells = <2>; 4992 ranges; 4993 4994 spmi_bus0: spmi@c42d000 { 4995 reg = <0 0x0c42d000 0 0x4000>, 4996 <0 0x0c4c0000 0 0x10000>; 4997 reg-names = "cnfg", "intr"; 4998 4999 interrupt-names = "periph_irq"; 5000 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5001 interrupt-controller; 5002 #interrupt-cells = <4>; 5003 5004 #address-cells = <2>; 5005 #size-cells = <0>; 5006 }; 5007 5008 spmi_bus1: spmi@c432000 { 5009 reg = <0 0x0c432000 0 0x4000>, 5010 <0 0x0c4d0000 0 0x10000>; 5011 reg-names = "cnfg", "intr"; 5012 5013 interrupt-names = "periph_irq"; 5014 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5015 interrupt-controller; 5016 #interrupt-cells = <4>; 5017 5018 #address-cells = <2>; 5019 #size-cells = <0>; 5020 }; 5021 }; 5022 5023 tlmm: pinctrl@f100000 { 5024 compatible = "qcom,x1e80100-tlmm"; 5025 reg = <0 0x0f100000 0 0xf00000>; 5026 5027 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5028 5029 gpio-controller; 5030 #gpio-cells = <2>; 5031 5032 interrupt-controller; 5033 #interrupt-cells = <2>; 5034 5035 gpio-ranges = <&tlmm 0 0 239>; 5036 wakeup-parent = <&pdc>; 5037 5038 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5039 /* SDA, SCL */ 5040 pins = "gpio0", "gpio1"; 5041 function = "qup0_se0"; 5042 drive-strength = <2>; 5043 bias-pull-up = <2200>; 5044 }; 5045 5046 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5047 /* SDA, SCL */ 5048 pins = "gpio4", "gpio5"; 5049 function = "qup0_se1"; 5050 drive-strength = <2>; 5051 bias-pull-up = <2200>; 5052 }; 5053 5054 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5055 /* SDA, SCL */ 5056 pins = "gpio8", "gpio9"; 5057 function = "qup0_se2"; 5058 drive-strength = <2>; 5059 bias-pull-up = <2200>; 5060 }; 5061 5062 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5063 /* SDA, SCL */ 5064 pins = "gpio12", "gpio13"; 5065 function = "qup0_se3"; 5066 drive-strength = <2>; 5067 bias-pull-up = <2200>; 5068 }; 5069 5070 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5071 /* SDA, SCL */ 5072 pins = "gpio16", "gpio17"; 5073 function = "qup0_se4"; 5074 drive-strength = <2>; 5075 bias-pull-up = <2200>; 5076 }; 5077 5078 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5079 /* SDA, SCL */ 5080 pins = "gpio20", "gpio21"; 5081 function = "qup0_se5"; 5082 drive-strength = <2>; 5083 bias-pull-up = <2200>; 5084 }; 5085 5086 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5087 /* SDA, SCL */ 5088 pins = "gpio24", "gpio25"; 5089 function = "qup0_se6"; 5090 drive-strength = <2>; 5091 bias-pull-up = <2200>; 5092 }; 5093 5094 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5095 /* SDA, SCL */ 5096 pins = "gpio14", "gpio15"; 5097 function = "qup0_se7"; 5098 drive-strength = <2>; 5099 bias-pull-up = <2200>; 5100 }; 5101 5102 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5103 /* SDA, SCL */ 5104 pins = "gpio32", "gpio33"; 5105 function = "qup1_se0"; 5106 drive-strength = <2>; 5107 bias-pull-up = <2200>; 5108 }; 5109 5110 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5111 /* SDA, SCL */ 5112 pins = "gpio36", "gpio37"; 5113 function = "qup1_se1"; 5114 drive-strength = <2>; 5115 bias-pull-up = <2200>; 5116 }; 5117 5118 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5119 /* SDA, SCL */ 5120 pins = "gpio40", "gpio41"; 5121 function = "qup1_se2"; 5122 drive-strength = <2>; 5123 bias-pull-up = <2200>; 5124 }; 5125 5126 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5127 /* SDA, SCL */ 5128 pins = "gpio44", "gpio45"; 5129 function = "qup1_se3"; 5130 drive-strength = <2>; 5131 bias-pull-up = <2200>; 5132 }; 5133 5134 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5135 /* SDA, SCL */ 5136 pins = "gpio48", "gpio49"; 5137 function = "qup1_se4"; 5138 drive-strength = <2>; 5139 bias-pull-up = <2200>; 5140 }; 5141 5142 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5143 /* SDA, SCL */ 5144 pins = "gpio52", "gpio53"; 5145 function = "qup1_se5"; 5146 drive-strength = <2>; 5147 bias-pull-up = <2200>; 5148 }; 5149 5150 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5151 /* SDA, SCL */ 5152 pins = "gpio56", "gpio57"; 5153 function = "qup1_se6"; 5154 drive-strength = <2>; 5155 bias-pull-up = <2200>; 5156 }; 5157 5158 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5159 /* SDA, SCL */ 5160 pins = "gpio54", "gpio55"; 5161 function = "qup1_se7"; 5162 drive-strength = <2>; 5163 bias-pull-up = <2200>; 5164 }; 5165 5166 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5167 /* SDA, SCL */ 5168 pins = "gpio64", "gpio65"; 5169 function = "qup2_se0"; 5170 drive-strength = <2>; 5171 bias-pull-up = <2200>; 5172 }; 5173 5174 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5175 /* SDA, SCL */ 5176 pins = "gpio68", "gpio69"; 5177 function = "qup2_se1"; 5178 drive-strength = <2>; 5179 bias-pull-up = <2200>; 5180 }; 5181 5182 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5183 /* SDA, SCL */ 5184 pins = "gpio72", "gpio73"; 5185 function = "qup2_se2"; 5186 drive-strength = <2>; 5187 bias-pull-up = <2200>; 5188 }; 5189 5190 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5191 /* SDA, SCL */ 5192 pins = "gpio76", "gpio77"; 5193 function = "qup2_se3"; 5194 drive-strength = <2>; 5195 bias-pull-up = <2200>; 5196 }; 5197 5198 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5199 /* SDA, SCL */ 5200 pins = "gpio80", "gpio81"; 5201 function = "qup2_se4"; 5202 drive-strength = <2>; 5203 bias-pull-up = <2200>; 5204 }; 5205 5206 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5207 /* SDA, SCL */ 5208 pins = "gpio84", "gpio85"; 5209 function = "qup2_se5"; 5210 drive-strength = <2>; 5211 bias-pull-up = <2200>; 5212 }; 5213 5214 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5215 /* SDA, SCL */ 5216 pins = "gpio88", "gpio89"; 5217 function = "qup2_se6"; 5218 drive-strength = <2>; 5219 bias-pull-up = <2200>; 5220 }; 5221 5222 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5223 /* SDA, SCL */ 5224 pins = "gpio86", "gpio87"; 5225 function = "qup2_se7"; 5226 drive-strength = <2>; 5227 bias-pull-up = <2200>; 5228 }; 5229 5230 qup_spi0_cs: qup-spi0-cs-state { 5231 pins = "gpio3"; 5232 function = "qup0_se0"; 5233 drive-strength = <6>; 5234 bias-disable; 5235 }; 5236 5237 qup_spi0_data_clk: qup-spi0-data-clk-state { 5238 /* MISO, MOSI, CLK */ 5239 pins = "gpio0", "gpio1", "gpio2"; 5240 function = "qup0_se0"; 5241 drive-strength = <6>; 5242 bias-disable; 5243 }; 5244 5245 qup_spi1_cs: qup-spi1-cs-state { 5246 pins = "gpio7"; 5247 function = "qup0_se1"; 5248 drive-strength = <6>; 5249 bias-disable; 5250 }; 5251 5252 qup_spi1_data_clk: qup-spi1-data-clk-state { 5253 /* MISO, MOSI, CLK */ 5254 pins = "gpio4", "gpio5", "gpio6"; 5255 function = "qup0_se1"; 5256 drive-strength = <6>; 5257 bias-disable; 5258 }; 5259 5260 qup_spi2_cs: qup-spi2-cs-state { 5261 pins = "gpio11"; 5262 function = "qup0_se2"; 5263 drive-strength = <6>; 5264 bias-disable; 5265 }; 5266 5267 qup_spi2_data_clk: qup-spi2-data-clk-state { 5268 /* MISO, MOSI, CLK */ 5269 pins = "gpio8", "gpio9", "gpio10"; 5270 function = "qup0_se2"; 5271 drive-strength = <6>; 5272 bias-disable; 5273 }; 5274 5275 qup_spi3_cs: qup-spi3-cs-state { 5276 pins = "gpio15"; 5277 function = "qup0_se3"; 5278 drive-strength = <6>; 5279 bias-disable; 5280 }; 5281 5282 qup_spi3_data_clk: qup-spi3-data-clk-state { 5283 /* MISO, MOSI, CLK */ 5284 pins = "gpio12", "gpio13", "gpio14"; 5285 function = "qup0_se3"; 5286 drive-strength = <6>; 5287 bias-disable; 5288 }; 5289 5290 qup_spi4_cs: qup-spi4-cs-state { 5291 pins = "gpio19"; 5292 function = "qup0_se4"; 5293 drive-strength = <6>; 5294 bias-disable; 5295 }; 5296 5297 qup_spi4_data_clk: qup-spi4-data-clk-state { 5298 /* MISO, MOSI, CLK */ 5299 pins = "gpio16", "gpio17", "gpio18"; 5300 function = "qup0_se4"; 5301 drive-strength = <6>; 5302 bias-disable; 5303 }; 5304 5305 qup_spi5_cs: qup-spi5-cs-state { 5306 pins = "gpio23"; 5307 function = "qup0_se5"; 5308 drive-strength = <6>; 5309 bias-disable; 5310 }; 5311 5312 qup_spi5_data_clk: qup-spi5-data-clk-state { 5313 /* MISO, MOSI, CLK */ 5314 pins = "gpio20", "gpio21", "gpio22"; 5315 function = "qup0_se5"; 5316 drive-strength = <6>; 5317 bias-disable; 5318 }; 5319 5320 qup_spi6_cs: qup-spi6-cs-state { 5321 pins = "gpio27"; 5322 function = "qup0_se6"; 5323 drive-strength = <6>; 5324 bias-disable; 5325 }; 5326 5327 qup_spi6_data_clk: qup-spi6-data-clk-state { 5328 /* MISO, MOSI, CLK */ 5329 pins = "gpio24", "gpio25", "gpio26"; 5330 function = "qup0_se6"; 5331 drive-strength = <6>; 5332 bias-disable; 5333 }; 5334 5335 qup_spi7_cs: qup-spi7-cs-state { 5336 pins = "gpio13"; 5337 function = "qup0_se7"; 5338 drive-strength = <6>; 5339 bias-disable; 5340 }; 5341 5342 qup_spi7_data_clk: qup-spi7-data-clk-state { 5343 /* MISO, MOSI, CLK */ 5344 pins = "gpio14", "gpio15", "gpio12"; 5345 function = "qup0_se7"; 5346 drive-strength = <6>; 5347 bias-disable; 5348 }; 5349 5350 qup_spi8_cs: qup-spi8-cs-state { 5351 pins = "gpio35"; 5352 function = "qup1_se0"; 5353 drive-strength = <6>; 5354 bias-disable; 5355 }; 5356 5357 qup_spi8_data_clk: qup-spi8-data-clk-state { 5358 /* MISO, MOSI, CLK */ 5359 pins = "gpio32", "gpio33", "gpio34"; 5360 function = "qup1_se0"; 5361 drive-strength = <6>; 5362 bias-disable; 5363 }; 5364 5365 qup_spi9_cs: qup-spi9-cs-state { 5366 pins = "gpio39"; 5367 function = "qup1_se1"; 5368 drive-strength = <6>; 5369 bias-disable; 5370 }; 5371 5372 qup_spi9_data_clk: qup-spi9-data-clk-state { 5373 /* MISO, MOSI, CLK */ 5374 pins = "gpio36", "gpio37", "gpio38"; 5375 function = "qup1_se1"; 5376 drive-strength = <6>; 5377 bias-disable; 5378 }; 5379 5380 qup_spi10_cs: qup-spi10-cs-state { 5381 pins = "gpio43"; 5382 function = "qup1_se2"; 5383 drive-strength = <6>; 5384 bias-disable; 5385 }; 5386 5387 qup_spi10_data_clk: qup-spi10-data-clk-state { 5388 /* MISO, MOSI, CLK */ 5389 pins = "gpio40", "gpio41", "gpio42"; 5390 function = "qup1_se2"; 5391 drive-strength = <6>; 5392 bias-disable; 5393 }; 5394 5395 qup_spi11_cs: qup-spi11-cs-state { 5396 pins = "gpio47"; 5397 function = "qup1_se3"; 5398 drive-strength = <6>; 5399 bias-disable; 5400 }; 5401 5402 qup_spi11_data_clk: qup-spi11-data-clk-state { 5403 /* MISO, MOSI, CLK */ 5404 pins = "gpio44", "gpio45", "gpio46"; 5405 function = "qup1_se3"; 5406 drive-strength = <6>; 5407 bias-disable; 5408 }; 5409 5410 qup_spi12_cs: qup-spi12-cs-state { 5411 pins = "gpio51"; 5412 function = "qup1_se4"; 5413 drive-strength = <6>; 5414 bias-disable; 5415 }; 5416 5417 qup_spi12_data_clk: qup-spi12-data-clk-state { 5418 /* MISO, MOSI, CLK */ 5419 pins = "gpio48", "gpio49", "gpio50"; 5420 function = "qup1_se4"; 5421 drive-strength = <6>; 5422 bias-disable; 5423 }; 5424 5425 qup_spi13_cs: qup-spi13-cs-state { 5426 pins = "gpio55"; 5427 function = "qup1_se5"; 5428 drive-strength = <6>; 5429 bias-disable; 5430 }; 5431 5432 qup_spi13_data_clk: qup-spi13-data-clk-state { 5433 /* MISO, MOSI, CLK */ 5434 pins = "gpio52", "gpio53", "gpio54"; 5435 function = "qup1_se5"; 5436 drive-strength = <6>; 5437 bias-disable; 5438 }; 5439 5440 qup_spi14_cs: qup-spi14-cs-state { 5441 pins = "gpio59"; 5442 function = "qup1_se6"; 5443 drive-strength = <6>; 5444 bias-disable; 5445 }; 5446 5447 qup_spi14_data_clk: qup-spi14-data-clk-state { 5448 /* MISO, MOSI, CLK */ 5449 pins = "gpio56", "gpio57", "gpio58"; 5450 function = "qup1_se6"; 5451 drive-strength = <6>; 5452 bias-disable; 5453 }; 5454 5455 qup_spi15_cs: qup-spi15-cs-state { 5456 pins = "gpio53"; 5457 function = "qup1_se7"; 5458 drive-strength = <6>; 5459 bias-disable; 5460 }; 5461 5462 qup_spi15_data_clk: qup-spi15-data-clk-state { 5463 /* MISO, MOSI, CLK */ 5464 pins = "gpio54", "gpio55", "gpio52"; 5465 function = "qup1_se7"; 5466 drive-strength = <6>; 5467 bias-disable; 5468 }; 5469 5470 qup_spi16_cs: qup-spi16-cs-state { 5471 pins = "gpio67"; 5472 function = "qup2_se0"; 5473 drive-strength = <6>; 5474 bias-disable; 5475 }; 5476 5477 qup_spi16_data_clk: qup-spi16-data-clk-state { 5478 /* MISO, MOSI, CLK */ 5479 pins = "gpio64", "gpio65", "gpio66"; 5480 function = "qup2_se0"; 5481 drive-strength = <6>; 5482 bias-disable; 5483 }; 5484 5485 qup_spi17_cs: qup-spi17-cs-state { 5486 pins = "gpio71"; 5487 function = "qup2_se1"; 5488 drive-strength = <6>; 5489 bias-disable; 5490 }; 5491 5492 qup_spi17_data_clk: qup-spi17-data-clk-state { 5493 /* MISO, MOSI, CLK */ 5494 pins = "gpio68", "gpio69", "gpio70"; 5495 function = "qup2_se1"; 5496 drive-strength = <6>; 5497 bias-disable; 5498 }; 5499 5500 qup_spi18_cs: qup-spi18-cs-state { 5501 pins = "gpio75"; 5502 function = "qup2_se2"; 5503 drive-strength = <6>; 5504 bias-disable; 5505 }; 5506 5507 qup_spi18_data_clk: qup-spi18-data-clk-state { 5508 /* MISO, MOSI, CLK */ 5509 pins = "gpio72", "gpio73", "gpio74"; 5510 function = "qup2_se2"; 5511 drive-strength = <6>; 5512 bias-disable; 5513 }; 5514 5515 qup_spi19_cs: qup-spi19-cs-state { 5516 pins = "gpio79"; 5517 function = "qup2_se3"; 5518 drive-strength = <6>; 5519 bias-disable; 5520 }; 5521 5522 qup_spi19_data_clk: qup-spi19-data-clk-state { 5523 /* MISO, MOSI, CLK */ 5524 pins = "gpio76", "gpio77", "gpio78"; 5525 function = "qup2_se3"; 5526 drive-strength = <6>; 5527 bias-disable; 5528 }; 5529 5530 qup_spi20_cs: qup-spi20-cs-state { 5531 pins = "gpio83"; 5532 function = "qup2_se4"; 5533 drive-strength = <6>; 5534 bias-disable; 5535 }; 5536 5537 qup_spi20_data_clk: qup-spi20-data-clk-state { 5538 /* MISO, MOSI, CLK */ 5539 pins = "gpio80", "gpio81", "gpio82"; 5540 function = "qup2_se4"; 5541 drive-strength = <6>; 5542 bias-disable; 5543 }; 5544 5545 qup_spi21_cs: qup-spi21-cs-state { 5546 pins = "gpio87"; 5547 function = "qup2_se5"; 5548 drive-strength = <6>; 5549 bias-disable; 5550 }; 5551 5552 qup_spi21_data_clk: qup-spi21-data-clk-state { 5553 /* MISO, MOSI, CLK */ 5554 pins = "gpio84", "gpio85", "gpio86"; 5555 function = "qup2_se5"; 5556 drive-strength = <6>; 5557 bias-disable; 5558 }; 5559 5560 qup_spi22_cs: qup-spi22-cs-state { 5561 pins = "gpio91"; 5562 function = "qup2_se6"; 5563 drive-strength = <6>; 5564 bias-disable; 5565 }; 5566 5567 qup_spi22_data_clk: qup-spi22-data-clk-state { 5568 /* MISO, MOSI, CLK */ 5569 pins = "gpio88", "gpio89", "gpio90"; 5570 function = "qup2_se6"; 5571 drive-strength = <6>; 5572 bias-disable; 5573 }; 5574 5575 qup_spi23_cs: qup-spi23-cs-state { 5576 pins = "gpio85"; 5577 function = "qup2_se7"; 5578 drive-strength = <6>; 5579 bias-disable; 5580 }; 5581 5582 qup_spi23_data_clk: qup-spi23-data-clk-state { 5583 /* MISO, MOSI, CLK */ 5584 pins = "gpio86", "gpio87", "gpio84"; 5585 function = "qup2_se7"; 5586 drive-strength = <6>; 5587 bias-disable; 5588 }; 5589 5590 qup_uart2_default: qup-uart2-default-state { 5591 cts-pins { 5592 pins = "gpio8"; 5593 function = "qup0_se2"; 5594 drive-strength = <2>; 5595 bias-disable; 5596 }; 5597 5598 rts-pins { 5599 pins = "gpio9"; 5600 function = "qup0_se2"; 5601 drive-strength = <2>; 5602 bias-disable; 5603 }; 5604 5605 tx-pins { 5606 pins = "gpio10"; 5607 function = "qup0_se2"; 5608 drive-strength = <2>; 5609 bias-disable; 5610 }; 5611 5612 rx-pins { 5613 pins = "gpio11"; 5614 function = "qup0_se2"; 5615 drive-strength = <2>; 5616 bias-disable; 5617 }; 5618 }; 5619 5620 qup_uart21_default: qup-uart21-default-state { 5621 tx-pins { 5622 pins = "gpio86"; 5623 function = "qup2_se5"; 5624 drive-strength = <2>; 5625 bias-disable; 5626 }; 5627 5628 rx-pins { 5629 pins = "gpio87"; 5630 function = "qup2_se5"; 5631 drive-strength = <2>; 5632 bias-disable; 5633 }; 5634 }; 5635 }; 5636 5637 apps_smmu: iommu@15000000 { 5638 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5639 reg = <0 0x15000000 0 0x100000>; 5640 5641 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5642 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5643 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5644 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5645 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5646 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5647 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5648 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5649 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5650 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5651 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5652 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5653 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5654 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5655 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5656 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5657 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5658 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5659 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5660 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5661 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5662 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5663 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5664 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5665 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5666 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5667 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5668 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5669 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5670 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5671 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5672 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5673 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5674 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5675 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5676 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5677 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5678 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5679 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5680 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5681 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5682 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5683 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5684 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5685 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5686 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5687 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5688 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5689 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5690 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5691 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5692 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5693 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5694 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5695 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5696 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5697 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5698 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5699 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5700 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5701 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5702 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5703 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5704 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5705 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5706 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5707 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5708 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5709 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5710 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5711 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5712 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5713 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5714 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5715 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5716 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5717 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5718 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5719 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5720 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5721 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5722 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5723 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5724 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5725 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5726 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5727 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5728 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5729 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5730 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5731 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5732 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5733 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5734 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5735 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5736 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5737 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 5738 5739 #iommu-cells = <2>; 5740 #global-interrupts = <1>; 5741 }; 5742 5743 intc: interrupt-controller@17000000 { 5744 compatible = "arm,gic-v3"; 5745 reg = <0 0x17000000 0 0x10000>, /* GICD */ 5746 <0 0x17080000 0 0x480000>; /* GICR * 12 */ 5747 5748 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5749 5750 #interrupt-cells = <3>; 5751 interrupt-controller; 5752 5753 #redistributor-regions = <1>; 5754 redistributor-stride = <0x0 0x40000>; 5755 5756 #address-cells = <2>; 5757 #size-cells = <2>; 5758 ranges; 5759 5760 gic_its: msi-controller@17040000 { 5761 compatible = "arm,gic-v3-its"; 5762 reg = <0 0x17040000 0 0x40000>; 5763 5764 msi-controller; 5765 #msi-cells = <1>; 5766 5767 status = "disabled"; 5768 }; 5769 }; 5770 5771 apps_rsc: rsc@17500000 { 5772 compatible = "qcom,rpmh-rsc"; 5773 reg = <0 0x17500000 0 0x10000>, 5774 <0 0x17510000 0 0x10000>, 5775 <0 0x17520000 0 0x10000>; 5776 reg-names = "drv-0", "drv-1", "drv-2"; 5777 5778 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5779 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5780 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5781 qcom,tcs-offset = <0xd00>; 5782 qcom,drv-id = <2>; 5783 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5784 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5785 5786 label = "apps_rsc"; 5787 power-domains = <&SYSTEM_PD>; 5788 5789 apps_bcm_voter: bcm-voter { 5790 compatible = "qcom,bcm-voter"; 5791 }; 5792 5793 rpmhcc: clock-controller { 5794 compatible = "qcom,x1e80100-rpmh-clk"; 5795 5796 clocks = <&xo_board>; 5797 clock-names = "xo"; 5798 5799 #clock-cells = <1>; 5800 }; 5801 5802 rpmhpd: power-controller { 5803 compatible = "qcom,x1e80100-rpmhpd"; 5804 5805 operating-points-v2 = <&rpmhpd_opp_table>; 5806 5807 #power-domain-cells = <1>; 5808 5809 rpmhpd_opp_table: opp-table { 5810 compatible = "operating-points-v2"; 5811 5812 rpmhpd_opp_ret: opp-16 { 5813 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5814 }; 5815 5816 rpmhpd_opp_min_svs: opp-48 { 5817 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5818 }; 5819 5820 rpmhpd_opp_low_svs_d2: opp-52 { 5821 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5822 }; 5823 5824 rpmhpd_opp_low_svs_d1: opp-56 { 5825 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5826 }; 5827 5828 rpmhpd_opp_low_svs_d0: opp-60 { 5829 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5830 }; 5831 5832 rpmhpd_opp_low_svs: opp-64 { 5833 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5834 }; 5835 5836 rpmhpd_opp_low_svs_l1: opp-80 { 5837 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5838 }; 5839 5840 rpmhpd_opp_svs: opp-128 { 5841 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5842 }; 5843 5844 rpmhpd_opp_svs_l0: opp-144 { 5845 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5846 }; 5847 5848 rpmhpd_opp_svs_l1: opp-192 { 5849 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5850 }; 5851 5852 rpmhpd_opp_nom: opp-256 { 5853 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5854 }; 5855 5856 rpmhpd_opp_nom_l1: opp-320 { 5857 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5858 }; 5859 5860 rpmhpd_opp_nom_l2: opp-336 { 5861 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5862 }; 5863 5864 rpmhpd_opp_turbo: opp-384 { 5865 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5866 }; 5867 5868 rpmhpd_opp_turbo_l1: opp-416 { 5869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5870 }; 5871 }; 5872 }; 5873 }; 5874 5875 timer@17800000 { 5876 compatible = "arm,armv7-timer-mem"; 5877 reg = <0 0x17800000 0 0x1000>; 5878 5879 #address-cells = <2>; 5880 #size-cells = <1>; 5881 ranges = <0 0 0 0 0x20000000>; 5882 5883 frame@17801000 { 5884 reg = <0 0x17801000 0x1000>, 5885 <0 0x17802000 0x1000>; 5886 5887 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5889 5890 frame-number = <0>; 5891 }; 5892 5893 frame@17803000 { 5894 reg = <0 0x17803000 0x1000>; 5895 5896 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5897 5898 frame-number = <1>; 5899 5900 status = "disabled"; 5901 }; 5902 5903 frame@17805000 { 5904 reg = <0 0x17805000 0x1000>; 5905 5906 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5907 5908 frame-number = <2>; 5909 5910 status = "disabled"; 5911 }; 5912 5913 frame@17807000 { 5914 reg = <0 0x17807000 0x1000>; 5915 5916 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5917 5918 frame-number = <3>; 5919 5920 status = "disabled"; 5921 }; 5922 5923 frame@17809000 { 5924 reg = <0 0x17809000 0x1000>; 5925 5926 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5927 5928 frame-number = <4>; 5929 5930 status = "disabled"; 5931 }; 5932 5933 frame@1780b000 { 5934 reg = <0 0x1780b000 0x1000>; 5935 5936 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5937 5938 frame-number = <5>; 5939 5940 status = "disabled"; 5941 }; 5942 5943 frame@1780d000 { 5944 reg = <0 0x1780d000 0x1000>; 5945 5946 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5947 5948 frame-number = <6>; 5949 5950 status = "disabled"; 5951 }; 5952 }; 5953 5954 pmu@24091000 { 5955 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5956 reg = <0 0x24091000 0 0x1000>; 5957 5958 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 5959 5960 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5961 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5962 5963 operating-points-v2 = <&llcc_bwmon_opp_table>; 5964 5965 llcc_bwmon_opp_table: opp-table { 5966 compatible = "operating-points-v2"; 5967 5968 opp-0 { 5969 opp-peak-kBps = <800000>; 5970 }; 5971 5972 opp-1 { 5973 opp-peak-kBps = <2188000>; 5974 }; 5975 5976 opp-2 { 5977 opp-peak-kBps = <3072000>; 5978 }; 5979 5980 opp-3 { 5981 opp-peak-kBps = <6220800>; 5982 }; 5983 5984 opp-4 { 5985 opp-peak-kBps = <6835200>; 5986 }; 5987 5988 opp-5 { 5989 opp-peak-kBps = <8371200>; 5990 }; 5991 5992 opp-6 { 5993 opp-peak-kBps = <10944000>; 5994 }; 5995 5996 opp-7 { 5997 opp-peak-kBps = <12748800>; 5998 }; 5999 6000 opp-8 { 6001 opp-peak-kBps = <14745600>; 6002 }; 6003 6004 opp-9 { 6005 opp-peak-kBps = <16896000>; 6006 }; 6007 }; 6008 }; 6009 6010 /* cluster0 */ 6011 pmu@240b3400 { 6012 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 6013 reg = <0 0x240b3400 0 0x600>; 6014 6015 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 6016 6017 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6018 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 6019 6020 operating-points-v2 = <&cpu_bwmon_opp_table>; 6021 6022 cpu_bwmon_opp_table: opp-table { 6023 compatible = "operating-points-v2"; 6024 6025 opp-0 { 6026 opp-peak-kBps = <4800000>; 6027 }; 6028 6029 opp-1 { 6030 opp-peak-kBps = <7464000>; 6031 }; 6032 6033 opp-2 { 6034 opp-peak-kBps = <9600000>; 6035 }; 6036 6037 opp-3 { 6038 opp-peak-kBps = <12896000>; 6039 }; 6040 6041 opp-4 { 6042 opp-peak-kBps = <14928000>; 6043 }; 6044 6045 opp-5 { 6046 opp-peak-kBps = <17064000>; 6047 }; 6048 }; 6049 }; 6050 6051 /* cluster2 */ 6052 pmu@240b5400 { 6053 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 6054 reg = <0 0x240b5400 0 0x600>; 6055 6056 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 6057 6058 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6059 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 6060 6061 operating-points-v2 = <&cpu_bwmon_opp_table>; 6062 }; 6063 6064 /* cluster1 */ 6065 pmu@240b6400 { 6066 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 6067 reg = <0 0x240b6400 0 0x600>; 6068 6069 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 6070 6071 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6072 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 6073 6074 operating-points-v2 = <&cpu_bwmon_opp_table>; 6075 }; 6076 6077 system-cache-controller@25000000 { 6078 compatible = "qcom,x1e80100-llcc"; 6079 reg = <0 0x25000000 0 0x200000>, 6080 <0 0x25200000 0 0x200000>, 6081 <0 0x25400000 0 0x200000>, 6082 <0 0x25600000 0 0x200000>, 6083 <0 0x25800000 0 0x200000>, 6084 <0 0x25a00000 0 0x200000>, 6085 <0 0x25c00000 0 0x200000>, 6086 <0 0x25e00000 0 0x200000>, 6087 <0 0x26000000 0 0x200000>; 6088 reg-names = "llcc0_base", 6089 "llcc1_base", 6090 "llcc2_base", 6091 "llcc3_base", 6092 "llcc4_base", 6093 "llcc5_base", 6094 "llcc6_base", 6095 "llcc7_base", 6096 "llcc_broadcast_base"; 6097 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 6098 }; 6099 6100 remoteproc_adsp: remoteproc@30000000 { 6101 compatible = "qcom,x1e80100-adsp-pas"; 6102 reg = <0 0x30000000 0 0x100>; 6103 6104 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 6105 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 6106 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 6107 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 6108 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 6109 interrupt-names = "wdog", 6110 "fatal", 6111 "ready", 6112 "handover", 6113 "stop-ack"; 6114 6115 clocks = <&rpmhcc RPMH_CXO_CLK>; 6116 clock-names = "xo"; 6117 6118 power-domains = <&rpmhpd RPMHPD_LCX>, 6119 <&rpmhpd RPMHPD_LMX>; 6120 power-domain-names = "lcx", 6121 "lmx"; 6122 6123 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 6124 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 6125 6126 memory-region = <&adspslpi_mem>, 6127 <&q6_adsp_dtb_mem>; 6128 6129 qcom,qmp = <&aoss_qmp>; 6130 6131 qcom,smem-states = <&smp2p_adsp_out 0>; 6132 qcom,smem-state-names = "stop"; 6133 6134 status = "disabled"; 6135 6136 glink-edge { 6137 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 6138 IPCC_MPROC_SIGNAL_GLINK_QMP 6139 IRQ_TYPE_EDGE_RISING>; 6140 mboxes = <&ipcc IPCC_CLIENT_LPASS 6141 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6142 6143 label = "lpass"; 6144 qcom,remote-pid = <2>; 6145 6146 fastrpc { 6147 compatible = "qcom,fastrpc"; 6148 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6149 label = "adsp"; 6150 qcom,non-secure-domain; 6151 #address-cells = <1>; 6152 #size-cells = <0>; 6153 6154 compute-cb@3 { 6155 compatible = "qcom,fastrpc-compute-cb"; 6156 reg = <3>; 6157 iommus = <&apps_smmu 0x1003 0x80>, 6158 <&apps_smmu 0x1063 0x0>; 6159 dma-coherent; 6160 }; 6161 6162 compute-cb@4 { 6163 compatible = "qcom,fastrpc-compute-cb"; 6164 reg = <4>; 6165 iommus = <&apps_smmu 0x1004 0x80>, 6166 <&apps_smmu 0x1064 0x0>; 6167 dma-coherent; 6168 }; 6169 6170 compute-cb@5 { 6171 compatible = "qcom,fastrpc-compute-cb"; 6172 reg = <5>; 6173 iommus = <&apps_smmu 0x1005 0x80>, 6174 <&apps_smmu 0x1065 0x0>; 6175 dma-coherent; 6176 }; 6177 6178 compute-cb@6 { 6179 compatible = "qcom,fastrpc-compute-cb"; 6180 reg = <6>; 6181 iommus = <&apps_smmu 0x1006 0x80>, 6182 <&apps_smmu 0x1066 0x0>; 6183 dma-coherent; 6184 }; 6185 6186 compute-cb@7 { 6187 compatible = "qcom,fastrpc-compute-cb"; 6188 reg = <7>; 6189 iommus = <&apps_smmu 0x1007 0x80>, 6190 <&apps_smmu 0x1067 0x0>; 6191 dma-coherent; 6192 }; 6193 }; 6194 6195 gpr { 6196 compatible = "qcom,gpr"; 6197 qcom,glink-channels = "adsp_apps"; 6198 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 6199 qcom,intents = <512 20>; 6200 #address-cells = <1>; 6201 #size-cells = <0>; 6202 6203 q6apm: service@1 { 6204 compatible = "qcom,q6apm"; 6205 reg = <GPR_APM_MODULE_IID>; 6206 #sound-dai-cells = <0>; 6207 qcom,protection-domain = "avs/audio", 6208 "msm/adsp/audio_pd"; 6209 6210 q6apmbedai: bedais { 6211 compatible = "qcom,q6apm-lpass-dais"; 6212 #sound-dai-cells = <1>; 6213 }; 6214 6215 q6apmdai: dais { 6216 compatible = "qcom,q6apm-dais"; 6217 iommus = <&apps_smmu 0x1001 0x80>, 6218 <&apps_smmu 0x1061 0x0>; 6219 }; 6220 }; 6221 6222 q6prm: service@2 { 6223 compatible = "qcom,q6prm"; 6224 reg = <GPR_PRM_MODULE_IID>; 6225 qcom,protection-domain = "avs/audio", 6226 "msm/adsp/audio_pd"; 6227 6228 q6prmcc: clock-controller { 6229 compatible = "qcom,q6prm-lpass-clocks"; 6230 #clock-cells = <2>; 6231 }; 6232 }; 6233 }; 6234 }; 6235 }; 6236 6237 remoteproc_cdsp: remoteproc@32300000 { 6238 compatible = "qcom,x1e80100-cdsp-pas"; 6239 reg = <0 0x32300000 0 0x1400000>; 6240 6241 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6242 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 6243 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 6244 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 6245 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 6246 interrupt-names = "wdog", 6247 "fatal", 6248 "ready", 6249 "handover", 6250 "stop-ack"; 6251 6252 clocks = <&rpmhcc RPMH_CXO_CLK>; 6253 clock-names = "xo"; 6254 6255 power-domains = <&rpmhpd RPMHPD_CX>, 6256 <&rpmhpd RPMHPD_MXC>, 6257 <&rpmhpd RPMHPD_NSP>; 6258 power-domain-names = "cx", 6259 "mxc", 6260 "nsp"; 6261 6262 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 6263 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 6264 6265 memory-region = <&cdsp_mem>, 6266 <&q6_cdsp_dtb_mem>; 6267 6268 qcom,qmp = <&aoss_qmp>; 6269 6270 qcom,smem-states = <&smp2p_cdsp_out 0>; 6271 qcom,smem-state-names = "stop"; 6272 6273 status = "disabled"; 6274 6275 glink-edge { 6276 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6277 IPCC_MPROC_SIGNAL_GLINK_QMP 6278 IRQ_TYPE_EDGE_RISING>; 6279 mboxes = <&ipcc IPCC_CLIENT_CDSP 6280 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6281 6282 label = "cdsp"; 6283 qcom,remote-pid = <5>; 6284 6285 fastrpc { 6286 compatible = "qcom,fastrpc"; 6287 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6288 label = "cdsp"; 6289 qcom,non-secure-domain; 6290 #address-cells = <1>; 6291 #size-cells = <0>; 6292 6293 compute-cb@1 { 6294 compatible = "qcom,fastrpc-compute-cb"; 6295 reg = <1>; 6296 iommus = <&apps_smmu 0x0c01 0x20>; 6297 dma-coherent; 6298 }; 6299 6300 compute-cb@2 { 6301 compatible = "qcom,fastrpc-compute-cb"; 6302 reg = <2>; 6303 iommus = <&apps_smmu 0x0c02 0x20>; 6304 dma-coherent; 6305 }; 6306 6307 compute-cb@3 { 6308 compatible = "qcom,fastrpc-compute-cb"; 6309 reg = <3>; 6310 iommus = <&apps_smmu 0x0c03 0x20>; 6311 dma-coherent; 6312 }; 6313 6314 compute-cb@4 { 6315 compatible = "qcom,fastrpc-compute-cb"; 6316 reg = <4>; 6317 iommus = <&apps_smmu 0x0c04 0x20>; 6318 dma-coherent; 6319 }; 6320 6321 compute-cb@5 { 6322 compatible = "qcom,fastrpc-compute-cb"; 6323 reg = <5>; 6324 iommus = <&apps_smmu 0x0c05 0x20>; 6325 dma-coherent; 6326 }; 6327 6328 compute-cb@6 { 6329 compatible = "qcom,fastrpc-compute-cb"; 6330 reg = <6>; 6331 iommus = <&apps_smmu 0x0c06 0x20>; 6332 dma-coherent; 6333 }; 6334 6335 compute-cb@7 { 6336 compatible = "qcom,fastrpc-compute-cb"; 6337 reg = <7>; 6338 iommus = <&apps_smmu 0x0c07 0x20>; 6339 dma-coherent; 6340 }; 6341 6342 compute-cb@8 { 6343 compatible = "qcom,fastrpc-compute-cb"; 6344 reg = <8>; 6345 iommus = <&apps_smmu 0x0c08 0x20>; 6346 dma-coherent; 6347 }; 6348 6349 /* note: compute-cb@9 is secure */ 6350 6351 compute-cb@10 { 6352 compatible = "qcom,fastrpc-compute-cb"; 6353 reg = <10>; 6354 iommus = <&apps_smmu 0x0c0c 0x20>; 6355 dma-coherent; 6356 }; 6357 6358 compute-cb@11 { 6359 compatible = "qcom,fastrpc-compute-cb"; 6360 reg = <11>; 6361 iommus = <&apps_smmu 0x0c0d 0x20>; 6362 dma-coherent; 6363 }; 6364 6365 compute-cb@12 { 6366 compatible = "qcom,fastrpc-compute-cb"; 6367 reg = <12>; 6368 iommus = <&apps_smmu 0x0c0e 0x20>; 6369 dma-coherent; 6370 }; 6371 6372 compute-cb@13 { 6373 compatible = "qcom,fastrpc-compute-cb"; 6374 reg = <13>; 6375 iommus = <&apps_smmu 0x0c0f 0x20>; 6376 dma-coherent; 6377 }; 6378 }; 6379 }; 6380 }; 6381 }; 6382 6383 timer { 6384 compatible = "arm,armv8-timer"; 6385 6386 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6387 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6388 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6389 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6390 }; 6391 6392 thermal-zones { 6393 aoss0-thermal { 6394 thermal-sensors = <&tsens0 0>; 6395 6396 trips { 6397 trip-point0 { 6398 temperature = <90000>; 6399 hysteresis = <2000>; 6400 type = "hot"; 6401 }; 6402 6403 aoss0-critical { 6404 temperature = <125000>; 6405 hysteresis = <0>; 6406 type = "critical"; 6407 }; 6408 }; 6409 }; 6410 6411 cpu0-0-top-thermal { 6412 polling-delay-passive = <250>; 6413 6414 thermal-sensors = <&tsens0 1>; 6415 6416 trips { 6417 trip-point0 { 6418 temperature = <90000>; 6419 hysteresis = <2000>; 6420 type = "passive"; 6421 }; 6422 6423 trip-point1 { 6424 temperature = <95000>; 6425 hysteresis = <2000>; 6426 type = "passive"; 6427 }; 6428 6429 cpu-critical { 6430 temperature = <110000>; 6431 hysteresis = <1000>; 6432 type = "critical"; 6433 }; 6434 }; 6435 }; 6436 6437 cpu0-0-btm-thermal { 6438 polling-delay-passive = <250>; 6439 6440 thermal-sensors = <&tsens0 2>; 6441 6442 trips { 6443 trip-point0 { 6444 temperature = <90000>; 6445 hysteresis = <2000>; 6446 type = "passive"; 6447 }; 6448 6449 trip-point1 { 6450 temperature = <95000>; 6451 hysteresis = <2000>; 6452 type = "passive"; 6453 }; 6454 6455 cpu-critical { 6456 temperature = <110000>; 6457 hysteresis = <1000>; 6458 type = "critical"; 6459 }; 6460 }; 6461 }; 6462 6463 cpu0-1-top-thermal { 6464 polling-delay-passive = <250>; 6465 6466 thermal-sensors = <&tsens0 3>; 6467 6468 trips { 6469 trip-point0 { 6470 temperature = <90000>; 6471 hysteresis = <2000>; 6472 type = "passive"; 6473 }; 6474 6475 trip-point1 { 6476 temperature = <95000>; 6477 hysteresis = <2000>; 6478 type = "passive"; 6479 }; 6480 6481 cpu-critical { 6482 temperature = <110000>; 6483 hysteresis = <1000>; 6484 type = "critical"; 6485 }; 6486 }; 6487 }; 6488 6489 cpu0-1-btm-thermal { 6490 polling-delay-passive = <250>; 6491 6492 thermal-sensors = <&tsens0 4>; 6493 6494 trips { 6495 trip-point0 { 6496 temperature = <90000>; 6497 hysteresis = <2000>; 6498 type = "passive"; 6499 }; 6500 6501 trip-point1 { 6502 temperature = <95000>; 6503 hysteresis = <2000>; 6504 type = "passive"; 6505 }; 6506 6507 cpu-critical { 6508 temperature = <110000>; 6509 hysteresis = <1000>; 6510 type = "critical"; 6511 }; 6512 }; 6513 }; 6514 6515 cpu0-2-top-thermal { 6516 polling-delay-passive = <250>; 6517 6518 thermal-sensors = <&tsens0 5>; 6519 6520 trips { 6521 trip-point0 { 6522 temperature = <90000>; 6523 hysteresis = <2000>; 6524 type = "passive"; 6525 }; 6526 6527 trip-point1 { 6528 temperature = <95000>; 6529 hysteresis = <2000>; 6530 type = "passive"; 6531 }; 6532 6533 cpu-critical { 6534 temperature = <110000>; 6535 hysteresis = <1000>; 6536 type = "critical"; 6537 }; 6538 }; 6539 }; 6540 6541 cpu0-2-btm-thermal { 6542 polling-delay-passive = <250>; 6543 6544 thermal-sensors = <&tsens0 6>; 6545 6546 trips { 6547 trip-point0 { 6548 temperature = <90000>; 6549 hysteresis = <2000>; 6550 type = "passive"; 6551 }; 6552 6553 trip-point1 { 6554 temperature = <95000>; 6555 hysteresis = <2000>; 6556 type = "passive"; 6557 }; 6558 6559 cpu-critical { 6560 temperature = <110000>; 6561 hysteresis = <1000>; 6562 type = "critical"; 6563 }; 6564 }; 6565 }; 6566 6567 cpu0-3-top-thermal { 6568 polling-delay-passive = <250>; 6569 6570 thermal-sensors = <&tsens0 7>; 6571 6572 trips { 6573 trip-point0 { 6574 temperature = <90000>; 6575 hysteresis = <2000>; 6576 type = "passive"; 6577 }; 6578 6579 trip-point1 { 6580 temperature = <95000>; 6581 hysteresis = <2000>; 6582 type = "passive"; 6583 }; 6584 6585 cpu-critical { 6586 temperature = <110000>; 6587 hysteresis = <1000>; 6588 type = "critical"; 6589 }; 6590 }; 6591 }; 6592 6593 cpu0-3-btm-thermal { 6594 polling-delay-passive = <250>; 6595 6596 thermal-sensors = <&tsens0 8>; 6597 6598 trips { 6599 trip-point0 { 6600 temperature = <90000>; 6601 hysteresis = <2000>; 6602 type = "passive"; 6603 }; 6604 6605 trip-point1 { 6606 temperature = <95000>; 6607 hysteresis = <2000>; 6608 type = "passive"; 6609 }; 6610 6611 cpu-critical { 6612 temperature = <110000>; 6613 hysteresis = <1000>; 6614 type = "critical"; 6615 }; 6616 }; 6617 }; 6618 6619 cpuss0-top-thermal { 6620 thermal-sensors = <&tsens0 9>; 6621 6622 trips { 6623 trip-point0 { 6624 temperature = <90000>; 6625 hysteresis = <2000>; 6626 type = "hot"; 6627 }; 6628 6629 cpuss2-critical { 6630 temperature = <125000>; 6631 hysteresis = <0>; 6632 type = "critical"; 6633 }; 6634 }; 6635 }; 6636 6637 cpuss0-btm-thermal { 6638 thermal-sensors = <&tsens0 10>; 6639 6640 trips { 6641 trip-point0 { 6642 temperature = <90000>; 6643 hysteresis = <2000>; 6644 type = "hot"; 6645 }; 6646 6647 cpuss2-critical { 6648 temperature = <125000>; 6649 hysteresis = <0>; 6650 type = "critical"; 6651 }; 6652 }; 6653 }; 6654 6655 mem-thermal { 6656 thermal-sensors = <&tsens0 11>; 6657 6658 trips { 6659 trip-point0 { 6660 temperature = <90000>; 6661 hysteresis = <2000>; 6662 type = "hot"; 6663 }; 6664 6665 mem-critical { 6666 temperature = <125000>; 6667 hysteresis = <0>; 6668 type = "critical"; 6669 }; 6670 }; 6671 }; 6672 6673 video-thermal { 6674 polling-delay-passive = <250>; 6675 6676 thermal-sensors = <&tsens0 12>; 6677 6678 trips { 6679 trip-point0 { 6680 temperature = <125000>; 6681 hysteresis = <1000>; 6682 type = "passive"; 6683 }; 6684 }; 6685 }; 6686 6687 aoss1-thermal { 6688 thermal-sensors = <&tsens1 0>; 6689 6690 trips { 6691 trip-point0 { 6692 temperature = <90000>; 6693 hysteresis = <2000>; 6694 type = "hot"; 6695 }; 6696 6697 aoss0-critical { 6698 temperature = <125000>; 6699 hysteresis = <0>; 6700 type = "critical"; 6701 }; 6702 }; 6703 }; 6704 6705 cpu1-0-top-thermal { 6706 polling-delay-passive = <250>; 6707 6708 thermal-sensors = <&tsens1 1>; 6709 6710 trips { 6711 trip-point0 { 6712 temperature = <90000>; 6713 hysteresis = <2000>; 6714 type = "passive"; 6715 }; 6716 6717 trip-point1 { 6718 temperature = <95000>; 6719 hysteresis = <2000>; 6720 type = "passive"; 6721 }; 6722 6723 cpu-critical { 6724 temperature = <110000>; 6725 hysteresis = <1000>; 6726 type = "critical"; 6727 }; 6728 }; 6729 }; 6730 6731 cpu1-0-btm-thermal { 6732 polling-delay-passive = <250>; 6733 6734 thermal-sensors = <&tsens1 2>; 6735 6736 trips { 6737 trip-point0 { 6738 temperature = <90000>; 6739 hysteresis = <2000>; 6740 type = "passive"; 6741 }; 6742 6743 trip-point1 { 6744 temperature = <95000>; 6745 hysteresis = <2000>; 6746 type = "passive"; 6747 }; 6748 6749 cpu-critical { 6750 temperature = <110000>; 6751 hysteresis = <1000>; 6752 type = "critical"; 6753 }; 6754 }; 6755 }; 6756 6757 cpu1-1-top-thermal { 6758 polling-delay-passive = <250>; 6759 6760 thermal-sensors = <&tsens1 3>; 6761 6762 trips { 6763 trip-point0 { 6764 temperature = <90000>; 6765 hysteresis = <2000>; 6766 type = "passive"; 6767 }; 6768 6769 trip-point1 { 6770 temperature = <95000>; 6771 hysteresis = <2000>; 6772 type = "passive"; 6773 }; 6774 6775 cpu-critical { 6776 temperature = <110000>; 6777 hysteresis = <1000>; 6778 type = "critical"; 6779 }; 6780 }; 6781 }; 6782 6783 cpu1-1-btm-thermal { 6784 polling-delay-passive = <250>; 6785 6786 thermal-sensors = <&tsens1 4>; 6787 6788 trips { 6789 trip-point0 { 6790 temperature = <90000>; 6791 hysteresis = <2000>; 6792 type = "passive"; 6793 }; 6794 6795 trip-point1 { 6796 temperature = <95000>; 6797 hysteresis = <2000>; 6798 type = "passive"; 6799 }; 6800 6801 cpu-critical { 6802 temperature = <110000>; 6803 hysteresis = <1000>; 6804 type = "critical"; 6805 }; 6806 }; 6807 }; 6808 6809 cpu1-2-top-thermal { 6810 polling-delay-passive = <250>; 6811 6812 thermal-sensors = <&tsens1 5>; 6813 6814 trips { 6815 trip-point0 { 6816 temperature = <90000>; 6817 hysteresis = <2000>; 6818 type = "passive"; 6819 }; 6820 6821 trip-point1 { 6822 temperature = <95000>; 6823 hysteresis = <2000>; 6824 type = "passive"; 6825 }; 6826 6827 cpu-critical { 6828 temperature = <110000>; 6829 hysteresis = <1000>; 6830 type = "critical"; 6831 }; 6832 }; 6833 }; 6834 6835 cpu1-2-btm-thermal { 6836 polling-delay-passive = <250>; 6837 6838 thermal-sensors = <&tsens1 6>; 6839 6840 trips { 6841 trip-point0 { 6842 temperature = <90000>; 6843 hysteresis = <2000>; 6844 type = "passive"; 6845 }; 6846 6847 trip-point1 { 6848 temperature = <95000>; 6849 hysteresis = <2000>; 6850 type = "passive"; 6851 }; 6852 6853 cpu-critical { 6854 temperature = <110000>; 6855 hysteresis = <1000>; 6856 type = "critical"; 6857 }; 6858 }; 6859 }; 6860 6861 cpu1-3-top-thermal { 6862 polling-delay-passive = <250>; 6863 6864 thermal-sensors = <&tsens1 7>; 6865 6866 trips { 6867 trip-point0 { 6868 temperature = <90000>; 6869 hysteresis = <2000>; 6870 type = "passive"; 6871 }; 6872 6873 trip-point1 { 6874 temperature = <95000>; 6875 hysteresis = <2000>; 6876 type = "passive"; 6877 }; 6878 6879 cpu-critical { 6880 temperature = <110000>; 6881 hysteresis = <1000>; 6882 type = "critical"; 6883 }; 6884 }; 6885 }; 6886 6887 cpu1-3-btm-thermal { 6888 polling-delay-passive = <250>; 6889 6890 thermal-sensors = <&tsens1 8>; 6891 6892 trips { 6893 trip-point0 { 6894 temperature = <90000>; 6895 hysteresis = <2000>; 6896 type = "passive"; 6897 }; 6898 6899 trip-point1 { 6900 temperature = <95000>; 6901 hysteresis = <2000>; 6902 type = "passive"; 6903 }; 6904 6905 cpu-critical { 6906 temperature = <110000>; 6907 hysteresis = <1000>; 6908 type = "critical"; 6909 }; 6910 }; 6911 }; 6912 6913 cpuss1-top-thermal { 6914 thermal-sensors = <&tsens1 9>; 6915 6916 trips { 6917 trip-point0 { 6918 temperature = <90000>; 6919 hysteresis = <2000>; 6920 type = "hot"; 6921 }; 6922 6923 cpuss2-critical { 6924 temperature = <125000>; 6925 hysteresis = <0>; 6926 type = "critical"; 6927 }; 6928 }; 6929 }; 6930 6931 cpuss1-btm-thermal { 6932 thermal-sensors = <&tsens1 10>; 6933 6934 trips { 6935 trip-point0 { 6936 temperature = <90000>; 6937 hysteresis = <2000>; 6938 type = "hot"; 6939 }; 6940 6941 cpuss2-critical { 6942 temperature = <125000>; 6943 hysteresis = <0>; 6944 type = "critical"; 6945 }; 6946 }; 6947 }; 6948 6949 aoss2-thermal { 6950 thermal-sensors = <&tsens2 0>; 6951 6952 trips { 6953 trip-point0 { 6954 temperature = <90000>; 6955 hysteresis = <2000>; 6956 type = "hot"; 6957 }; 6958 6959 aoss0-critical { 6960 temperature = <125000>; 6961 hysteresis = <0>; 6962 type = "critical"; 6963 }; 6964 }; 6965 }; 6966 6967 cpu2-0-top-thermal { 6968 polling-delay-passive = <250>; 6969 6970 thermal-sensors = <&tsens2 1>; 6971 6972 trips { 6973 trip-point0 { 6974 temperature = <90000>; 6975 hysteresis = <2000>; 6976 type = "passive"; 6977 }; 6978 6979 trip-point1 { 6980 temperature = <95000>; 6981 hysteresis = <2000>; 6982 type = "passive"; 6983 }; 6984 6985 cpu-critical { 6986 temperature = <110000>; 6987 hysteresis = <1000>; 6988 type = "critical"; 6989 }; 6990 }; 6991 }; 6992 6993 cpu2-0-btm-thermal { 6994 polling-delay-passive = <250>; 6995 6996 thermal-sensors = <&tsens2 2>; 6997 6998 trips { 6999 trip-point0 { 7000 temperature = <90000>; 7001 hysteresis = <2000>; 7002 type = "passive"; 7003 }; 7004 7005 trip-point1 { 7006 temperature = <95000>; 7007 hysteresis = <2000>; 7008 type = "passive"; 7009 }; 7010 7011 cpu-critical { 7012 temperature = <110000>; 7013 hysteresis = <1000>; 7014 type = "critical"; 7015 }; 7016 }; 7017 }; 7018 7019 cpu2-1-top-thermal { 7020 polling-delay-passive = <250>; 7021 7022 thermal-sensors = <&tsens2 3>; 7023 7024 trips { 7025 trip-point0 { 7026 temperature = <90000>; 7027 hysteresis = <2000>; 7028 type = "passive"; 7029 }; 7030 7031 trip-point1 { 7032 temperature = <95000>; 7033 hysteresis = <2000>; 7034 type = "passive"; 7035 }; 7036 7037 cpu-critical { 7038 temperature = <110000>; 7039 hysteresis = <1000>; 7040 type = "critical"; 7041 }; 7042 }; 7043 }; 7044 7045 cpu2-1-btm-thermal { 7046 polling-delay-passive = <250>; 7047 7048 thermal-sensors = <&tsens2 4>; 7049 7050 trips { 7051 trip-point0 { 7052 temperature = <90000>; 7053 hysteresis = <2000>; 7054 type = "passive"; 7055 }; 7056 7057 trip-point1 { 7058 temperature = <95000>; 7059 hysteresis = <2000>; 7060 type = "passive"; 7061 }; 7062 7063 cpu-critical { 7064 temperature = <110000>; 7065 hysteresis = <1000>; 7066 type = "critical"; 7067 }; 7068 }; 7069 }; 7070 7071 cpu2-2-top-thermal { 7072 polling-delay-passive = <250>; 7073 7074 thermal-sensors = <&tsens2 5>; 7075 7076 trips { 7077 trip-point0 { 7078 temperature = <90000>; 7079 hysteresis = <2000>; 7080 type = "passive"; 7081 }; 7082 7083 trip-point1 { 7084 temperature = <95000>; 7085 hysteresis = <2000>; 7086 type = "passive"; 7087 }; 7088 7089 cpu-critical { 7090 temperature = <110000>; 7091 hysteresis = <1000>; 7092 type = "critical"; 7093 }; 7094 }; 7095 }; 7096 7097 cpu2-2-btm-thermal { 7098 polling-delay-passive = <250>; 7099 7100 thermal-sensors = <&tsens2 6>; 7101 7102 trips { 7103 trip-point0 { 7104 temperature = <90000>; 7105 hysteresis = <2000>; 7106 type = "passive"; 7107 }; 7108 7109 trip-point1 { 7110 temperature = <95000>; 7111 hysteresis = <2000>; 7112 type = "passive"; 7113 }; 7114 7115 cpu-critical { 7116 temperature = <110000>; 7117 hysteresis = <1000>; 7118 type = "critical"; 7119 }; 7120 }; 7121 }; 7122 7123 cpu2-3-top-thermal { 7124 polling-delay-passive = <250>; 7125 7126 thermal-sensors = <&tsens2 7>; 7127 7128 trips { 7129 trip-point0 { 7130 temperature = <90000>; 7131 hysteresis = <2000>; 7132 type = "passive"; 7133 }; 7134 7135 trip-point1 { 7136 temperature = <95000>; 7137 hysteresis = <2000>; 7138 type = "passive"; 7139 }; 7140 7141 cpu-critical { 7142 temperature = <110000>; 7143 hysteresis = <1000>; 7144 type = "critical"; 7145 }; 7146 }; 7147 }; 7148 7149 cpu2-3-btm-thermal { 7150 polling-delay-passive = <250>; 7151 7152 thermal-sensors = <&tsens2 8>; 7153 7154 trips { 7155 trip-point0 { 7156 temperature = <90000>; 7157 hysteresis = <2000>; 7158 type = "passive"; 7159 }; 7160 7161 trip-point1 { 7162 temperature = <95000>; 7163 hysteresis = <2000>; 7164 type = "passive"; 7165 }; 7166 7167 cpu-critical { 7168 temperature = <110000>; 7169 hysteresis = <1000>; 7170 type = "critical"; 7171 }; 7172 }; 7173 }; 7174 7175 cpuss2-top-thermal { 7176 thermal-sensors = <&tsens2 9>; 7177 7178 trips { 7179 trip-point0 { 7180 temperature = <90000>; 7181 hysteresis = <2000>; 7182 type = "hot"; 7183 }; 7184 7185 cpuss2-critical { 7186 temperature = <125000>; 7187 hysteresis = <0>; 7188 type = "critical"; 7189 }; 7190 }; 7191 }; 7192 7193 cpuss2-btm-thermal { 7194 thermal-sensors = <&tsens2 10>; 7195 7196 trips { 7197 trip-point0 { 7198 temperature = <90000>; 7199 hysteresis = <2000>; 7200 type = "hot"; 7201 }; 7202 7203 cpuss2-critical { 7204 temperature = <125000>; 7205 hysteresis = <0>; 7206 type = "critical"; 7207 }; 7208 }; 7209 }; 7210 7211 aoss3-thermal { 7212 thermal-sensors = <&tsens3 0>; 7213 7214 trips { 7215 trip-point0 { 7216 temperature = <90000>; 7217 hysteresis = <2000>; 7218 type = "hot"; 7219 }; 7220 7221 aoss0-critical { 7222 temperature = <125000>; 7223 hysteresis = <0>; 7224 type = "critical"; 7225 }; 7226 }; 7227 }; 7228 7229 nsp0-thermal { 7230 thermal-sensors = <&tsens3 1>; 7231 7232 trips { 7233 trip-point0 { 7234 temperature = <90000>; 7235 hysteresis = <2000>; 7236 type = "hot"; 7237 }; 7238 7239 nsp0-critical { 7240 temperature = <125000>; 7241 hysteresis = <0>; 7242 type = "critical"; 7243 }; 7244 }; 7245 }; 7246 7247 nsp1-thermal { 7248 thermal-sensors = <&tsens3 2>; 7249 7250 trips { 7251 trip-point0 { 7252 temperature = <90000>; 7253 hysteresis = <2000>; 7254 type = "hot"; 7255 }; 7256 7257 nsp1-critical { 7258 temperature = <125000>; 7259 hysteresis = <0>; 7260 type = "critical"; 7261 }; 7262 }; 7263 }; 7264 7265 nsp2-thermal { 7266 thermal-sensors = <&tsens3 3>; 7267 7268 trips { 7269 trip-point0 { 7270 temperature = <90000>; 7271 hysteresis = <2000>; 7272 type = "hot"; 7273 }; 7274 7275 nsp2-critical { 7276 temperature = <125000>; 7277 hysteresis = <0>; 7278 type = "critical"; 7279 }; 7280 }; 7281 }; 7282 7283 nsp3-thermal { 7284 thermal-sensors = <&tsens3 4>; 7285 7286 trips { 7287 trip-point0 { 7288 temperature = <90000>; 7289 hysteresis = <2000>; 7290 type = "hot"; 7291 }; 7292 7293 nsp3-critical { 7294 temperature = <125000>; 7295 hysteresis = <0>; 7296 type = "critical"; 7297 }; 7298 }; 7299 }; 7300 7301 gpuss-0-thermal { 7302 polling-delay-passive = <10>; 7303 7304 thermal-sensors = <&tsens3 5>; 7305 7306 trips { 7307 trip-point0 { 7308 temperature = <85000>; 7309 hysteresis = <1000>; 7310 type = "passive"; 7311 }; 7312 7313 trip-point1 { 7314 temperature = <90000>; 7315 hysteresis = <1000>; 7316 type = "hot"; 7317 }; 7318 7319 trip-point2 { 7320 temperature = <125000>; 7321 hysteresis = <1000>; 7322 type = "critical"; 7323 }; 7324 }; 7325 }; 7326 7327 gpuss-1-thermal { 7328 polling-delay-passive = <10>; 7329 7330 thermal-sensors = <&tsens3 6>; 7331 7332 trips { 7333 trip-point0 { 7334 temperature = <85000>; 7335 hysteresis = <1000>; 7336 type = "passive"; 7337 }; 7338 7339 trip-point1 { 7340 temperature = <90000>; 7341 hysteresis = <1000>; 7342 type = "hot"; 7343 }; 7344 7345 trip-point2 { 7346 temperature = <125000>; 7347 hysteresis = <1000>; 7348 type = "critical"; 7349 }; 7350 }; 7351 }; 7352 7353 gpuss-2-thermal { 7354 polling-delay-passive = <10>; 7355 7356 thermal-sensors = <&tsens3 7>; 7357 7358 trips { 7359 trip-point0 { 7360 temperature = <85000>; 7361 hysteresis = <1000>; 7362 type = "passive"; 7363 }; 7364 7365 trip-point1 { 7366 temperature = <90000>; 7367 hysteresis = <1000>; 7368 type = "hot"; 7369 }; 7370 7371 trip-point2 { 7372 temperature = <125000>; 7373 hysteresis = <1000>; 7374 type = "critical"; 7375 }; 7376 }; 7377 }; 7378 7379 gpuss-3-thermal { 7380 polling-delay-passive = <10>; 7381 7382 thermal-sensors = <&tsens3 8>; 7383 7384 trips { 7385 trip-point0 { 7386 temperature = <85000>; 7387 hysteresis = <1000>; 7388 type = "passive"; 7389 }; 7390 7391 trip-point1 { 7392 temperature = <90000>; 7393 hysteresis = <1000>; 7394 type = "hot"; 7395 }; 7396 7397 trip-point2 { 7398 temperature = <125000>; 7399 hysteresis = <1000>; 7400 type = "critical"; 7401 }; 7402 }; 7403 }; 7404 7405 gpuss-4-thermal { 7406 polling-delay-passive = <10>; 7407 7408 thermal-sensors = <&tsens3 9>; 7409 7410 trips { 7411 trip-point0 { 7412 temperature = <85000>; 7413 hysteresis = <1000>; 7414 type = "passive"; 7415 }; 7416 7417 trip-point1 { 7418 temperature = <90000>; 7419 hysteresis = <1000>; 7420 type = "hot"; 7421 }; 7422 7423 trip-point2 { 7424 temperature = <125000>; 7425 hysteresis = <1000>; 7426 type = "critical"; 7427 }; 7428 }; 7429 }; 7430 7431 gpuss-5-thermal { 7432 polling-delay-passive = <10>; 7433 7434 thermal-sensors = <&tsens3 10>; 7435 7436 trips { 7437 trip-point0 { 7438 temperature = <85000>; 7439 hysteresis = <1000>; 7440 type = "passive"; 7441 }; 7442 7443 trip-point1 { 7444 temperature = <90000>; 7445 hysteresis = <1000>; 7446 type = "hot"; 7447 }; 7448 7449 trip-point2 { 7450 temperature = <125000>; 7451 hysteresis = <1000>; 7452 type = "critical"; 7453 }; 7454 }; 7455 }; 7456 7457 gpuss-6-thermal { 7458 polling-delay-passive = <10>; 7459 7460 thermal-sensors = <&tsens3 11>; 7461 7462 trips { 7463 trip-point0 { 7464 temperature = <85000>; 7465 hysteresis = <1000>; 7466 type = "passive"; 7467 }; 7468 7469 trip-point1 { 7470 temperature = <90000>; 7471 hysteresis = <1000>; 7472 type = "hot"; 7473 }; 7474 7475 trip-point2 { 7476 temperature = <125000>; 7477 hysteresis = <1000>; 7478 type = "critical"; 7479 }; 7480 }; 7481 }; 7482 7483 gpuss-7-thermal { 7484 polling-delay-passive = <10>; 7485 7486 thermal-sensors = <&tsens3 12>; 7487 7488 trips { 7489 trip-point0 { 7490 temperature = <85000>; 7491 hysteresis = <1000>; 7492 type = "passive"; 7493 }; 7494 7495 trip-point1 { 7496 temperature = <90000>; 7497 hysteresis = <1000>; 7498 type = "hot"; 7499 }; 7500 7501 trip-point2 { 7502 temperature = <125000>; 7503 hysteresis = <1000>; 7504 type = "critical"; 7505 }; 7506 }; 7507 }; 7508 7509 camera0-thermal { 7510 thermal-sensors = <&tsens3 13>; 7511 7512 trips { 7513 trip-point0 { 7514 temperature = <90000>; 7515 hysteresis = <2000>; 7516 type = "hot"; 7517 }; 7518 7519 camera0-critical { 7520 temperature = <115000>; 7521 hysteresis = <0>; 7522 type = "critical"; 7523 }; 7524 }; 7525 }; 7526 7527 camera1-thermal { 7528 thermal-sensors = <&tsens3 14>; 7529 7530 trips { 7531 trip-point0 { 7532 temperature = <90000>; 7533 hysteresis = <2000>; 7534 type = "hot"; 7535 }; 7536 7537 camera0-critical { 7538 temperature = <115000>; 7539 hysteresis = <0>; 7540 type = "critical"; 7541 }; 7542 }; 7543 }; 7544 }; 7545}; 7546