1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 44 enum amdgpu_mes_priority_level { 45 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 46 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 47 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 48 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 49 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 50 AMDGPU_MES_PRIORITY_NUM_LEVELS 51 }; 52 53 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 54 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 55 56 struct amdgpu_mes_funcs; 57 58 enum admgpu_mes_pipe { 59 AMDGPU_MES_SCHED_PIPE = 0, 60 AMDGPU_MES_KIQ_PIPE, 61 AMDGPU_MAX_MES_PIPES = 2, 62 }; 63 64 struct amdgpu_mes { 65 struct amdgpu_device *adev; 66 67 struct mutex mutex_hidden; 68 69 struct idr pasid_idr; 70 struct idr gang_id_idr; 71 struct idr queue_id_idr; 72 struct ida doorbell_ida; 73 74 spinlock_t queue_id_lock; 75 76 uint32_t sched_version; 77 uint32_t kiq_version; 78 79 uint32_t total_max_queue; 80 uint32_t max_doorbell_slices; 81 82 uint64_t default_process_quantum; 83 uint64_t default_gang_quantum; 84 85 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES]; 86 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES]; 87 88 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 89 90 /* mes ucode */ 91 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 92 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 93 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 94 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 95 96 /* mes ucode data */ 97 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 98 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 99 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 100 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 101 102 /* eop gpu obj */ 103 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 104 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 105 106 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 107 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 108 109 uint32_t vmid_mask_gfxhub; 110 uint32_t vmid_mask_mmhub; 111 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 112 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 113 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 114 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 115 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; 116 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; 117 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; 118 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; 119 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; 120 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; 121 uint32_t read_val_offs; 122 uint64_t read_val_gpu_addr; 123 uint32_t *read_val_ptr; 124 125 uint32_t saved_flags; 126 127 /* initialize kiq pipe */ 128 int (*kiq_hw_init)(struct amdgpu_device *adev); 129 int (*kiq_hw_fini)(struct amdgpu_device *adev); 130 131 /* MES doorbells */ 132 uint32_t db_start_dw_offset; 133 uint32_t num_mes_dbs; 134 unsigned long *doorbell_bitmap; 135 136 /* MES event log buffer */ 137 uint32_t event_log_size; 138 struct amdgpu_bo *event_log_gpu_obj; 139 uint64_t event_log_gpu_addr; 140 void *event_log_cpu_addr; 141 142 /* ip specific functions */ 143 const struct amdgpu_mes_funcs *funcs; 144 145 /* mes resource_1 bo*/ 146 struct amdgpu_bo *resource_1; 147 uint64_t resource_1_gpu_addr; 148 void *resource_1_addr; 149 150 }; 151 152 struct amdgpu_mes_process { 153 int pasid; 154 struct amdgpu_vm *vm; 155 uint64_t pd_gpu_addr; 156 struct amdgpu_bo *proc_ctx_bo; 157 uint64_t proc_ctx_gpu_addr; 158 void *proc_ctx_cpu_ptr; 159 uint64_t process_quantum; 160 struct list_head gang_list; 161 uint32_t doorbell_index; 162 struct mutex doorbell_lock; 163 }; 164 165 struct amdgpu_mes_gang { 166 int gang_id; 167 int priority; 168 int inprocess_gang_priority; 169 int global_priority_level; 170 struct list_head list; 171 struct amdgpu_mes_process *process; 172 struct amdgpu_bo *gang_ctx_bo; 173 uint64_t gang_ctx_gpu_addr; 174 void *gang_ctx_cpu_ptr; 175 uint64_t gang_quantum; 176 struct list_head queue_list; 177 }; 178 179 struct amdgpu_mes_queue { 180 struct list_head list; 181 struct amdgpu_mes_gang *gang; 182 int queue_id; 183 uint64_t doorbell_off; 184 struct amdgpu_bo *mqd_obj; 185 void *mqd_cpu_ptr; 186 uint64_t mqd_gpu_addr; 187 uint64_t wptr_gpu_addr; 188 int queue_type; 189 int paging; 190 struct amdgpu_ring *ring; 191 }; 192 193 struct amdgpu_mes_queue_properties { 194 int queue_type; 195 uint64_t hqd_base_gpu_addr; 196 uint64_t rptr_gpu_addr; 197 uint64_t wptr_gpu_addr; 198 uint64_t wptr_mc_addr; 199 uint32_t queue_size; 200 uint64_t eop_gpu_addr; 201 uint32_t hqd_pipe_priority; 202 uint32_t hqd_queue_priority; 203 bool paging; 204 struct amdgpu_ring *ring; 205 /* out */ 206 uint64_t doorbell_off; 207 }; 208 209 struct amdgpu_mes_gang_properties { 210 uint32_t priority; 211 uint32_t gang_quantum; 212 uint32_t inprocess_gang_priority; 213 uint32_t priority_level; 214 int global_priority_level; 215 }; 216 217 struct mes_add_queue_input { 218 uint32_t process_id; 219 uint64_t page_table_base_addr; 220 uint64_t process_va_start; 221 uint64_t process_va_end; 222 uint64_t process_quantum; 223 uint64_t process_context_addr; 224 uint64_t gang_quantum; 225 uint64_t gang_context_addr; 226 uint32_t inprocess_gang_priority; 227 uint32_t gang_global_priority_level; 228 uint32_t doorbell_offset; 229 uint64_t mqd_addr; 230 uint64_t wptr_addr; 231 uint64_t wptr_mc_addr; 232 uint32_t queue_type; 233 uint32_t paging; 234 uint32_t gws_base; 235 uint32_t gws_size; 236 uint64_t tba_addr; 237 uint64_t tma_addr; 238 uint32_t trap_en; 239 uint32_t skip_process_ctx_clear; 240 uint32_t is_kfd_process; 241 uint32_t is_aql_queue; 242 uint32_t queue_size; 243 uint32_t exclusively_scheduled; 244 }; 245 246 struct mes_remove_queue_input { 247 uint32_t doorbell_offset; 248 uint64_t gang_context_addr; 249 }; 250 251 struct mes_reset_queue_input { 252 uint32_t doorbell_offset; 253 uint64_t gang_context_addr; 254 }; 255 256 struct mes_map_legacy_queue_input { 257 uint32_t queue_type; 258 uint32_t doorbell_offset; 259 uint32_t pipe_id; 260 uint32_t queue_id; 261 uint64_t mqd_addr; 262 uint64_t wptr_addr; 263 }; 264 265 struct mes_unmap_legacy_queue_input { 266 enum amdgpu_unmap_queues_action action; 267 uint32_t queue_type; 268 uint32_t doorbell_offset; 269 uint32_t pipe_id; 270 uint32_t queue_id; 271 uint64_t trail_fence_addr; 272 uint64_t trail_fence_data; 273 }; 274 275 struct mes_suspend_gang_input { 276 bool suspend_all_gangs; 277 uint64_t gang_context_addr; 278 uint64_t suspend_fence_addr; 279 uint32_t suspend_fence_value; 280 }; 281 282 struct mes_resume_gang_input { 283 bool resume_all_gangs; 284 uint64_t gang_context_addr; 285 }; 286 287 struct mes_reset_legacy_queue_input { 288 uint32_t queue_type; 289 uint32_t doorbell_offset; 290 uint32_t pipe_id; 291 uint32_t queue_id; 292 uint64_t mqd_addr; 293 uint64_t wptr_addr; 294 uint32_t vmid; 295 }; 296 297 enum mes_misc_opcode { 298 MES_MISC_OP_WRITE_REG, 299 MES_MISC_OP_READ_REG, 300 MES_MISC_OP_WRM_REG_WAIT, 301 MES_MISC_OP_WRM_REG_WR_WAIT, 302 MES_MISC_OP_SET_SHADER_DEBUGGER, 303 }; 304 305 struct mes_misc_op_input { 306 enum mes_misc_opcode op; 307 308 union { 309 struct { 310 uint32_t reg_offset; 311 uint64_t buffer_addr; 312 } read_reg; 313 314 struct { 315 uint32_t reg_offset; 316 uint32_t reg_value; 317 } write_reg; 318 319 struct { 320 uint32_t ref; 321 uint32_t mask; 322 uint32_t reg0; 323 uint32_t reg1; 324 } wrm_reg; 325 326 struct { 327 uint64_t process_context_addr; 328 union { 329 struct { 330 uint32_t single_memop : 1; 331 uint32_t single_alu_op : 1; 332 uint32_t reserved: 29; 333 uint32_t process_ctx_flush: 1; 334 }; 335 uint32_t u32all; 336 } flags; 337 uint32_t spi_gdbg_per_vmid_cntl; 338 uint32_t tcp_watch_cntl[4]; 339 uint32_t trap_en; 340 } set_shader_debugger; 341 }; 342 }; 343 344 struct amdgpu_mes_funcs { 345 int (*add_hw_queue)(struct amdgpu_mes *mes, 346 struct mes_add_queue_input *input); 347 348 int (*remove_hw_queue)(struct amdgpu_mes *mes, 349 struct mes_remove_queue_input *input); 350 351 int (*map_legacy_queue)(struct amdgpu_mes *mes, 352 struct mes_map_legacy_queue_input *input); 353 354 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 355 struct mes_unmap_legacy_queue_input *input); 356 357 int (*suspend_gang)(struct amdgpu_mes *mes, 358 struct mes_suspend_gang_input *input); 359 360 int (*resume_gang)(struct amdgpu_mes *mes, 361 struct mes_resume_gang_input *input); 362 363 int (*misc_op)(struct amdgpu_mes *mes, 364 struct mes_misc_op_input *input); 365 366 int (*reset_legacy_queue)(struct amdgpu_mes *mes, 367 struct mes_reset_legacy_queue_input *input); 368 369 int (*reset_hw_queue)(struct amdgpu_mes *mes, 370 struct mes_reset_queue_input *input); 371 }; 372 373 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 374 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 375 376 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 377 378 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 379 int amdgpu_mes_init(struct amdgpu_device *adev); 380 void amdgpu_mes_fini(struct amdgpu_device *adev); 381 382 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 383 struct amdgpu_vm *vm); 384 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 385 386 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 387 struct amdgpu_mes_gang_properties *gprops, 388 int *gang_id); 389 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 390 391 int amdgpu_mes_suspend(struct amdgpu_device *adev); 392 int amdgpu_mes_resume(struct amdgpu_device *adev); 393 394 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 395 struct amdgpu_mes_queue_properties *qprops, 396 int *queue_id); 397 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 398 int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id); 399 400 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 401 struct amdgpu_ring *ring); 402 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 403 struct amdgpu_ring *ring, 404 enum amdgpu_unmap_queues_action action, 405 u64 gpu_addr, u64 seq); 406 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 407 struct amdgpu_ring *ring, 408 unsigned int vmid); 409 410 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 411 int amdgpu_mes_wreg(struct amdgpu_device *adev, 412 uint32_t reg, uint32_t val); 413 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 414 uint32_t val, uint32_t mask); 415 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 416 uint32_t reg0, uint32_t reg1, 417 uint32_t ref, uint32_t mask); 418 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 419 uint64_t process_context_addr, 420 uint32_t spi_gdbg_per_vmid_cntl, 421 const uint32_t *tcp_watch_cntl, 422 uint32_t flags, 423 bool trap_en); 424 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 425 uint64_t process_context_addr); 426 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 427 int queue_type, int idx, 428 struct amdgpu_mes_ctx_data *ctx_data, 429 struct amdgpu_ring **out); 430 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 431 struct amdgpu_ring *ring); 432 433 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 434 enum amdgpu_mes_priority_level prio); 435 436 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 437 struct amdgpu_mes_ctx_data *ctx_data); 438 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 439 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 440 struct amdgpu_vm *vm, 441 struct amdgpu_mes_ctx_data *ctx_data); 442 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, 443 struct amdgpu_mes_ctx_data *ctx_data); 444 445 int amdgpu_mes_self_test(struct amdgpu_device *adev); 446 447 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 448 449 /* 450 * MES lock can be taken in MMU notifiers. 451 * 452 * A bit more detail about why to set no-FS reclaim with MES lock: 453 * 454 * The purpose of the MMU notifier is to stop GPU access to memory so 455 * that the Linux VM subsystem can move pages around safely. This is 456 * done by preempting user mode queues for the affected process. When 457 * MES is used, MES lock needs to be taken to preempt the queues. 458 * 459 * The MMU notifier callback entry point in the driver is 460 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 461 * there is: 462 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 463 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 464 * 465 * The last part of the chain is a function pointer where we take the 466 * MES lock. 467 * 468 * The problem with taking locks in the MMU notifier is, that MMU 469 * notifiers can be called in reclaim-FS context. That's where the 470 * kernel frees up pages to make room for new page allocations under 471 * memory pressure. While we are running in reclaim-FS context, we must 472 * not trigger another memory reclaim operation because that would 473 * recursively reenter the reclaim code and cause a deadlock. The 474 * memalloc_nofs_save/restore calls guarantee that. 475 * 476 * In addition we also need to avoid lock dependencies on other locks taken 477 * under the MES lock, for example reservation locks. Here is a possible 478 * scenario of a deadlock: 479 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 480 * MMU notifier | blocks trying to take MES lock 481 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 482 * 483 * In this scenario Thread B gets involved in a deadlock even without 484 * triggering a reclaim-FS operation itself. 485 * To fix this and break the lock dependency chain you'd need to either: 486 * 1. protect reservation locks with memalloc_nofs_save/restore, or 487 * 2. avoid taking reservation locks under the MES lock. 488 * 489 * Reservation locks are taken all over the kernel in different subsystems, we 490 * have no control over them and their lock dependencies.So the only workable 491 * solution is to avoid taking other locks under the MES lock. 492 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 493 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 494 */ 495 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 496 { 497 mutex_lock(&mes->mutex_hidden); 498 mes->saved_flags = memalloc_noreclaim_save(); 499 } 500 501 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 502 { 503 memalloc_noreclaim_restore(mes->saved_flags); 504 mutex_unlock(&mes->mutex_hidden); 505 } 506 507 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 508 #endif /* __AMDGPU_MES_H__ */ 509