1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Fast Models 4 * 5 * Architecture Envelope Model (AEM) ARMv8-A 6 * ARMAEMv8AMPCT 7 * 8 * FVP Base RevC 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14 15/memreserve/ 0x80000000 0x00010000; 16 17#include "rtsm_ve-motherboard.dtsi" 18#include "rtsm_ve-motherboard-rs2.dtsi" 19 20/ { 21 model = "FVP Base RevC"; 22 compatible = "arm,fvp-base-revc", "arm,vexpress"; 23 interrupt-parent = <&gic>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 aliases { 32 serial0 = &v2m_serial0; 33 serial1 = &v2m_serial1; 34 serial2 = &v2m_serial2; 35 serial3 = &v2m_serial3; 36 }; 37 38 psci { 39 compatible = "arm,psci-0.2"; 40 method = "smc"; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,armv8"; 50 reg = <0x0 0x000>; 51 enable-method = "psci"; 52 i-cache-size = <0x8000>; 53 i-cache-line-size = <64>; 54 i-cache-sets = <256>; 55 d-cache-size = <0x8000>; 56 d-cache-line-size = <64>; 57 d-cache-sets = <256>; 58 next-level-cache = <&C0_L2>; 59 }; 60 cpu1: cpu@100 { 61 device_type = "cpu"; 62 compatible = "arm,armv8"; 63 reg = <0x0 0x100>; 64 enable-method = "psci"; 65 i-cache-size = <0x8000>; 66 i-cache-line-size = <64>; 67 i-cache-sets = <256>; 68 d-cache-size = <0x8000>; 69 d-cache-line-size = <64>; 70 d-cache-sets = <256>; 71 next-level-cache = <&C0_L2>; 72 }; 73 cpu2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "arm,armv8"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 i-cache-size = <0x8000>; 79 i-cache-line-size = <64>; 80 i-cache-sets = <256>; 81 d-cache-size = <0x8000>; 82 d-cache-line-size = <64>; 83 d-cache-sets = <256>; 84 next-level-cache = <&C0_L2>; 85 }; 86 cpu3: cpu@300 { 87 device_type = "cpu"; 88 compatible = "arm,armv8"; 89 reg = <0x0 0x300>; 90 enable-method = "psci"; 91 i-cache-size = <0x8000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <256>; 97 next-level-cache = <&C0_L2>; 98 }; 99 cpu4: cpu@10000 { 100 device_type = "cpu"; 101 compatible = "arm,armv8"; 102 reg = <0x0 0x10000>; 103 enable-method = "psci"; 104 i-cache-size = <0x8000>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <256>; 107 d-cache-size = <0x8000>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <256>; 110 next-level-cache = <&C1_L2>; 111 }; 112 cpu5: cpu@10100 { 113 device_type = "cpu"; 114 compatible = "arm,armv8"; 115 reg = <0x0 0x10100>; 116 enable-method = "psci"; 117 i-cache-size = <0x8000>; 118 i-cache-line-size = <64>; 119 i-cache-sets = <256>; 120 d-cache-size = <0x8000>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <256>; 123 next-level-cache = <&C1_L2>; 124 }; 125 cpu6: cpu@10200 { 126 device_type = "cpu"; 127 compatible = "arm,armv8"; 128 reg = <0x0 0x10200>; 129 enable-method = "psci"; 130 i-cache-size = <0x8000>; 131 i-cache-line-size = <64>; 132 i-cache-sets = <256>; 133 d-cache-size = <0x8000>; 134 d-cache-line-size = <64>; 135 d-cache-sets = <256>; 136 next-level-cache = <&C1_L2>; 137 }; 138 cpu7: cpu@10300 { 139 device_type = "cpu"; 140 compatible = "arm,armv8"; 141 reg = <0x0 0x10300>; 142 enable-method = "psci"; 143 i-cache-size = <0x8000>; 144 i-cache-line-size = <64>; 145 i-cache-sets = <256>; 146 d-cache-size = <0x8000>; 147 d-cache-line-size = <64>; 148 d-cache-sets = <256>; 149 next-level-cache = <&C1_L2>; 150 }; 151 C0_L2: l2-cache0 { 152 compatible = "cache"; 153 cache-size = <0x80000>; 154 cache-line-size = <64>; 155 cache-sets = <512>; 156 cache-level = <2>; 157 cache-unified; 158 }; 159 160 C1_L2: l2-cache1 { 161 compatible = "cache"; 162 cache-size = <0x80000>; 163 cache-line-size = <64>; 164 cache-sets = <512>; 165 cache-level = <2>; 166 cache-unified; 167 }; 168 }; 169 170 memory@80000000 { 171 device_type = "memory"; 172 reg = <0x00000000 0x80000000 0 0x80000000>, 173 <0x00000008 0x80000000 0 0x80000000>; 174 }; 175 176 reserved-memory { 177 #address-cells = <2>; 178 #size-cells = <2>; 179 ranges; 180 181 /* Chipselect 2,00000000 is physically at 0x18000000 */ 182 vram: vram@18000000 { 183 /* 8 MB of designated video RAM */ 184 compatible = "shared-dma-pool"; 185 reg = <0x00000000 0x18000000 0 0x00800000>; 186 no-map; 187 }; 188 }; 189 190 gic: interrupt-controller@2f000000 { 191 compatible = "arm,gic-v3"; 192 #interrupt-cells = <3>; 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges; 196 interrupt-controller; 197 reg = <0x0 0x2f000000 0 0x10000>, // GICD 198 <0x0 0x2f100000 0 0x200000>, // GICR 199 <0x0 0x2c000000 0 0x2000>, // GICC 200 <0x0 0x2c010000 0 0x2000>, // GICH 201 <0x0 0x2c02f000 0 0x2000>; // GICV 202 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 203 204 its: msi-controller@2f020000 { 205 #msi-cells = <1>; 206 compatible = "arm,gic-v3-its"; 207 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS 208 msi-controller; 209 }; 210 }; 211 212 timer { 213 compatible = "arm,armv8-timer"; 214 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 215 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 216 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 217 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 218 }; 219 220 pmu { 221 compatible = "arm,armv8-pmuv3"; 222 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 223 }; 224 225 spe-pmu { 226 compatible = "arm,statistical-profiling-extension-v1"; 227 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 228 }; 229 230 pci: pci@40000000 { 231 #address-cells = <0x3>; 232 #size-cells = <0x2>; 233 #interrupt-cells = <0x1>; 234 compatible = "pci-host-ecam-generic"; 235 device_type = "pci"; 236 bus-range = <0x0 0x1>; 237 reg = <0x0 0x40000000 0x0 0x10000000>; 238 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; 239 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 240 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 241 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 242 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 243 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 244 msi-map = <0x0 &its 0x0 0x10000>; 245 iommu-map = <0x0 &smmu 0x0 0x10000>; 246 247 dma-coherent; 248 ats-supported; 249 }; 250 251 smmu: iommu@2b400000 { 252 compatible = "arm,smmu-v3"; 253 reg = <0x0 0x2b400000 0x0 0x100000>; 254 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 255 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 256 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 257 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; 258 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 259 dma-coherent; 260 #iommu-cells = <1>; 261 msi-parent = <&its 0x10000>; 262 }; 263 264 panel { 265 compatible = "arm,rtsm-display"; 266 port { 267 panel_in: endpoint { 268 remote-endpoint = <&clcd_pads>; 269 }; 270 }; 271 }; 272 273 bus@8000000 { 274 #interrupt-cells = <1>; 275 interrupt-map-mask = <0 0 63>; 276 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 277 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 278 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 279 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 280 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 281 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 282 <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 283 <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 284 <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 285 <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 286 <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 287 <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 288 <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 289 <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 290 <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 291 <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 292 <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 293 <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 294 <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 295 <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 296 <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 297 <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 298 <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 299 <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 300 <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 301 <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 302 <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 303 <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 304 <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 305 <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 306 <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 307 <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 308 <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 309 <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 310 <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 311 <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 312 <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 313 <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 314 <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 315 <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 316 <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 317 <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 318 <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 319 <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 320 <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 321 <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 322 }; 323}; 324