1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> 5 */ 6#include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8&pinctrl { 9 /omit-if-no-ref/ 10 adc1_pins_a: adc1-pins-0 { 11 pins { 12 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ 13 }; 14 }; 15 16 /omit-if-no-ref/ 17 adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { 18 pins { 19 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 20 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ 21 }; 22 }; 23 24 /omit-if-no-ref/ 25 adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { 26 pins { 27 pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */ 28 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */ 29 }; 30 }; 31 32 /omit-if-no-ref/ 33 dcmipp_pins_a: dcmi-0 { 34 pins1 { 35 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ 36 <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */ 37 <STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */ 38 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ 39 <STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */ 40 <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */ 41 <STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */ 42 <STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */ 43 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ 44 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ 45 <STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */ 46 bias-disable; 47 }; 48 }; 49 50 /omit-if-no-ref/ 51 dcmipp_sleep_pins_a: dcmi-sleep-0 { 52 pins1 { 53 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ 54 <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */ 55 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */ 56 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ 57 <STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */ 58 <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */ 59 <STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */ 60 <STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */ 61 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ 62 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ 63 <STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */ 64 }; 65 }; 66 67 /omit-if-no-ref/ 68 eth1_rgmii_pins_a: eth1-rgmii-0 { 69 pins1 { 70 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 71 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 72 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 73 <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */ 74 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 75 <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */ 76 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ 77 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ 78 bias-disable; 79 drive-push-pull; 80 slew-rate = <2>; 81 }; 82 83 pins2 { 84 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 85 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 86 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ 87 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 88 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */ 89 <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */ 90 bias-disable; 91 }; 92 }; 93 94 /omit-if-no-ref/ 95 eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { 96 pins1 { 97 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 98 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 99 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 100 <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */ 101 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 102 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 103 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 104 <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ 105 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 106 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 107 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */ 108 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */ 109 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */ 110 <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */ 111 }; 112 }; 113 114 /omit-if-no-ref/ 115 eth1_rmii_pins_a: eth1-rmii-0 { 116 pins1 { 117 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */ 118 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */ 119 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */ 120 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */ 121 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ 122 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ 123 bias-disable; 124 drive-push-pull; 125 slew-rate = <1>; 126 }; 127 128 pins2 { 129 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */ 130 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */ 131 <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */ 132 bias-disable; 133 }; 134 }; 135 136 /omit-if-no-ref/ 137 eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { 138 pins1 { 139 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */ 140 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */ 141 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */ 142 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */ 143 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 144 <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ 145 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */ 146 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */ 147 <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */ 148 }; 149 }; 150 151 /omit-if-no-ref/ 152 eth2_rgmii_pins_a: eth2-rgmii-0 { 153 pins1 { 154 pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */ 155 <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */ 156 <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */ 157 <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */ 158 <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */ 159 <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */ 160 <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ 161 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ 162 bias-disable; 163 drive-push-pull; 164 slew-rate = <2>; 165 }; 166 167 pins2 { 168 pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */ 169 <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */ 170 <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */ 171 <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */ 172 <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */ 173 <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */ 174 bias-disable; 175 }; 176 }; 177 178 /omit-if-no-ref/ 179 eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { 180 pins1 { 181 pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ 182 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */ 183 <STM32_PINMUX('G', 1, ANALOG)>, /* ETH_RGMII_TXD2 */ 184 <STM32_PINMUX('E', 6, ANALOG)>, /* ETH_RGMII_TXD3 */ 185 <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_TX_CTL */ 186 <STM32_PINMUX('G', 3, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 187 <STM32_PINMUX('B', 6, ANALOG)>, /* ETH_MDIO */ 188 <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ 189 <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 190 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ 191 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 192 <STM32_PINMUX('A', 8, ANALOG)>, /* ETH_RGMII_RXD3 */ 193 <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */ 194 <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */ 195 }; 196 }; 197 198 /omit-if-no-ref/ 199 eth2_rmii_pins_a: eth2-rmii-0 { 200 pins1 { 201 pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */ 202 <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */ 203 <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */ 204 <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */ 205 <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */ 206 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ 207 bias-disable; 208 drive-push-pull; 209 slew-rate = <1>; 210 }; 211 212 pins2 { 213 pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */ 214 <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */ 215 <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */ 216 bias-disable; 217 }; 218 }; 219 220 /omit-if-no-ref/ 221 eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { 222 pins1 { 223 pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */ 224 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */ 225 <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */ 226 <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */ 227 <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */ 228 <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ 229 <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */ 230 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */ 231 <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */ 232 }; 233 }; 234 235 /omit-if-no-ref/ 236 goodix_pins_a: goodix-0 { 237 /* 238 * touchscreen reset needs to be configured 239 * via the pinctrl not the driver (a pull-down resistor 240 * has been soldered onto the reset line which forces 241 * the touchscreen to reset state). 242 */ 243 pins1 { 244 pinmux = <STM32_PINMUX('H', 2, GPIO)>; 245 output-high; 246 bias-pull-up; 247 }; 248 /* 249 * Interrupt line must have a pull-down resistor 250 * in order to freeze the i2c address at 0x5D 251 */ 252 pins2 { 253 pinmux = <STM32_PINMUX('F', 5, GPIO)>; 254 bias-pull-down; 255 }; 256 }; 257 258 /omit-if-no-ref/ 259 i2c1_pins_a: i2c1-0 { 260 pins { 261 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ 262 <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */ 263 bias-disable; 264 drive-open-drain; 265 slew-rate = <0>; 266 }; 267 }; 268 269 /omit-if-no-ref/ 270 i2c1_sleep_pins_a: i2c1-sleep-0 { 271 pins { 272 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ 273 <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */ 274 }; 275 }; 276 277 /omit-if-no-ref/ 278 i2c5_pins_a: i2c5-0 { 279 pins { 280 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ 281 <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */ 282 bias-disable; 283 drive-open-drain; 284 slew-rate = <0>; 285 }; 286 }; 287 288 /omit-if-no-ref/ 289 i2c5_sleep_pins_a: i2c5-sleep-0 { 290 pins { 291 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ 292 <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */ 293 }; 294 }; 295 296 /omit-if-no-ref/ 297 i2c5_pins_b: i2c5-1 { 298 pins { 299 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ 300 <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */ 301 bias-disable; 302 drive-open-drain; 303 slew-rate = <0>; 304 }; 305 }; 306 307 /omit-if-no-ref/ 308 i2c5_sleep_pins_b: i2c5-sleep-1 { 309 pins { 310 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ 311 <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */ 312 }; 313 }; 314 315 /omit-if-no-ref/ 316 ltdc_pins_a: ltdc-0 { 317 pins { 318 pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */ 319 <STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */ 320 <STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */ 321 <STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */ 322 <STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */ 323 <STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */ 324 <STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */ 325 <STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */ 326 <STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */ 327 <STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */ 328 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 329 <STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */ 330 <STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */ 331 <STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */ 332 <STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */ 333 <STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */ 334 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */ 335 <STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */ 336 <STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */ 337 <STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */ 338 <STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */ 339 <STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */ 340 bias-disable; 341 drive-push-pull; 342 slew-rate = <0>; 343 }; 344 }; 345 346 /omit-if-no-ref/ 347 ltdc_sleep_pins_a: ltdc-sleep-0 { 348 pins { 349 pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */ 350 <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */ 351 <STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */ 352 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */ 353 <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */ 354 <STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */ 355 <STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */ 356 <STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */ 357 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */ 358 <STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */ 359 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 360 <STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */ 361 <STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */ 362 <STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */ 363 <STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */ 364 <STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */ 365 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */ 366 <STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */ 367 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */ 368 <STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */ 369 <STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */ 370 <STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */ 371 }; 372 }; 373 374 /omit-if-no-ref/ 375 m_can1_pins_a: m-can1-0 { 376 pins1 { 377 pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */ 378 slew-rate = <1>; 379 drive-push-pull; 380 bias-disable; 381 }; 382 pins2 { 383 pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ 384 bias-disable; 385 }; 386 }; 387 388 /omit-if-no-ref/ 389 m_can1_sleep_pins_a: m_can1-sleep-0 { 390 pins { 391 pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */ 392 <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */ 393 }; 394 }; 395 396 /omit-if-no-ref/ 397 m_can2_pins_a: m-can2-0 { 398 pins1 { 399 pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */ 400 slew-rate = <1>; 401 drive-push-pull; 402 bias-disable; 403 }; 404 pins2 { 405 pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */ 406 bias-disable; 407 }; 408 }; 409 410 /omit-if-no-ref/ 411 m_can2_sleep_pins_a: m_can2-sleep-0 { 412 pins { 413 pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */ 414 <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */ 415 }; 416 }; 417 418 /omit-if-no-ref/ 419 mcp23017_pins_a: mcp23017-0 { 420 pins { 421 pinmux = <STM32_PINMUX('G', 12, GPIO)>; 422 bias-pull-up; 423 }; 424 }; 425 426 /omit-if-no-ref/ 427 pwm3_pins_a: pwm3-0 { 428 pins { 429 pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */ 430 bias-pull-down; 431 drive-push-pull; 432 slew-rate = <0>; 433 }; 434 }; 435 436 /omit-if-no-ref/ 437 pwm3_sleep_pins_a: pwm3-sleep-0 { 438 pins { 439 pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */ 440 }; 441 }; 442 443 /omit-if-no-ref/ 444 pwm4_pins_a: pwm4-0 { 445 pins { 446 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ 447 bias-pull-down; 448 drive-push-pull; 449 slew-rate = <0>; 450 }; 451 }; 452 453 /omit-if-no-ref/ 454 pwm4_sleep_pins_a: pwm4-sleep-0 { 455 pins { 456 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ 457 }; 458 }; 459 460 /omit-if-no-ref/ 461 pwm5_pins_a: pwm5-0 { 462 pins { 463 pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */ 464 bias-pull-down; 465 drive-push-pull; 466 slew-rate = <0>; 467 }; 468 }; 469 470 /omit-if-no-ref/ 471 pwm5_sleep_pins_a: pwm5-sleep-0 { 472 pins { 473 pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */ 474 }; 475 }; 476 477 /omit-if-no-ref/ 478 pwm8_pins_a: pwm8-0 { 479 pins { 480 pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ 481 bias-pull-down; 482 drive-push-pull; 483 slew-rate = <0>; 484 }; 485 }; 486 487 /omit-if-no-ref/ 488 pwm8_sleep_pins_a: pwm8-sleep-0 { 489 pins { 490 pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */ 491 }; 492 }; 493 494 /omit-if-no-ref/ 495 pwm13_pins_a: pwm13-0 { 496 pins { 497 pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */ 498 bias-pull-down; 499 drive-push-pull; 500 slew-rate = <0>; 501 }; 502 }; 503 504 /omit-if-no-ref/ 505 pwm13_sleep_pins_a: pwm13-sleep-0 { 506 pins { 507 pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */ 508 }; 509 }; 510 511 /omit-if-no-ref/ 512 pwm14_pins_a: pwm14-0 { 513 pins { 514 pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ 515 bias-pull-down; 516 drive-push-pull; 517 slew-rate = <0>; 518 }; 519 }; 520 521 /omit-if-no-ref/ 522 pwm14_sleep_pins_a: pwm14-sleep-0 { 523 pins { 524 pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */ 525 }; 526 }; 527 528 /omit-if-no-ref/ 529 qspi_clk_pins_a: qspi-clk-0 { 530 pins { 531 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 532 bias-disable; 533 drive-push-pull; 534 slew-rate = <3>; 535 }; 536 }; 537 538 /omit-if-no-ref/ 539 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { 540 pins { 541 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ 542 }; 543 }; 544 545 /omit-if-no-ref/ 546 qspi_bk1_pins_a: qspi-bk1-0 { 547 pins { 548 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 549 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 550 <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */ 551 <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */ 552 bias-disable; 553 drive-push-pull; 554 slew-rate = <1>; 555 }; 556 }; 557 558 /omit-if-no-ref/ 559 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { 560 pins { 561 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ 562 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ 563 <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */ 564 <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */ 565 }; 566 }; 567 568 /omit-if-no-ref/ 569 qspi_cs1_pins_a: qspi-cs1-0 { 570 pins { 571 pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */ 572 bias-pull-up; 573 drive-push-pull; 574 slew-rate = <1>; 575 }; 576 }; 577 578 /omit-if-no-ref/ 579 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { 580 pins { 581 pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */ 582 }; 583 }; 584 585 /omit-if-no-ref/ 586 sai1a_pins_a: sai1a-0 { 587 pins { 588 pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */ 589 <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */ 590 <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */ 591 slew-rate = <0>; 592 drive-push-pull; 593 bias-disable; 594 }; 595 }; 596 597 /omit-if-no-ref/ 598 sai1a_sleep_pins_a: sai1a-sleep-0 { 599 pins { 600 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */ 601 <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */ 602 <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */ 603 }; 604 }; 605 606 /omit-if-no-ref/ 607 sai1b_pins_a: sai1b-0 { 608 pins { 609 pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */ 610 bias-disable; 611 }; 612 }; 613 614 /omit-if-no-ref/ 615 sai1b_sleep_pins_a: sai1b-sleep-0 { 616 pins { 617 pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */ 618 }; 619 }; 620 621 /omit-if-no-ref/ 622 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 623 pins { 624 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 625 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 626 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 627 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 628 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 629 slew-rate = <1>; 630 drive-push-pull; 631 bias-disable; 632 }; 633 }; 634 635 /omit-if-no-ref/ 636 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 637 pins1 { 638 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 639 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 640 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 641 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 642 slew-rate = <1>; 643 drive-push-pull; 644 bias-disable; 645 }; 646 pins2 { 647 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 648 slew-rate = <1>; 649 drive-open-drain; 650 bias-disable; 651 }; 652 }; 653 654 /omit-if-no-ref/ 655 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 656 pins { 657 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 658 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 659 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 660 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 661 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 662 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 663 }; 664 }; 665 666 /omit-if-no-ref/ 667 sdmmc1_clk_pins_a: sdmmc1-clk-0 { 668 pins { 669 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 670 slew-rate = <1>; 671 drive-push-pull; 672 bias-disable; 673 }; 674 }; 675 676 /omit-if-no-ref/ 677 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 678 pins { 679 pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ 680 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ 681 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ 682 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */ 683 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 684 slew-rate = <1>; 685 drive-push-pull; 686 bias-pull-up; 687 }; 688 }; 689 690 /omit-if-no-ref/ 691 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { 692 pins1 { 693 pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ 694 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ 695 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ 696 <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */ 697 slew-rate = <1>; 698 drive-push-pull; 699 bias-pull-up; 700 }; 701 pins2 { 702 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 703 slew-rate = <1>; 704 drive-open-drain; 705 bias-pull-up; 706 }; 707 }; 708 709 /omit-if-no-ref/ 710 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { 711 pins { 712 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 713 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ 714 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 715 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 716 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 717 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 718 }; 719 }; 720 721 /omit-if-no-ref/ 722 sdmmc2_clk_pins_a: sdmmc2-clk-0 { 723 pins { 724 pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ 725 slew-rate = <1>; 726 drive-push-pull; 727 bias-pull-up; 728 }; 729 }; 730 731 /omit-if-no-ref/ 732 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 733 pins { 734 pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */ 735 <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */ 736 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 737 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 738 slew-rate = <1>; 739 drive-push-pull; 740 bias-pull-up; 741 }; 742 }; 743 744 /omit-if-no-ref/ 745 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { 746 pins { 747 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */ 748 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */ 749 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 750 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 751 }; 752 }; 753 754 /omit-if-no-ref/ 755 spi2_pins_a: spi2-0 { 756 pins1 { 757 pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */ 758 <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */ 759 bias-disable; 760 drive-push-pull; 761 slew-rate = <1>; 762 }; 763 764 pins2 { 765 pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */ 766 bias-disable; 767 }; 768 }; 769 770 /omit-if-no-ref/ 771 spi2_sleep_pins_a: spi2-sleep-0 { 772 pins { 773 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */ 774 <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */ 775 <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */ 776 }; 777 }; 778 779 /omit-if-no-ref/ 780 spi3_pins_a: spi3-0 { 781 pins1 { 782 pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */ 783 <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */ 784 bias-disable; 785 drive-push-pull; 786 slew-rate = <1>; 787 }; 788 789 pins2 { 790 pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */ 791 bias-disable; 792 }; 793 }; 794 795 /omit-if-no-ref/ 796 spi3_sleep_pins_a: spi3-sleep-0 { 797 pins { 798 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */ 799 <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */ 800 <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */ 801 }; 802 }; 803 804 /omit-if-no-ref/ 805 spi5_pins_a: spi5-0 { 806 pins1 { 807 pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ 808 <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */ 809 bias-disable; 810 drive-push-pull; 811 slew-rate = <1>; 812 }; 813 814 pins2 { 815 pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */ 816 bias-disable; 817 }; 818 }; 819 820 /omit-if-no-ref/ 821 spi5_sleep_pins_a: spi5-sleep-0 { 822 pins { 823 pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ 824 <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */ 825 <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */ 826 }; 827 }; 828 829 /omit-if-no-ref/ 830 stm32g0_intn_pins_a: stm32g0-intn-0 { 831 pins { 832 pinmux = <STM32_PINMUX('I', 2, GPIO)>; 833 bias-pull-up; 834 }; 835 }; 836 837 /omit-if-no-ref/ 838 uart4_pins_a: uart4-0 { 839 pins1 { 840 pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ 841 bias-disable; 842 drive-push-pull; 843 slew-rate = <0>; 844 }; 845 pins2 { 846 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ 847 bias-disable; 848 }; 849 }; 850 851 /omit-if-no-ref/ 852 uart4_idle_pins_a: uart4-idle-0 { 853 pins1 { 854 pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */ 855 }; 856 pins2 { 857 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ 858 bias-disable; 859 }; 860 }; 861 862 /omit-if-no-ref/ 863 uart4_sleep_pins_a: uart4-sleep-0 { 864 pins { 865 pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */ 866 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ 867 }; 868 }; 869 870 /omit-if-no-ref/ 871 uart4_pins_b: uart4-1 { 872 pins1 { 873 pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */ 874 bias-disable; 875 drive-push-pull; 876 slew-rate = <0>; 877 }; 878 pins2 { 879 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ 880 bias-pull-up; 881 }; 882 }; 883 884 /omit-if-no-ref/ 885 uart4_idle_pins_b: uart4-idle-1 { 886 pins1 { 887 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */ 888 }; 889 pins2 { 890 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ 891 bias-pull-up; 892 }; 893 }; 894 895 /omit-if-no-ref/ 896 uart4_sleep_pins_b: uart4-sleep-1 { 897 pins { 898 pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */ 899 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ 900 }; 901 }; 902 903 /omit-if-no-ref/ 904 uart7_pins_a: uart7-0 { 905 pins1 { 906 pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */ 907 <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ 908 bias-disable; 909 drive-push-pull; 910 slew-rate = <0>; 911 }; 912 pins2 { 913 pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */ 914 <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */ 915 bias-disable; 916 }; 917 }; 918 919 /omit-if-no-ref/ 920 uart7_idle_pins_a: uart7-idle-0 { 921 pins1 { 922 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ 923 <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ 924 }; 925 pins2 { 926 pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ 927 bias-disable; 928 drive-push-pull; 929 slew-rate = <0>; 930 }; 931 pins3 { 932 pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ 933 bias-disable; 934 }; 935 }; 936 937 /omit-if-no-ref/ 938 uart7_sleep_pins_a: uart7-sleep-0 { 939 pins { 940 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ 941 <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */ 942 <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */ 943 <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ 944 }; 945 }; 946 947 /omit-if-no-ref/ 948 uart8_pins_a: uart8-0 { 949 pins1 { 950 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ 951 bias-disable; 952 drive-push-pull; 953 slew-rate = <0>; 954 }; 955 pins2 { 956 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ 957 bias-pull-up; 958 }; 959 }; 960 961 /omit-if-no-ref/ 962 uart8_idle_pins_a: uart8-idle-0 { 963 pins1 { 964 pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */ 965 }; 966 pins2 { 967 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ 968 bias-pull-up; 969 }; 970 }; 971 972 /omit-if-no-ref/ 973 uart8_sleep_pins_a: uart8-sleep-0 { 974 pins { 975 pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */ 976 <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */ 977 }; 978 }; 979 980 /omit-if-no-ref/ 981 usart1_pins_a: usart1-0 { 982 pins1 { 983 pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ 984 <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ 985 bias-disable; 986 drive-push-pull; 987 slew-rate = <0>; 988 }; 989 pins2 { 990 pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */ 991 <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */ 992 bias-pull-up; 993 }; 994 }; 995 996 /omit-if-no-ref/ 997 usart1_idle_pins_a: usart1-idle-0 { 998 pins1 { 999 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ 1000 <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */ 1001 }; 1002 pins2 { 1003 pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ 1004 bias-disable; 1005 drive-push-pull; 1006 slew-rate = <0>; 1007 }; 1008 pins3 { 1009 pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */ 1010 bias-pull-up; 1011 }; 1012 }; 1013 1014 /omit-if-no-ref/ 1015 usart1_sleep_pins_a: usart1-sleep-0 { 1016 pins { 1017 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ 1018 <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */ 1019 <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */ 1020 <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */ 1021 }; 1022 }; 1023 1024 /omit-if-no-ref/ 1025 usart1_pins_b: usart1-1 { 1026 pins1 { 1027 pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */ 1028 bias-disable; 1029 drive-push-pull; 1030 slew-rate = <0>; 1031 }; 1032 pins2 { 1033 pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ 1034 bias-pull-up; 1035 }; 1036 }; 1037 1038 /omit-if-no-ref/ 1039 usart1_idle_pins_b: usart1-idle-1 { 1040 pins1 { 1041 pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */ 1042 }; 1043 pins2 { 1044 pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ 1045 bias-pull-up; 1046 }; 1047 }; 1048 1049 /omit-if-no-ref/ 1050 usart1_sleep_pins_b: usart1-sleep-1 { 1051 pins { 1052 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ 1053 <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */ 1054 }; 1055 }; 1056 1057 /omit-if-no-ref/ 1058 usart2_pins_a: usart2-0 { 1059 pins1 { 1060 pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */ 1061 <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ 1062 bias-disable; 1063 drive-push-pull; 1064 slew-rate = <0>; 1065 }; 1066 pins2 { 1067 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ 1068 <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */ 1069 bias-disable; 1070 }; 1071 }; 1072 1073 /omit-if-no-ref/ 1074 usart2_idle_pins_a: usart2-idle-0 { 1075 pins1 { 1076 pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ 1077 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ 1078 }; 1079 pins2 { 1080 pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */ 1081 bias-disable; 1082 drive-push-pull; 1083 slew-rate = <0>; 1084 }; 1085 pins3 { 1086 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ 1087 bias-disable; 1088 }; 1089 }; 1090 1091 /omit-if-no-ref/ 1092 usart2_sleep_pins_a: usart2-sleep-0 { 1093 pins { 1094 pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ 1095 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 1096 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ 1097 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ 1098 }; 1099 }; 1100 1101 /omit-if-no-ref/ 1102 usart2_pins_b: usart2-1 { 1103 pins1 { 1104 pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */ 1105 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 1106 bias-disable; 1107 drive-push-pull; 1108 slew-rate = <0>; 1109 }; 1110 pins2 { 1111 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ 1112 <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */ 1113 bias-disable; 1114 }; 1115 }; 1116 1117 /omit-if-no-ref/ 1118 usart2_idle_pins_b: usart2-idle-1 { 1119 pins1 { 1120 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ 1121 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 1122 }; 1123 pins2 { 1124 pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 1125 bias-disable; 1126 drive-push-pull; 1127 slew-rate = <0>; 1128 }; 1129 pins3 { 1130 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ 1131 bias-disable; 1132 }; 1133 }; 1134 1135 /omit-if-no-ref/ 1136 usart2_sleep_pins_b: usart2-sleep-1 { 1137 pins { 1138 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ 1139 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ 1140 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ 1141 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 1142 }; 1143 }; 1144}; 1145