af94002b | 13-Jan-2021 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Fixup swapon
Current csky's swappon is broken by wrong swap PTE entry format. Now redesign the new format for abiv1 & abiv2 and make swappon + zram work properly on csky machines.
C-SKY PTE h
csky: Fixup swapon
Current csky's swappon is broken by wrong swap PTE entry format. Now redesign the new format for abiv1 & abiv2 and make swappon + zram work properly on csky machines.
C-SKY PTE has VALID, DIRTY to emulate PRESENT, READ, WRITE, EXEC attributes. GLOBAL bit is shared by two pages in the same tlb entry. So we need to keep GLOBAL, VALID, PRESENT zero in swp_pte.
To distinguish PAGE_NONE and swp_pte, we need to use an additional bit (abiv1 is _PAGE_READ, abiv2 is _PAGE_WRITE).
Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: Arnd Bergmann <arnd@arndb.de>
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a8fac05a | 11-Jan-2021 |
Guo Ren <guoren@linux.alibaba.com> |
csky: pgtable.h: Coding convention
C-SKY page table attributes only have 'Dirty' and 'Valid' to emulate 'PRESENT, READ, WRITE, EXEC, DIRTY, ACCESSED'.
This patch cleanup unnecessary definition.
Si
csky: pgtable.h: Coding convention
C-SKY page table attributes only have 'Dirty' and 'Valid' to emulate 'PRESENT, READ, WRITE, EXEC, DIRTY, ACCESSED'.
This patch cleanup unnecessary definition.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: Arnd Bergmann <arnd@arndb.de>
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20f69538 | 24-May-2020 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Coding convention in entry.S
There is no fixup or feature in the patch, we only cleanup with:
- Remove unnecessary reg used (r11, r12), just use r9 & r10 & syscallid regs as temp useage.
csky: Coding convention in entry.S
There is no fixup or feature in the patch, we only cleanup with:
- Remove unnecessary reg used (r11, r12), just use r9 & r10 & syscallid regs as temp useage. - Add _TIF_SYSCALL_WORK and _TIF_WORK_MASK to gather macros.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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e0bbb538 | 24-May-2020 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Fixup abiv2 syscall_trace break a4 & a5
Current implementation could destory a4 & a5 when strace, so we need to get them from pt_regs by SAVE_ALL.
Signed-off-by: Guo Ren <guoren@linux.alibaba
csky: Fixup abiv2 syscall_trace break a4 & a5
Current implementation could destory a4 & a5 when strace, so we need to get them from pt_regs by SAVE_ALL.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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aefd9461 | 28-Mar-2020 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Fixup cpu speculative execution to IO area
For the memory size ( > 512MB, < 1GB), the MSA setting is:
- SSEG0: PHY_START , PHY_START + 512MB - SSEG1: PHY_START + 512MB, PHY_START + 1
csky: Fixup cpu speculative execution to IO area
For the memory size ( > 512MB, < 1GB), the MSA setting is:
- SSEG0: PHY_START , PHY_START + 512MB - SSEG1: PHY_START + 512MB, PHY_START + 1GB
But the real memory is no more than 1GB, there is a gap between the end size of memory and border of 1GB. CPU could speculatively execute to that gap and if the gap of the bus couldn't respond to the CPU request, then the crash will happen.
Now make the setting with:
- SSEG0: PHY_START , PHY_START + 512MB (no change) - SSEG1: Disabled (We use highmem to use the memory of 512MB~1GB)
We also deprecated zhole_szie[] settings, it's only used by arm style CPUs. All memory gap should use Reserved setting of dts in csky system.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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89a3927a | 18-Feb-2020 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Implement ftrace with regs
This patch implements FTRACE_WITH_REGS for csky, which allows a traced function's arguments (and some other registers) to be captured into a struct pt_regs, allowing
csky: Implement ftrace with regs
This patch implements FTRACE_WITH_REGS for csky, which allows a traced function's arguments (and some other registers) to be captured into a struct pt_regs, allowing these to be inspected and/or modified.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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cc1f6563 | 27-Jan-2020 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Optimize abiv2 copy_to_user_page with VM_EXEC
Only when vma is for VM_EXEC, we need sync dcache & icache. eg: - gdb ptrace modify user space instruction code area.
Add VM_EXEC condition to r
csky: Optimize abiv2 copy_to_user_page with VM_EXEC
Only when vma is for VM_EXEC, we need sync dcache & icache. eg: - gdb ptrace modify user space instruction code area.
Add VM_EXEC condition to reduce unnecessary cache flush.
The abiv1 cpus' cache are all VIPT, so we still need to deal with dcache aliasing problem. But there is optimized way to use cache color, just like what's done in arch/csky/abiv1/inc/abi/page.h.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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d936a7e7 | 26-Jan-2020 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Enable defer flush_dcache_page for abiv2 cpus (807/810/860)
Instead of flushing cache per update_mmu_cache() called, we use flush_dcache_page to reduce the frequency of flashing the cache.
As
csky: Enable defer flush_dcache_page for abiv2 cpus (807/810/860)
Instead of flushing cache per update_mmu_cache() called, we use flush_dcache_page to reduce the frequency of flashing the cache.
As abiv2 cpus are all PIPT for icache & dcache, we needn't handle dcache aliasing problem. But their icache can't snoop dcache, so we still need sync_icache_dcache in update_mmu_cache().
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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a1176734 | 24-Jan-2020 |
Guo Ren <guoren@linux.alibaba.com> |
csky: Remove unnecessary flush_icache_* implementation
The abiv2 CPUs are all PIPT cache, so there is no need to implement flush_icache_page function.
The function flush_icache_user_range hasn't be
csky: Remove unnecessary flush_icache_* implementation
The abiv2 CPUs are all PIPT cache, so there is no need to implement flush_icache_page function.
The function flush_icache_user_range hasn't been used, so just remove it.
The function flush_cache_range is not necessary for PIPT cache when tlb mapping changed.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
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