1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2021 Maxlinear Corporation 3 * Copyright (C) 2020 Intel Corporation 4 * 5 * Drivers for Maxlinear Ethernet GPY 6 * 7 */ 8 9 #include <linux/module.h> 10 #include <linux/bitfield.h> 11 #include <linux/hwmon.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/polynomial.h> 15 #include <linux/netdevice.h> 16 17 /* PHY ID */ 18 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC 19 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9 20 #define PHY_ID_GPY2xx 0x67C9DC00 21 #define PHY_ID_GPY115B 0x67C9DF00 22 #define PHY_ID_GPY115C 0x67C9DF10 23 #define PHY_ID_GPY211B 0x67C9DE08 24 #define PHY_ID_GPY211C 0x67C9DE10 25 #define PHY_ID_GPY212B 0x67C9DE09 26 #define PHY_ID_GPY212C 0x67C9DE20 27 #define PHY_ID_GPY215B 0x67C9DF04 28 #define PHY_ID_GPY215C 0x67C9DF20 29 #define PHY_ID_GPY241B 0x67C9DE40 30 #define PHY_ID_GPY241BM 0x67C9DE80 31 #define PHY_ID_GPY245B 0x67C9DEC0 32 33 #define PHY_CTL1 0x13 34 #define PHY_CTL1_MDICD BIT(3) 35 #define PHY_CTL1_MDIAB BIT(2) 36 #define PHY_CTL1_AMDIX BIT(0) 37 #define PHY_MIISTAT 0x18 /* MII state */ 38 #define PHY_IMASK 0x19 /* interrupt mask */ 39 #define PHY_ISTAT 0x1A /* interrupt status */ 40 #define PHY_FWV 0x1E /* firmware version */ 41 42 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) 43 #define PHY_MIISTAT_DPX BIT(3) 44 #define PHY_MIISTAT_LS BIT(10) 45 46 #define PHY_MIISTAT_SPD_10 0 47 #define PHY_MIISTAT_SPD_100 1 48 #define PHY_MIISTAT_SPD_1000 2 49 #define PHY_MIISTAT_SPD_2500 4 50 51 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */ 52 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */ 53 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */ 54 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */ 55 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */ 56 #define PHY_IMASK_LSTC BIT(0) /* Link state change */ 57 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \ 58 PHY_IMASK_LSPC | \ 59 PHY_IMASK_DXMC | \ 60 PHY_IMASK_ADSC | \ 61 PHY_IMASK_ANC) 62 63 #define PHY_FWV_REL_MASK BIT(15) 64 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) 65 #define PHY_FWV_MINOR_MASK GENMASK(7, 0) 66 67 #define PHY_PMA_MGBT_POLARITY 0x82 68 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) 69 #define PHY_MDI_MDI_X_NORMAL 0x3 70 #define PHY_MDI_MDI_X_AB 0x2 71 #define PHY_MDI_MDI_X_CD 0x1 72 #define PHY_MDI_MDI_X_CROSS 0x0 73 74 /* SGMII */ 75 #define VSPEC1_SGMII_CTRL 0x08 76 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ 77 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */ 78 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \ 79 VSPEC1_SGMII_CTRL_ANRS) 80 81 /* Temperature sensor */ 82 #define VSPEC1_TEMP_STA 0x0E 83 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0) 84 85 /* Mailbox */ 86 #define VSPEC1_MBOX_DATA 0x5 87 #define VSPEC1_MBOX_ADDRLO 0x6 88 #define VSPEC1_MBOX_CMD 0x7 89 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0) 90 #define VSPEC1_MBOX_CMD_RD (0 << 8) 91 #define VSPEC1_MBOX_CMD_READY BIT(15) 92 93 /* WoL */ 94 #define VPSPEC2_WOL_CTL 0x0E06 95 #define VPSPEC2_WOL_AD01 0x0E08 96 #define VPSPEC2_WOL_AD23 0x0E09 97 #define VPSPEC2_WOL_AD45 0x0E0A 98 #define WOL_EN BIT(0) 99 100 /* Internal registers, access via mbox */ 101 #define REG_GPIO0_OUT 0xd3ce00 102 103 struct gpy_priv { 104 /* serialize mailbox acesses */ 105 struct mutex mbox_lock; 106 107 u8 fw_major; 108 u8 fw_minor; 109 }; 110 111 static const struct { 112 int major; 113 int minor; 114 } ver_need_sgmii_reaneg[] = { 115 {7, 0x6D}, 116 {8, 0x6D}, 117 {9, 0x73}, 118 }; 119 120 #if IS_ENABLED(CONFIG_HWMON) 121 /* The original translation formulae of the temperature (in degrees of Celsius) 122 * are as follows: 123 * 124 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) + 125 * 3.0762e-1*(N^1) + -5.2156e1 126 * 127 * where [-52.156, 137.961]C and N = [0, 1023]. 128 * 129 * They must be accordingly altered to be suitable for the integer arithmetics. 130 * The technique is called 'factor redistribution', which just makes sure the 131 * multiplications and divisions are made so to have a result of the operations 132 * within the integer numbers limit. In addition we need to translate the 133 * formulae to accept millidegrees of Celsius. Here what it looks like after 134 * the alterations: 135 * 136 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) + 137 * 307620e-3*(N^1) + -52156 138 * 139 * where T = [-52156, 137961]mC and N = [0, 1023]. 140 */ 141 static const struct polynomial poly_N_to_temp = { 142 .terms = { 143 {4, -25761, 1000, 1}, 144 {3, 97332, 1000, 1}, 145 {2, -191650, 1000, 1}, 146 {1, 307620, 1000, 1}, 147 {0, -52156, 1, 1} 148 } 149 }; 150 151 static int gpy_hwmon_read(struct device *dev, 152 enum hwmon_sensor_types type, 153 u32 attr, int channel, long *value) 154 { 155 struct phy_device *phydev = dev_get_drvdata(dev); 156 int ret; 157 158 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA); 159 if (ret < 0) 160 return ret; 161 if (!ret) 162 return -ENODATA; 163 164 *value = polynomial_calc(&poly_N_to_temp, 165 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret)); 166 167 return 0; 168 } 169 170 static umode_t gpy_hwmon_is_visible(const void *data, 171 enum hwmon_sensor_types type, 172 u32 attr, int channel) 173 { 174 return 0444; 175 } 176 177 static const struct hwmon_channel_info *gpy_hwmon_info[] = { 178 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 179 NULL 180 }; 181 182 static const struct hwmon_ops gpy_hwmon_hwmon_ops = { 183 .is_visible = gpy_hwmon_is_visible, 184 .read = gpy_hwmon_read, 185 }; 186 187 static const struct hwmon_chip_info gpy_hwmon_chip_info = { 188 .ops = &gpy_hwmon_hwmon_ops, 189 .info = gpy_hwmon_info, 190 }; 191 192 static int gpy_hwmon_register(struct phy_device *phydev) 193 { 194 struct device *dev = &phydev->mdio.dev; 195 struct device *hwmon_dev; 196 char *hwmon_name; 197 198 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev)); 199 if (IS_ERR(hwmon_name)) 200 return PTR_ERR(hwmon_name); 201 202 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name, 203 phydev, 204 &gpy_hwmon_chip_info, 205 NULL); 206 207 return PTR_ERR_OR_ZERO(hwmon_dev); 208 } 209 #else 210 static int gpy_hwmon_register(struct phy_device *phydev) 211 { 212 return 0; 213 } 214 #endif 215 216 static int gpy_mbox_read(struct phy_device *phydev, u32 addr) 217 { 218 struct gpy_priv *priv = phydev->priv; 219 int val, ret; 220 u16 cmd; 221 222 mutex_lock(&priv->mbox_lock); 223 224 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, 225 addr); 226 if (ret) 227 goto out; 228 229 cmd = VSPEC1_MBOX_CMD_RD; 230 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16); 231 232 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); 233 if (ret) 234 goto out; 235 236 /* The mbox read is used in the interrupt workaround. It was observed 237 * that a read might take up to 2.5ms. This is also the time for which 238 * the interrupt line is stuck low. To be on the safe side, poll the 239 * ready bit for 10ms. 240 */ 241 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 242 VSPEC1_MBOX_CMD, val, 243 (val & VSPEC1_MBOX_CMD_READY), 244 500, 10000, false); 245 if (ret) 246 goto out; 247 248 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA); 249 250 out: 251 mutex_unlock(&priv->mbox_lock); 252 return ret; 253 } 254 255 static int gpy_config_init(struct phy_device *phydev) 256 { 257 int ret; 258 259 /* Mask all interrupts */ 260 ret = phy_write(phydev, PHY_IMASK, 0); 261 if (ret) 262 return ret; 263 264 /* Clear all pending interrupts */ 265 ret = phy_read(phydev, PHY_ISTAT); 266 return ret < 0 ? ret : 0; 267 } 268 269 static bool gpy_has_broken_mdint(struct phy_device *phydev) 270 { 271 /* At least these PHYs are known to have broken interrupt handling */ 272 return phydev->drv->phy_id == PHY_ID_GPY215B || 273 phydev->drv->phy_id == PHY_ID_GPY215C; 274 } 275 276 static int gpy_probe(struct phy_device *phydev) 277 { 278 struct device *dev = &phydev->mdio.dev; 279 struct gpy_priv *priv; 280 int fw_version; 281 int ret; 282 283 if (!phydev->is_c45) { 284 ret = phy_get_c45_ids(phydev); 285 if (ret < 0) 286 return ret; 287 } 288 289 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 290 if (!priv) 291 return -ENOMEM; 292 phydev->priv = priv; 293 mutex_init(&priv->mbox_lock); 294 295 fw_version = phy_read(phydev, PHY_FWV); 296 if (fw_version < 0) 297 return fw_version; 298 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version); 299 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version); 300 301 ret = gpy_hwmon_register(phydev); 302 if (ret) 303 return ret; 304 305 /* Show GPY PHY FW version in dmesg */ 306 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n", 307 priv->fw_major, priv->fw_minor, fw_version, 308 fw_version & PHY_FWV_REL_MASK ? "" : " test version"); 309 310 return 0; 311 } 312 313 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev) 314 { 315 struct gpy_priv *priv = phydev->priv; 316 size_t i; 317 318 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) { 319 if (priv->fw_major != ver_need_sgmii_reaneg[i].major) 320 continue; 321 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor) 322 return true; 323 break; 324 } 325 326 return false; 327 } 328 329 static bool gpy_2500basex_chk(struct phy_device *phydev) 330 { 331 int ret; 332 333 ret = phy_read(phydev, PHY_MIISTAT); 334 if (ret < 0) { 335 phydev_err(phydev, "Error: MDIO register access failed: %d\n", 336 ret); 337 return false; 338 } 339 340 if (!(ret & PHY_MIISTAT_LS) || 341 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500) 342 return false; 343 344 phydev->speed = SPEED_2500; 345 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 346 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 347 VSPEC1_SGMII_CTRL_ANEN, 0); 348 return true; 349 } 350 351 static bool gpy_sgmii_aneg_en(struct phy_device *phydev) 352 { 353 int ret; 354 355 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL); 356 if (ret < 0) { 357 phydev_err(phydev, "Error: MMD register access failed: %d\n", 358 ret); 359 return true; 360 } 361 362 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; 363 } 364 365 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) 366 { 367 int ret; 368 u16 val; 369 370 switch (ctrl) { 371 case ETH_TP_MDI_AUTO: 372 val = PHY_CTL1_AMDIX; 373 break; 374 case ETH_TP_MDI_X: 375 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); 376 break; 377 case ETH_TP_MDI: 378 val = 0; 379 break; 380 default: 381 return 0; 382 } 383 384 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | 385 PHY_CTL1_MDICD, val); 386 if (ret < 0) 387 return ret; 388 389 return genphy_c45_restart_aneg(phydev); 390 } 391 392 static int gpy_config_aneg(struct phy_device *phydev) 393 { 394 bool changed = false; 395 u32 adv; 396 int ret; 397 398 if (phydev->autoneg == AUTONEG_DISABLE) { 399 /* Configure half duplex with genphy_setup_forced, 400 * because genphy_c45_pma_setup_forced does not support. 401 */ 402 return phydev->duplex != DUPLEX_FULL 403 ? genphy_setup_forced(phydev) 404 : genphy_c45_pma_setup_forced(phydev); 405 } 406 407 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); 408 if (ret < 0) 409 return ret; 410 411 ret = genphy_c45_an_config_aneg(phydev); 412 if (ret < 0) 413 return ret; 414 if (ret > 0) 415 changed = true; 416 417 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 418 ret = phy_modify_changed(phydev, MII_CTRL1000, 419 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 420 adv); 421 if (ret < 0) 422 return ret; 423 if (ret > 0) 424 changed = true; 425 426 ret = genphy_c45_check_and_restart_aneg(phydev, changed); 427 if (ret < 0) 428 return ret; 429 430 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 431 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 432 return 0; 433 434 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is 435 * disabled. 436 */ 437 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) || 438 !gpy_sgmii_aneg_en(phydev)) 439 return 0; 440 441 /* There is a design constraint in GPY2xx device where SGMII AN is 442 * only triggered when there is change of speed. If, PHY link 443 * partner`s speed is still same even after PHY TPI is down and up 444 * again, SGMII AN is not triggered and hence no new in-band message 445 * from GPY to MAC side SGMII. 446 * This could cause an issue during power up, when PHY is up prior to 447 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII 448 * wouldn`t receive new in-band message from GPY with correct link 449 * status, speed and duplex info. 450 * 451 * 1) If PHY is already up and TPI link status is still down (such as 452 * hard reboot), TPI link status is polled for 4 seconds before 453 * retriggerring SGMII AN. 454 * 2) If PHY is already up and TPI link status is also up (such as soft 455 * reboot), polling of TPI link status is not needed and SGMII AN is 456 * immediately retriggered. 457 * 3) Other conditions such as PHY is down, speed change etc, skip 458 * retriggering SGMII AN. Note: in case of speed change, GPY FW will 459 * initiate SGMII AN. 460 */ 461 462 if (phydev->state != PHY_UP) 463 return 0; 464 465 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS, 466 20000, 4000000, false); 467 if (ret == -ETIMEDOUT) 468 return 0; 469 else if (ret < 0) 470 return ret; 471 472 /* Trigger SGMII AN. */ 473 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 474 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); 475 } 476 477 static int gpy_update_mdix(struct phy_device *phydev) 478 { 479 int ret; 480 481 ret = phy_read(phydev, PHY_CTL1); 482 if (ret < 0) 483 return ret; 484 485 if (ret & PHY_CTL1_AMDIX) 486 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 487 else 488 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) 489 phydev->mdix_ctrl = ETH_TP_MDI_X; 490 else 491 phydev->mdix_ctrl = ETH_TP_MDI; 492 493 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); 494 if (ret < 0) 495 return ret; 496 497 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) 498 phydev->mdix = ETH_TP_MDI_X; 499 else 500 phydev->mdix = ETH_TP_MDI; 501 502 return 0; 503 } 504 505 static int gpy_update_interface(struct phy_device *phydev) 506 { 507 int ret; 508 509 /* Interface mode is fixed for USXGMII and integrated PHY */ 510 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 511 phydev->interface == PHY_INTERFACE_MODE_INTERNAL) 512 return -EINVAL; 513 514 /* Automatically switch SERDES interface between SGMII and 2500-BaseX 515 * according to speed. Disable ANEG in 2500-BaseX mode. 516 */ 517 switch (phydev->speed) { 518 case SPEED_2500: 519 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 520 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 521 VSPEC1_SGMII_CTRL_ANEN, 0); 522 if (ret < 0) { 523 phydev_err(phydev, 524 "Error: Disable of SGMII ANEG failed: %d\n", 525 ret); 526 return ret; 527 } 528 break; 529 case SPEED_1000: 530 case SPEED_100: 531 case SPEED_10: 532 phydev->interface = PHY_INTERFACE_MODE_SGMII; 533 if (gpy_sgmii_aneg_en(phydev)) 534 break; 535 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed 536 * if ANEG is disabled (in 2500-BaseX mode). 537 */ 538 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, 539 VSPEC1_SGMII_ANEN_ANRS, 540 VSPEC1_SGMII_ANEN_ANRS); 541 if (ret < 0) { 542 phydev_err(phydev, 543 "Error: Enable of SGMII ANEG failed: %d\n", 544 ret); 545 return ret; 546 } 547 break; 548 } 549 550 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { 551 ret = genphy_read_master_slave(phydev); 552 if (ret < 0) 553 return ret; 554 } 555 556 return gpy_update_mdix(phydev); 557 } 558 559 static int gpy_read_status(struct phy_device *phydev) 560 { 561 int ret; 562 563 ret = genphy_update_link(phydev); 564 if (ret) 565 return ret; 566 567 phydev->speed = SPEED_UNKNOWN; 568 phydev->duplex = DUPLEX_UNKNOWN; 569 phydev->pause = 0; 570 phydev->asym_pause = 0; 571 572 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { 573 ret = genphy_c45_read_lpa(phydev); 574 if (ret < 0) 575 return ret; 576 577 /* Read the link partner's 1G advertisement */ 578 ret = phy_read(phydev, MII_STAT1000); 579 if (ret < 0) 580 return ret; 581 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); 582 } else if (phydev->autoneg == AUTONEG_DISABLE) { 583 linkmode_zero(phydev->lp_advertising); 584 } 585 586 ret = phy_read(phydev, PHY_MIISTAT); 587 if (ret < 0) 588 return ret; 589 590 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0; 591 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF; 592 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) { 593 case PHY_MIISTAT_SPD_10: 594 phydev->speed = SPEED_10; 595 break; 596 case PHY_MIISTAT_SPD_100: 597 phydev->speed = SPEED_100; 598 break; 599 case PHY_MIISTAT_SPD_1000: 600 phydev->speed = SPEED_1000; 601 break; 602 case PHY_MIISTAT_SPD_2500: 603 phydev->speed = SPEED_2500; 604 break; 605 } 606 607 if (phydev->link) { 608 ret = gpy_update_interface(phydev); 609 if (ret < 0) 610 return ret; 611 } 612 613 return 0; 614 } 615 616 static int gpy_config_intr(struct phy_device *phydev) 617 { 618 u16 mask = 0; 619 620 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 621 mask = PHY_IMASK_MASK; 622 623 return phy_write(phydev, PHY_IMASK, mask); 624 } 625 626 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev) 627 { 628 int reg; 629 630 reg = phy_read(phydev, PHY_ISTAT); 631 if (reg < 0) { 632 phy_error(phydev); 633 return IRQ_NONE; 634 } 635 636 if (!(reg & PHY_IMASK_MASK)) 637 return IRQ_NONE; 638 639 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT 640 * is read. To avoid interrupt storms, delay the interrupt handling as 641 * long as the PHY drives the interrupt line. An internal bus read will 642 * stall as long as the interrupt line is asserted, thus just read a 643 * random register here. 644 * Because we cannot access the internal bus at all while the interrupt 645 * is driven by the PHY, there is no way to make the interrupt line 646 * unstuck (e.g. by changing the pinmux to GPIO input) during that time 647 * frame. Therefore, polling is the best we can do and won't do any more 648 * harm. 649 * It was observed that this bug happens on link state and link speed 650 * changes on a GPY215B and GYP215C independent of the firmware version 651 * (which doesn't mean that this list is exhaustive). 652 */ 653 if (gpy_has_broken_mdint(phydev) && 654 (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC))) { 655 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT); 656 if (reg < 0) { 657 phy_error(phydev); 658 return IRQ_NONE; 659 } 660 } 661 662 phy_trigger_machine(phydev); 663 664 return IRQ_HANDLED; 665 } 666 667 static int gpy_set_wol(struct phy_device *phydev, 668 struct ethtool_wolinfo *wol) 669 { 670 struct net_device *attach_dev = phydev->attached_dev; 671 int ret; 672 673 if (wol->wolopts & WAKE_MAGIC) { 674 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5 675 * VPSPEC2_WOL_AD45 = Byte0:Byte1 676 * VPSPEC2_WOL_AD23 = Byte2:Byte3 677 * VPSPEC2_WOL_AD01 = Byte4:Byte5 678 */ 679 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 680 VPSPEC2_WOL_AD45, 681 ((attach_dev->dev_addr[0] << 8) | 682 attach_dev->dev_addr[1])); 683 if (ret < 0) 684 return ret; 685 686 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 687 VPSPEC2_WOL_AD23, 688 ((attach_dev->dev_addr[2] << 8) | 689 attach_dev->dev_addr[3])); 690 if (ret < 0) 691 return ret; 692 693 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 694 VPSPEC2_WOL_AD01, 695 ((attach_dev->dev_addr[4] << 8) | 696 attach_dev->dev_addr[5])); 697 if (ret < 0) 698 return ret; 699 700 /* Enable the WOL interrupt */ 701 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL); 702 if (ret < 0) 703 return ret; 704 705 /* Enable magic packet matching */ 706 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 707 VPSPEC2_WOL_CTL, 708 WOL_EN); 709 if (ret < 0) 710 return ret; 711 712 /* Clear the interrupt status register. 713 * Only WoL is enabled so clear all. 714 */ 715 ret = phy_read(phydev, PHY_ISTAT); 716 if (ret < 0) 717 return ret; 718 } else { 719 /* Disable magic packet matching */ 720 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 721 VPSPEC2_WOL_CTL, 722 WOL_EN); 723 if (ret < 0) 724 return ret; 725 } 726 727 if (wol->wolopts & WAKE_PHY) { 728 /* Enable the link state change interrupt */ 729 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 730 if (ret < 0) 731 return ret; 732 733 /* Clear the interrupt status register */ 734 ret = phy_read(phydev, PHY_ISTAT); 735 if (ret < 0) 736 return ret; 737 738 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC)) 739 phy_trigger_machine(phydev); 740 741 return 0; 742 } 743 744 /* Disable the link state change interrupt */ 745 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); 746 } 747 748 static void gpy_get_wol(struct phy_device *phydev, 749 struct ethtool_wolinfo *wol) 750 { 751 int ret; 752 753 wol->supported = WAKE_MAGIC | WAKE_PHY; 754 wol->wolopts = 0; 755 756 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL); 757 if (ret & WOL_EN) 758 wol->wolopts |= WAKE_MAGIC; 759 760 ret = phy_read(phydev, PHY_IMASK); 761 if (ret & PHY_IMASK_LSTC) 762 wol->wolopts |= WAKE_PHY; 763 } 764 765 static int gpy_loopback(struct phy_device *phydev, bool enable) 766 { 767 int ret; 768 769 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 770 enable ? BMCR_LOOPBACK : 0); 771 if (!ret) { 772 /* It takes some time for PHY device to switch 773 * into/out-of loopback mode. 774 */ 775 msleep(100); 776 } 777 778 return ret; 779 } 780 781 static int gpy115_loopback(struct phy_device *phydev, bool enable) 782 { 783 struct gpy_priv *priv = phydev->priv; 784 785 if (enable) 786 return gpy_loopback(phydev, enable); 787 788 if (priv->fw_minor > 0x76) 789 return gpy_loopback(phydev, 0); 790 791 return genphy_soft_reset(phydev); 792 } 793 794 static struct phy_driver gpy_drivers[] = { 795 { 796 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), 797 .name = "Maxlinear Ethernet GPY2xx", 798 .get_features = genphy_c45_pma_read_abilities, 799 .config_init = gpy_config_init, 800 .probe = gpy_probe, 801 .suspend = genphy_suspend, 802 .resume = genphy_resume, 803 .config_aneg = gpy_config_aneg, 804 .aneg_done = genphy_c45_aneg_done, 805 .read_status = gpy_read_status, 806 .config_intr = gpy_config_intr, 807 .handle_interrupt = gpy_handle_interrupt, 808 .set_wol = gpy_set_wol, 809 .get_wol = gpy_get_wol, 810 .set_loopback = gpy_loopback, 811 }, 812 { 813 .phy_id = PHY_ID_GPY115B, 814 .phy_id_mask = PHY_ID_GPYx15B_MASK, 815 .name = "Maxlinear Ethernet GPY115B", 816 .get_features = genphy_c45_pma_read_abilities, 817 .config_init = gpy_config_init, 818 .probe = gpy_probe, 819 .suspend = genphy_suspend, 820 .resume = genphy_resume, 821 .config_aneg = gpy_config_aneg, 822 .aneg_done = genphy_c45_aneg_done, 823 .read_status = gpy_read_status, 824 .config_intr = gpy_config_intr, 825 .handle_interrupt = gpy_handle_interrupt, 826 .set_wol = gpy_set_wol, 827 .get_wol = gpy_get_wol, 828 .set_loopback = gpy115_loopback, 829 }, 830 { 831 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), 832 .name = "Maxlinear Ethernet GPY115C", 833 .get_features = genphy_c45_pma_read_abilities, 834 .config_init = gpy_config_init, 835 .probe = gpy_probe, 836 .suspend = genphy_suspend, 837 .resume = genphy_resume, 838 .config_aneg = gpy_config_aneg, 839 .aneg_done = genphy_c45_aneg_done, 840 .read_status = gpy_read_status, 841 .config_intr = gpy_config_intr, 842 .handle_interrupt = gpy_handle_interrupt, 843 .set_wol = gpy_set_wol, 844 .get_wol = gpy_get_wol, 845 .set_loopback = gpy115_loopback, 846 }, 847 { 848 .phy_id = PHY_ID_GPY211B, 849 .phy_id_mask = PHY_ID_GPY21xB_MASK, 850 .name = "Maxlinear Ethernet GPY211B", 851 .get_features = genphy_c45_pma_read_abilities, 852 .config_init = gpy_config_init, 853 .probe = gpy_probe, 854 .suspend = genphy_suspend, 855 .resume = genphy_resume, 856 .config_aneg = gpy_config_aneg, 857 .aneg_done = genphy_c45_aneg_done, 858 .read_status = gpy_read_status, 859 .config_intr = gpy_config_intr, 860 .handle_interrupt = gpy_handle_interrupt, 861 .set_wol = gpy_set_wol, 862 .get_wol = gpy_get_wol, 863 .set_loopback = gpy_loopback, 864 }, 865 { 866 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), 867 .name = "Maxlinear Ethernet GPY211C", 868 .get_features = genphy_c45_pma_read_abilities, 869 .config_init = gpy_config_init, 870 .probe = gpy_probe, 871 .suspend = genphy_suspend, 872 .resume = genphy_resume, 873 .config_aneg = gpy_config_aneg, 874 .aneg_done = genphy_c45_aneg_done, 875 .read_status = gpy_read_status, 876 .config_intr = gpy_config_intr, 877 .handle_interrupt = gpy_handle_interrupt, 878 .set_wol = gpy_set_wol, 879 .get_wol = gpy_get_wol, 880 .set_loopback = gpy_loopback, 881 }, 882 { 883 .phy_id = PHY_ID_GPY212B, 884 .phy_id_mask = PHY_ID_GPY21xB_MASK, 885 .name = "Maxlinear Ethernet GPY212B", 886 .get_features = genphy_c45_pma_read_abilities, 887 .config_init = gpy_config_init, 888 .probe = gpy_probe, 889 .suspend = genphy_suspend, 890 .resume = genphy_resume, 891 .config_aneg = gpy_config_aneg, 892 .aneg_done = genphy_c45_aneg_done, 893 .read_status = gpy_read_status, 894 .config_intr = gpy_config_intr, 895 .handle_interrupt = gpy_handle_interrupt, 896 .set_wol = gpy_set_wol, 897 .get_wol = gpy_get_wol, 898 .set_loopback = gpy_loopback, 899 }, 900 { 901 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), 902 .name = "Maxlinear Ethernet GPY212C", 903 .get_features = genphy_c45_pma_read_abilities, 904 .config_init = gpy_config_init, 905 .probe = gpy_probe, 906 .suspend = genphy_suspend, 907 .resume = genphy_resume, 908 .config_aneg = gpy_config_aneg, 909 .aneg_done = genphy_c45_aneg_done, 910 .read_status = gpy_read_status, 911 .config_intr = gpy_config_intr, 912 .handle_interrupt = gpy_handle_interrupt, 913 .set_wol = gpy_set_wol, 914 .get_wol = gpy_get_wol, 915 .set_loopback = gpy_loopback, 916 }, 917 { 918 .phy_id = PHY_ID_GPY215B, 919 .phy_id_mask = PHY_ID_GPYx15B_MASK, 920 .name = "Maxlinear Ethernet GPY215B", 921 .get_features = genphy_c45_pma_read_abilities, 922 .config_init = gpy_config_init, 923 .probe = gpy_probe, 924 .suspend = genphy_suspend, 925 .resume = genphy_resume, 926 .config_aneg = gpy_config_aneg, 927 .aneg_done = genphy_c45_aneg_done, 928 .read_status = gpy_read_status, 929 .config_intr = gpy_config_intr, 930 .handle_interrupt = gpy_handle_interrupt, 931 .set_wol = gpy_set_wol, 932 .get_wol = gpy_get_wol, 933 .set_loopback = gpy_loopback, 934 }, 935 { 936 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), 937 .name = "Maxlinear Ethernet GPY215C", 938 .get_features = genphy_c45_pma_read_abilities, 939 .config_init = gpy_config_init, 940 .probe = gpy_probe, 941 .suspend = genphy_suspend, 942 .resume = genphy_resume, 943 .config_aneg = gpy_config_aneg, 944 .aneg_done = genphy_c45_aneg_done, 945 .read_status = gpy_read_status, 946 .config_intr = gpy_config_intr, 947 .handle_interrupt = gpy_handle_interrupt, 948 .set_wol = gpy_set_wol, 949 .get_wol = gpy_get_wol, 950 .set_loopback = gpy_loopback, 951 }, 952 { 953 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), 954 .name = "Maxlinear Ethernet GPY241B", 955 .get_features = genphy_c45_pma_read_abilities, 956 .config_init = gpy_config_init, 957 .probe = gpy_probe, 958 .suspend = genphy_suspend, 959 .resume = genphy_resume, 960 .config_aneg = gpy_config_aneg, 961 .aneg_done = genphy_c45_aneg_done, 962 .read_status = gpy_read_status, 963 .config_intr = gpy_config_intr, 964 .handle_interrupt = gpy_handle_interrupt, 965 .set_wol = gpy_set_wol, 966 .get_wol = gpy_get_wol, 967 .set_loopback = gpy_loopback, 968 }, 969 { 970 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), 971 .name = "Maxlinear Ethernet GPY241BM", 972 .get_features = genphy_c45_pma_read_abilities, 973 .config_init = gpy_config_init, 974 .probe = gpy_probe, 975 .suspend = genphy_suspend, 976 .resume = genphy_resume, 977 .config_aneg = gpy_config_aneg, 978 .aneg_done = genphy_c45_aneg_done, 979 .read_status = gpy_read_status, 980 .config_intr = gpy_config_intr, 981 .handle_interrupt = gpy_handle_interrupt, 982 .set_wol = gpy_set_wol, 983 .get_wol = gpy_get_wol, 984 .set_loopback = gpy_loopback, 985 }, 986 { 987 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), 988 .name = "Maxlinear Ethernet GPY245B", 989 .get_features = genphy_c45_pma_read_abilities, 990 .config_init = gpy_config_init, 991 .probe = gpy_probe, 992 .suspend = genphy_suspend, 993 .resume = genphy_resume, 994 .config_aneg = gpy_config_aneg, 995 .aneg_done = genphy_c45_aneg_done, 996 .read_status = gpy_read_status, 997 .config_intr = gpy_config_intr, 998 .handle_interrupt = gpy_handle_interrupt, 999 .set_wol = gpy_set_wol, 1000 .get_wol = gpy_get_wol, 1001 .set_loopback = gpy_loopback, 1002 }, 1003 }; 1004 module_phy_driver(gpy_drivers); 1005 1006 static struct mdio_device_id __maybe_unused gpy_tbl[] = { 1007 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)}, 1008 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK}, 1009 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)}, 1010 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK}, 1011 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)}, 1012 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK}, 1013 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)}, 1014 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK}, 1015 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)}, 1016 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)}, 1017 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)}, 1018 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)}, 1019 { } 1020 }; 1021 MODULE_DEVICE_TABLE(mdio, gpy_tbl); 1022 1023 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver"); 1024 MODULE_AUTHOR("Xu Liang"); 1025 MODULE_LICENSE("GPL"); 1026