1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Analog Devices ADV748X HDMI receiver and Component Processor (CP) 4 * 5 * Copyright (C) 2017 Renesas Electronics Corp. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/mutex.h> 10 11 #include <media/v4l2-ctrls.h> 12 #include <media/v4l2-device.h> 13 #include <media/v4l2-dv-timings.h> 14 #include <media/v4l2-ioctl.h> 15 16 #include <uapi/linux/v4l2-dv-timings.h> 17 18 #include "adv748x.h" 19 20 /* ----------------------------------------------------------------------------- 21 * HDMI and CP 22 */ 23 24 #define ADV748X_HDMI_MIN_WIDTH 640 25 #define ADV748X_HDMI_MAX_WIDTH 1920 26 #define ADV748X_HDMI_MIN_HEIGHT 480 27 #define ADV748X_HDMI_MAX_HEIGHT 1200 28 29 /* V4L2_DV_BT_CEA_720X480I59_94 - 0.5 MHz */ 30 #define ADV748X_HDMI_MIN_PIXELCLOCK 13000000 31 /* V4L2_DV_BT_DMT_1600X1200P60 */ 32 #define ADV748X_HDMI_MAX_PIXELCLOCK 162000000 33 34 static const struct v4l2_dv_timings_cap adv748x_hdmi_timings_cap = { 35 .type = V4L2_DV_BT_656_1120, 36 /* keep this initialization for compatibility with GCC < 4.4.6 */ 37 .reserved = { 0 }, 38 39 V4L2_INIT_BT_TIMINGS(ADV748X_HDMI_MIN_WIDTH, ADV748X_HDMI_MAX_WIDTH, 40 ADV748X_HDMI_MIN_HEIGHT, ADV748X_HDMI_MAX_HEIGHT, 41 ADV748X_HDMI_MIN_PIXELCLOCK, 42 ADV748X_HDMI_MAX_PIXELCLOCK, 43 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT, 44 V4L2_DV_BT_CAP_PROGRESSIVE) 45 }; 46 47 struct adv748x_hdmi_video_standards { 48 struct v4l2_dv_timings timings; 49 u8 vid_std; 50 u8 v_freq; 51 }; 52 53 static const struct adv748x_hdmi_video_standards 54 adv748x_hdmi_video_standards[] = { 55 { V4L2_DV_BT_CEA_720X480P59_94, 0x4a, 0x00 }, 56 { V4L2_DV_BT_CEA_720X576P50, 0x4b, 0x00 }, 57 { V4L2_DV_BT_CEA_1280X720P60, 0x53, 0x00 }, 58 { V4L2_DV_BT_CEA_1280X720P50, 0x53, 0x01 }, 59 { V4L2_DV_BT_CEA_1280X720P30, 0x53, 0x02 }, 60 { V4L2_DV_BT_CEA_1280X720P25, 0x53, 0x03 }, 61 { V4L2_DV_BT_CEA_1280X720P24, 0x53, 0x04 }, 62 { V4L2_DV_BT_CEA_1920X1080P60, 0x5e, 0x00 }, 63 { V4L2_DV_BT_CEA_1920X1080P50, 0x5e, 0x01 }, 64 { V4L2_DV_BT_CEA_1920X1080P30, 0x5e, 0x02 }, 65 { V4L2_DV_BT_CEA_1920X1080P25, 0x5e, 0x03 }, 66 { V4L2_DV_BT_CEA_1920X1080P24, 0x5e, 0x04 }, 67 /* SVGA */ 68 { V4L2_DV_BT_DMT_800X600P56, 0x80, 0x00 }, 69 { V4L2_DV_BT_DMT_800X600P60, 0x81, 0x00 }, 70 { V4L2_DV_BT_DMT_800X600P72, 0x82, 0x00 }, 71 { V4L2_DV_BT_DMT_800X600P75, 0x83, 0x00 }, 72 { V4L2_DV_BT_DMT_800X600P85, 0x84, 0x00 }, 73 /* SXGA */ 74 { V4L2_DV_BT_DMT_1280X1024P60, 0x85, 0x00 }, 75 { V4L2_DV_BT_DMT_1280X1024P75, 0x86, 0x00 }, 76 /* VGA */ 77 { V4L2_DV_BT_DMT_640X480P60, 0x88, 0x00 }, 78 { V4L2_DV_BT_DMT_640X480P72, 0x89, 0x00 }, 79 { V4L2_DV_BT_DMT_640X480P75, 0x8a, 0x00 }, 80 { V4L2_DV_BT_DMT_640X480P85, 0x8b, 0x00 }, 81 /* XGA */ 82 { V4L2_DV_BT_DMT_1024X768P60, 0x8c, 0x00 }, 83 { V4L2_DV_BT_DMT_1024X768P70, 0x8d, 0x00 }, 84 { V4L2_DV_BT_DMT_1024X768P75, 0x8e, 0x00 }, 85 { V4L2_DV_BT_DMT_1024X768P85, 0x8f, 0x00 }, 86 /* UXGA */ 87 { V4L2_DV_BT_DMT_1600X1200P60, 0x96, 0x00 }, 88 }; 89 90 static void adv748x_hdmi_fill_format(struct adv748x_hdmi *hdmi, 91 struct v4l2_mbus_framefmt *fmt) 92 { 93 memset(fmt, 0, sizeof(*fmt)); 94 95 fmt->code = MEDIA_BUS_FMT_RGB888_1X24; 96 fmt->field = hdmi->timings.bt.interlaced ? 97 V4L2_FIELD_ALTERNATE : V4L2_FIELD_NONE; 98 99 /* TODO: The colorspace depends on the AVI InfoFrame contents */ 100 fmt->colorspace = V4L2_COLORSPACE_SRGB; 101 102 fmt->width = hdmi->timings.bt.width; 103 fmt->height = hdmi->timings.bt.height; 104 105 if (fmt->field == V4L2_FIELD_ALTERNATE) 106 fmt->height /= 2; 107 } 108 109 static void adv748x_fill_optional_dv_timings(struct v4l2_dv_timings *timings) 110 { 111 v4l2_find_dv_timings_cap(timings, &adv748x_hdmi_timings_cap, 112 250000, NULL, NULL); 113 } 114 115 static bool adv748x_hdmi_has_signal(struct adv748x_state *state) 116 { 117 int val; 118 119 /* Check that VERT_FILTER and DE_REGEN is locked */ 120 val = hdmi_read(state, ADV748X_HDMI_LW1); 121 return (val & ADV748X_HDMI_LW1_VERT_FILTER) && 122 (val & ADV748X_HDMI_LW1_DE_REGEN); 123 } 124 125 static int adv748x_hdmi_read_pixelclock(struct adv748x_state *state) 126 { 127 int a, b; 128 129 a = hdmi_read(state, ADV748X_HDMI_TMDS_1); 130 b = hdmi_read(state, ADV748X_HDMI_TMDS_2); 131 if (a < 0 || b < 0) 132 return -ENODATA; 133 134 /* 135 * The high 9 bits store TMDS frequency measurement in MHz 136 * The low 7 bits of TMDS_2 store the 7-bit TMDS fractional frequency 137 * measurement in 1/128 MHz 138 */ 139 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 140 } 141 142 /* 143 * adv748x_hdmi_set_de_timings: Adjust horizontal picture offset through DE 144 * 145 * HDMI CP uses a Data Enable synchronisation timing reference 146 * 147 * Vary the leading and trailing edge position of the DE signal output by the CP 148 * core. Values are stored as signed-twos-complement in one-pixel-clock units 149 * 150 * The start and end are shifted equally by the 10-bit shift value. 151 */ 152 static void adv748x_hdmi_set_de_timings(struct adv748x_state *state, int shift) 153 { 154 u8 high, low; 155 156 /* POS_HIGH stores bits 8 and 9 of both the start and end */ 157 high = ADV748X_CP_DE_POS_HIGH_SET; 158 high |= (shift & 0x300) >> 8; 159 low = shift & 0xff; 160 161 /* The sequence of the writes is important and must be followed */ 162 cp_write(state, ADV748X_CP_DE_POS_HIGH, high); 163 cp_write(state, ADV748X_CP_DE_POS_END_LOW, low); 164 165 high |= (shift & 0x300) >> 6; 166 167 cp_write(state, ADV748X_CP_DE_POS_HIGH, high); 168 cp_write(state, ADV748X_CP_DE_POS_START_LOW, low); 169 } 170 171 static int adv748x_hdmi_set_video_timings(struct adv748x_state *state, 172 const struct v4l2_dv_timings *timings) 173 { 174 const struct adv748x_hdmi_video_standards *stds = 175 adv748x_hdmi_video_standards; 176 unsigned int i; 177 178 for (i = 0; i < ARRAY_SIZE(adv748x_hdmi_video_standards); i++) { 179 if (!v4l2_match_dv_timings(timings, &stds[i].timings, 250000, 180 false)) 181 continue; 182 } 183 184 if (i >= ARRAY_SIZE(adv748x_hdmi_video_standards)) 185 return -EINVAL; 186 187 /* 188 * When setting cp_vid_std to either 720p, 1080i, or 1080p, the video 189 * will get shifted horizontally to the left in active video mode. 190 * The de_h_start and de_h_end controls are used to centre the picture 191 * correctly 192 */ 193 switch (stds[i].vid_std) { 194 case 0x53: /* 720p */ 195 adv748x_hdmi_set_de_timings(state, -40); 196 break; 197 case 0x54: /* 1080i */ 198 case 0x5e: /* 1080p */ 199 adv748x_hdmi_set_de_timings(state, -44); 200 break; 201 default: 202 adv748x_hdmi_set_de_timings(state, 0); 203 break; 204 } 205 206 io_write(state, ADV748X_IO_VID_STD, stds[i].vid_std); 207 io_clrset(state, ADV748X_IO_DATAPATH, ADV748X_IO_DATAPATH_VFREQ_M, 208 stds[i].v_freq << ADV748X_IO_DATAPATH_VFREQ_SHIFT); 209 210 return 0; 211 } 212 213 /* ----------------------------------------------------------------------------- 214 * v4l2_subdev_video_ops 215 */ 216 217 static int adv748x_hdmi_s_dv_timings(struct v4l2_subdev *sd, 218 struct v4l2_dv_timings *timings) 219 { 220 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 221 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 222 int ret; 223 224 if (!timings) 225 return -EINVAL; 226 227 if (v4l2_match_dv_timings(&hdmi->timings, timings, 0, false)) 228 return 0; 229 230 if (!v4l2_valid_dv_timings(timings, &adv748x_hdmi_timings_cap, 231 NULL, NULL)) 232 return -ERANGE; 233 234 adv748x_fill_optional_dv_timings(timings); 235 236 mutex_lock(&state->mutex); 237 238 ret = adv748x_hdmi_set_video_timings(state, timings); 239 if (ret) 240 goto error; 241 242 hdmi->timings = *timings; 243 244 cp_clrset(state, ADV748X_CP_VID_ADJ_2, ADV748X_CP_VID_ADJ_2_INTERLACED, 245 timings->bt.interlaced ? 246 ADV748X_CP_VID_ADJ_2_INTERLACED : 0); 247 248 mutex_unlock(&state->mutex); 249 250 return 0; 251 252 error: 253 mutex_unlock(&state->mutex); 254 return ret; 255 } 256 257 static int adv748x_hdmi_g_dv_timings(struct v4l2_subdev *sd, 258 struct v4l2_dv_timings *timings) 259 { 260 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 261 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 262 263 mutex_lock(&state->mutex); 264 265 *timings = hdmi->timings; 266 267 mutex_unlock(&state->mutex); 268 269 return 0; 270 } 271 272 static int adv748x_hdmi_query_dv_timings(struct v4l2_subdev *sd, 273 struct v4l2_dv_timings *timings) 274 { 275 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 276 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 277 struct v4l2_bt_timings *bt = &timings->bt; 278 int pixelclock; 279 int polarity; 280 281 if (!timings) 282 return -EINVAL; 283 284 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 285 286 if (!adv748x_hdmi_has_signal(state)) 287 return -ENOLINK; 288 289 pixelclock = adv748x_hdmi_read_pixelclock(state); 290 if (pixelclock < 0) 291 return -ENODATA; 292 293 timings->type = V4L2_DV_BT_656_1120; 294 295 bt->pixelclock = pixelclock; 296 bt->interlaced = hdmi_read(state, ADV748X_HDMI_F1H1) & 297 ADV748X_HDMI_F1H1_INTERLACED ? 298 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 299 bt->width = hdmi_read16(state, ADV748X_HDMI_LW1, 300 ADV748X_HDMI_LW1_WIDTH_MASK); 301 bt->height = hdmi_read16(state, ADV748X_HDMI_F0H1, 302 ADV748X_HDMI_F0H1_HEIGHT_MASK); 303 bt->hfrontporch = hdmi_read16(state, ADV748X_HDMI_HFRONT_PORCH, 304 ADV748X_HDMI_HFRONT_PORCH_MASK); 305 bt->hsync = hdmi_read16(state, ADV748X_HDMI_HSYNC_WIDTH, 306 ADV748X_HDMI_HSYNC_WIDTH_MASK); 307 bt->hbackporch = hdmi_read16(state, ADV748X_HDMI_HBACK_PORCH, 308 ADV748X_HDMI_HBACK_PORCH_MASK); 309 bt->vfrontporch = hdmi_read16(state, ADV748X_HDMI_VFRONT_PORCH, 310 ADV748X_HDMI_VFRONT_PORCH_MASK) / 2; 311 bt->vsync = hdmi_read16(state, ADV748X_HDMI_VSYNC_WIDTH, 312 ADV748X_HDMI_VSYNC_WIDTH_MASK) / 2; 313 bt->vbackporch = hdmi_read16(state, ADV748X_HDMI_VBACK_PORCH, 314 ADV748X_HDMI_VBACK_PORCH_MASK) / 2; 315 316 polarity = hdmi_read(state, 0x05); 317 bt->polarities = (polarity & BIT(4) ? V4L2_DV_VSYNC_POS_POL : 0) | 318 (polarity & BIT(5) ? V4L2_DV_HSYNC_POS_POL : 0); 319 320 if (bt->interlaced == V4L2_DV_INTERLACED) { 321 bt->height += hdmi_read16(state, 0x0b, 0x1fff); 322 bt->il_vfrontporch = hdmi_read16(state, 0x2c, 0x3fff) / 2; 323 bt->il_vsync = hdmi_read16(state, 0x30, 0x3fff) / 2; 324 bt->il_vbackporch = hdmi_read16(state, 0x34, 0x3fff) / 2; 325 } 326 327 adv748x_fill_optional_dv_timings(timings); 328 329 /* 330 * No interrupt handling is implemented yet. 331 * There should be an IRQ when a cable is plugged and the new timings 332 * should be figured out and stored to state. 333 */ 334 hdmi->timings = *timings; 335 336 return 0; 337 } 338 339 static int adv748x_hdmi_g_input_status(struct v4l2_subdev *sd, u32 *status) 340 { 341 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 342 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 343 344 mutex_lock(&state->mutex); 345 346 *status = adv748x_hdmi_has_signal(state) ? 0 : V4L2_IN_ST_NO_SIGNAL; 347 348 mutex_unlock(&state->mutex); 349 350 return 0; 351 } 352 353 static int adv748x_hdmi_s_stream(struct v4l2_subdev *sd, int enable) 354 { 355 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 356 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 357 int ret; 358 359 mutex_lock(&state->mutex); 360 361 ret = adv748x_tx_power(hdmi->tx, enable); 362 if (ret) 363 goto done; 364 365 if (adv748x_hdmi_has_signal(state)) 366 adv_dbg(state, "Detected HDMI signal\n"); 367 else 368 adv_dbg(state, "Couldn't detect HDMI video signal\n"); 369 370 done: 371 mutex_unlock(&state->mutex); 372 return ret; 373 } 374 375 static int adv748x_hdmi_g_pixelaspect(struct v4l2_subdev *sd, 376 struct v4l2_fract *aspect) 377 { 378 aspect->numerator = 1; 379 aspect->denominator = 1; 380 381 return 0; 382 } 383 384 static const struct v4l2_subdev_video_ops adv748x_video_ops_hdmi = { 385 .s_dv_timings = adv748x_hdmi_s_dv_timings, 386 .g_dv_timings = adv748x_hdmi_g_dv_timings, 387 .query_dv_timings = adv748x_hdmi_query_dv_timings, 388 .g_input_status = adv748x_hdmi_g_input_status, 389 .s_stream = adv748x_hdmi_s_stream, 390 .g_pixelaspect = adv748x_hdmi_g_pixelaspect, 391 }; 392 393 /* ----------------------------------------------------------------------------- 394 * v4l2_subdev_pad_ops 395 */ 396 397 static int adv748x_hdmi_propagate_pixelrate(struct adv748x_hdmi *hdmi) 398 { 399 struct v4l2_subdev *tx; 400 struct v4l2_dv_timings timings; 401 402 tx = adv748x_get_remote_sd(&hdmi->pads[ADV748X_HDMI_SOURCE]); 403 if (!tx) 404 return -ENOLINK; 405 406 adv748x_hdmi_query_dv_timings(&hdmi->sd, &timings); 407 408 return adv748x_csi2_set_pixelrate(tx, timings.bt.pixelclock); 409 } 410 411 static int adv748x_hdmi_enum_mbus_code(struct v4l2_subdev *sd, 412 struct v4l2_subdev_state *sd_state, 413 struct v4l2_subdev_mbus_code_enum *code) 414 { 415 if (code->index != 0) 416 return -EINVAL; 417 418 code->code = MEDIA_BUS_FMT_RGB888_1X24; 419 420 return 0; 421 } 422 423 static int adv748x_hdmi_get_format(struct v4l2_subdev *sd, 424 struct v4l2_subdev_state *sd_state, 425 struct v4l2_subdev_format *sdformat) 426 { 427 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 428 struct v4l2_mbus_framefmt *mbusformat; 429 430 if (sdformat->pad != ADV748X_HDMI_SOURCE) 431 return -EINVAL; 432 433 if (sdformat->which == V4L2_SUBDEV_FORMAT_TRY) { 434 mbusformat = v4l2_subdev_get_try_format(sd, sd_state, 435 sdformat->pad); 436 sdformat->format = *mbusformat; 437 } else { 438 adv748x_hdmi_fill_format(hdmi, &sdformat->format); 439 adv748x_hdmi_propagate_pixelrate(hdmi); 440 } 441 442 return 0; 443 } 444 445 static int adv748x_hdmi_set_format(struct v4l2_subdev *sd, 446 struct v4l2_subdev_state *sd_state, 447 struct v4l2_subdev_format *sdformat) 448 { 449 struct v4l2_mbus_framefmt *mbusformat; 450 451 if (sdformat->pad != ADV748X_HDMI_SOURCE) 452 return -EINVAL; 453 454 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) 455 return adv748x_hdmi_get_format(sd, sd_state, sdformat); 456 457 mbusformat = v4l2_subdev_get_try_format(sd, sd_state, sdformat->pad); 458 *mbusformat = sdformat->format; 459 460 return 0; 461 } 462 463 static int adv748x_hdmi_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 464 { 465 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 466 467 memset(edid->reserved, 0, sizeof(edid->reserved)); 468 469 if (!hdmi->edid.present) 470 return -ENODATA; 471 472 if (edid->start_block == 0 && edid->blocks == 0) { 473 edid->blocks = hdmi->edid.blocks; 474 return 0; 475 } 476 477 if (edid->start_block >= hdmi->edid.blocks) 478 return -EINVAL; 479 480 if (edid->start_block + edid->blocks > hdmi->edid.blocks) 481 edid->blocks = hdmi->edid.blocks - edid->start_block; 482 483 memcpy(edid->edid, hdmi->edid.edid + edid->start_block * 128, 484 edid->blocks * 128); 485 486 return 0; 487 } 488 489 static inline int adv748x_hdmi_edid_write_block(struct adv748x_hdmi *hdmi, 490 unsigned int total_len, const u8 *val) 491 { 492 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 493 int err = 0; 494 int i = 0; 495 int len = 0; 496 497 adv_dbg(state, "%s: write EDID block (%d byte)\n", 498 __func__, total_len); 499 500 while (!err && i < total_len) { 501 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? 502 I2C_SMBUS_BLOCK_MAX : 503 (total_len - i); 504 505 err = adv748x_write_block(state, ADV748X_PAGE_EDID, 506 i, val + i, len); 507 i += len; 508 } 509 510 return err; 511 } 512 513 static int adv748x_hdmi_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 514 { 515 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); 516 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 517 int err; 518 519 memset(edid->reserved, 0, sizeof(edid->reserved)); 520 521 if (edid->start_block != 0) 522 return -EINVAL; 523 524 if (edid->blocks == 0) { 525 hdmi->edid.blocks = 0; 526 hdmi->edid.present = 0; 527 528 /* Fall back to a 16:9 aspect ratio */ 529 hdmi->aspect_ratio.numerator = 16; 530 hdmi->aspect_ratio.denominator = 9; 531 532 /* Disable the EDID */ 533 repeater_write(state, ADV748X_REPEATER_EDID_SZ, 534 edid->blocks << ADV748X_REPEATER_EDID_SZ_SHIFT); 535 536 repeater_write(state, ADV748X_REPEATER_EDID_CTL, 0); 537 538 return 0; 539 } 540 541 if (edid->blocks > 4) { 542 edid->blocks = 4; 543 return -E2BIG; 544 } 545 546 memcpy(hdmi->edid.edid, edid->edid, 128 * edid->blocks); 547 hdmi->edid.blocks = edid->blocks; 548 hdmi->edid.present = true; 549 550 hdmi->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 551 edid->edid[0x16]); 552 553 err = adv748x_hdmi_edid_write_block(hdmi, 128 * edid->blocks, 554 hdmi->edid.edid); 555 if (err < 0) { 556 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 557 return err; 558 } 559 560 repeater_write(state, ADV748X_REPEATER_EDID_SZ, 561 edid->blocks << ADV748X_REPEATER_EDID_SZ_SHIFT); 562 563 repeater_write(state, ADV748X_REPEATER_EDID_CTL, 564 ADV748X_REPEATER_EDID_CTL_EN); 565 566 return 0; 567 } 568 569 static bool adv748x_hdmi_check_dv_timings(const struct v4l2_dv_timings *timings, 570 void *hdl) 571 { 572 const struct adv748x_hdmi_video_standards *stds = 573 adv748x_hdmi_video_standards; 574 unsigned int i; 575 576 for (i = 0; stds[i].timings.bt.width; i++) 577 if (v4l2_match_dv_timings(timings, &stds[i].timings, 0, false)) 578 return true; 579 580 return false; 581 } 582 583 static int adv748x_hdmi_enum_dv_timings(struct v4l2_subdev *sd, 584 struct v4l2_enum_dv_timings *timings) 585 { 586 return v4l2_enum_dv_timings_cap(timings, &adv748x_hdmi_timings_cap, 587 adv748x_hdmi_check_dv_timings, NULL); 588 } 589 590 static int adv748x_hdmi_dv_timings_cap(struct v4l2_subdev *sd, 591 struct v4l2_dv_timings_cap *cap) 592 { 593 *cap = adv748x_hdmi_timings_cap; 594 return 0; 595 } 596 597 static const struct v4l2_subdev_pad_ops adv748x_pad_ops_hdmi = { 598 .enum_mbus_code = adv748x_hdmi_enum_mbus_code, 599 .set_fmt = adv748x_hdmi_set_format, 600 .get_fmt = adv748x_hdmi_get_format, 601 .get_edid = adv748x_hdmi_get_edid, 602 .set_edid = adv748x_hdmi_set_edid, 603 .dv_timings_cap = adv748x_hdmi_dv_timings_cap, 604 .enum_dv_timings = adv748x_hdmi_enum_dv_timings, 605 }; 606 607 /* ----------------------------------------------------------------------------- 608 * v4l2_subdev_ops 609 */ 610 611 static const struct v4l2_subdev_ops adv748x_ops_hdmi = { 612 .video = &adv748x_video_ops_hdmi, 613 .pad = &adv748x_pad_ops_hdmi, 614 }; 615 616 /* ----------------------------------------------------------------------------- 617 * Controls 618 */ 619 620 static const char * const hdmi_ctrl_patgen_menu[] = { 621 "Disabled", 622 "Solid Color", 623 "Color Bars", 624 "Ramp Grey", 625 "Ramp Blue", 626 "Ramp Red", 627 "Checkered" 628 }; 629 630 static int adv748x_hdmi_s_ctrl(struct v4l2_ctrl *ctrl) 631 { 632 struct adv748x_hdmi *hdmi = adv748x_ctrl_to_hdmi(ctrl); 633 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 634 int ret; 635 u8 pattern; 636 637 /* Enable video adjustment first */ 638 ret = cp_clrset(state, ADV748X_CP_VID_ADJ, 639 ADV748X_CP_VID_ADJ_ENABLE, 640 ADV748X_CP_VID_ADJ_ENABLE); 641 if (ret < 0) 642 return ret; 643 644 switch (ctrl->id) { 645 case V4L2_CID_BRIGHTNESS: 646 ret = cp_write(state, ADV748X_CP_BRI, ctrl->val); 647 break; 648 case V4L2_CID_HUE: 649 ret = cp_write(state, ADV748X_CP_HUE, ctrl->val); 650 break; 651 case V4L2_CID_CONTRAST: 652 ret = cp_write(state, ADV748X_CP_CON, ctrl->val); 653 break; 654 case V4L2_CID_SATURATION: 655 ret = cp_write(state, ADV748X_CP_SAT, ctrl->val); 656 break; 657 case V4L2_CID_TEST_PATTERN: 658 pattern = ctrl->val; 659 660 /* Pattern is 0-indexed. Ctrl Menu is 1-indexed */ 661 if (pattern) { 662 pattern--; 663 pattern |= ADV748X_CP_PAT_GEN_EN; 664 } 665 666 ret = cp_write(state, ADV748X_CP_PAT_GEN, pattern); 667 668 break; 669 default: 670 return -EINVAL; 671 } 672 673 return ret; 674 } 675 676 static const struct v4l2_ctrl_ops adv748x_hdmi_ctrl_ops = { 677 .s_ctrl = adv748x_hdmi_s_ctrl, 678 }; 679 680 static int adv748x_hdmi_init_controls(struct adv748x_hdmi *hdmi) 681 { 682 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 683 684 v4l2_ctrl_handler_init(&hdmi->ctrl_hdl, 5); 685 686 /* Use our mutex for the controls */ 687 hdmi->ctrl_hdl.lock = &state->mutex; 688 689 v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 690 V4L2_CID_BRIGHTNESS, ADV748X_CP_BRI_MIN, 691 ADV748X_CP_BRI_MAX, 1, ADV748X_CP_BRI_DEF); 692 v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 693 V4L2_CID_CONTRAST, ADV748X_CP_CON_MIN, 694 ADV748X_CP_CON_MAX, 1, ADV748X_CP_CON_DEF); 695 v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 696 V4L2_CID_SATURATION, ADV748X_CP_SAT_MIN, 697 ADV748X_CP_SAT_MAX, 1, ADV748X_CP_SAT_DEF); 698 v4l2_ctrl_new_std(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 699 V4L2_CID_HUE, ADV748X_CP_HUE_MIN, 700 ADV748X_CP_HUE_MAX, 1, ADV748X_CP_HUE_DEF); 701 702 /* 703 * Todo: V4L2_CID_DV_RX_POWER_PRESENT should also be supported when 704 * interrupts are handled correctly 705 */ 706 707 v4l2_ctrl_new_std_menu_items(&hdmi->ctrl_hdl, &adv748x_hdmi_ctrl_ops, 708 V4L2_CID_TEST_PATTERN, 709 ARRAY_SIZE(hdmi_ctrl_patgen_menu) - 1, 710 0, 0, hdmi_ctrl_patgen_menu); 711 712 hdmi->sd.ctrl_handler = &hdmi->ctrl_hdl; 713 if (hdmi->ctrl_hdl.error) { 714 v4l2_ctrl_handler_free(&hdmi->ctrl_hdl); 715 return hdmi->ctrl_hdl.error; 716 } 717 718 return v4l2_ctrl_handler_setup(&hdmi->ctrl_hdl); 719 } 720 721 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi) 722 { 723 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); 724 static const struct v4l2_dv_timings cea1280x720 = 725 V4L2_DV_BT_CEA_1280X720P30; 726 int ret; 727 728 hdmi->timings = cea1280x720; 729 730 /* Initialise a default 16:9 aspect ratio */ 731 hdmi->aspect_ratio.numerator = 16; 732 hdmi->aspect_ratio.denominator = 9; 733 734 adv748x_subdev_init(&hdmi->sd, state, &adv748x_ops_hdmi, 735 MEDIA_ENT_F_IO_DTV, "hdmi"); 736 737 hdmi->pads[ADV748X_HDMI_SINK].flags = MEDIA_PAD_FL_SINK; 738 hdmi->pads[ADV748X_HDMI_SOURCE].flags = MEDIA_PAD_FL_SOURCE; 739 740 ret = media_entity_pads_init(&hdmi->sd.entity, 741 ADV748X_HDMI_NR_PADS, hdmi->pads); 742 if (ret) 743 return ret; 744 745 ret = adv748x_hdmi_init_controls(hdmi); 746 if (ret) 747 goto err_free_media; 748 749 return 0; 750 751 err_free_media: 752 media_entity_cleanup(&hdmi->sd.entity); 753 754 return ret; 755 } 756 757 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi) 758 { 759 v4l2_device_unregister_subdev(&hdmi->sd); 760 media_entity_cleanup(&hdmi->sd.entity); 761 v4l2_ctrl_handler_free(&hdmi->ctrl_hdl); 762 } 763