1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mm/mmu.c 4 * 5 * Copyright (C) 1995-2005 Russell King 6 */ 7 #include <linux/module.h> 8 #include <linux/kernel.h> 9 #include <linux/errno.h> 10 #include <linux/init.h> 11 #include <linux/mman.h> 12 #include <linux/nodemask.h> 13 #include <linux/memblock.h> 14 #include <linux/fs.h> 15 #include <linux/vmalloc.h> 16 #include <linux/sizes.h> 17 18 #include <asm/cp15.h> 19 #include <asm/cputype.h> 20 #include <asm/sections.h> 21 #include <asm/cachetype.h> 22 #include <asm/fixmap.h> 23 #include <asm/sections.h> 24 #include <asm/setup.h> 25 #include <asm/smp_plat.h> 26 #include <asm/tlb.h> 27 #include <asm/highmem.h> 28 #include <asm/system_info.h> 29 #include <asm/traps.h> 30 #include <asm/procinfo.h> 31 #include <asm/memory.h> 32 33 #include <asm/mach/arch.h> 34 #include <asm/mach/map.h> 35 #include <asm/mach/pci.h> 36 #include <asm/fixmap.h> 37 38 #include "fault.h" 39 #include "mm.h" 40 #include "tcm.h" 41 42 /* 43 * empty_zero_page is a special page that is used for 44 * zero-initialized data and COW. 45 */ 46 struct page *empty_zero_page; 47 EXPORT_SYMBOL(empty_zero_page); 48 49 /* 50 * The pmd table for the upper-most set of pages. 51 */ 52 pmd_t *top_pmd; 53 54 pmdval_t user_pmd_table = _PAGE_USER_TABLE; 55 56 #define CPOLICY_UNCACHED 0 57 #define CPOLICY_BUFFERED 1 58 #define CPOLICY_WRITETHROUGH 2 59 #define CPOLICY_WRITEBACK 3 60 #define CPOLICY_WRITEALLOC 4 61 62 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 63 static unsigned int ecc_mask __initdata = 0; 64 pgprot_t pgprot_user; 65 pgprot_t pgprot_kernel; 66 67 EXPORT_SYMBOL(pgprot_user); 68 EXPORT_SYMBOL(pgprot_kernel); 69 70 struct cachepolicy { 71 const char policy[16]; 72 unsigned int cr_mask; 73 pmdval_t pmd; 74 pteval_t pte; 75 }; 76 77 unsigned long kimage_voffset __ro_after_init; 78 79 static struct cachepolicy cache_policies[] __initdata = { 80 { 81 .policy = "uncached", 82 .cr_mask = CR_W|CR_C, 83 .pmd = PMD_SECT_UNCACHED, 84 .pte = L_PTE_MT_UNCACHED, 85 }, { 86 .policy = "buffered", 87 .cr_mask = CR_C, 88 .pmd = PMD_SECT_BUFFERED, 89 .pte = L_PTE_MT_BUFFERABLE, 90 }, { 91 .policy = "writethrough", 92 .cr_mask = 0, 93 .pmd = PMD_SECT_WT, 94 .pte = L_PTE_MT_WRITETHROUGH, 95 }, { 96 .policy = "writeback", 97 .cr_mask = 0, 98 .pmd = PMD_SECT_WB, 99 .pte = L_PTE_MT_WRITEBACK, 100 }, { 101 .policy = "writealloc", 102 .cr_mask = 0, 103 .pmd = PMD_SECT_WBWA, 104 .pte = L_PTE_MT_WRITEALLOC, 105 } 106 }; 107 108 #ifdef CONFIG_CPU_CP15 109 static unsigned long initial_pmd_value __initdata = 0; 110 111 /* 112 * Initialise the cache_policy variable with the initial state specified 113 * via the "pmd" value. This is used to ensure that on ARMv6 and later, 114 * the C code sets the page tables up with the same policy as the head 115 * assembly code, which avoids an illegal state where the TLBs can get 116 * confused. See comments in early_cachepolicy() for more information. 117 */ 118 void __init init_default_cache_policy(unsigned long pmd) 119 { 120 int i; 121 122 initial_pmd_value = pmd; 123 124 pmd &= PMD_SECT_CACHE_MASK; 125 126 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) 127 if (cache_policies[i].pmd == pmd) { 128 cachepolicy = i; 129 break; 130 } 131 132 if (i == ARRAY_SIZE(cache_policies)) 133 pr_err("ERROR: could not find cache policy\n"); 134 } 135 136 /* 137 * These are useful for identifying cache coherency problems by allowing 138 * the cache or the cache and writebuffer to be turned off. (Note: the 139 * write buffer should not be on and the cache off). 140 */ 141 static int __init early_cachepolicy(char *p) 142 { 143 int i, selected = -1; 144 145 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 146 int len = strlen(cache_policies[i].policy); 147 148 if (memcmp(p, cache_policies[i].policy, len) == 0) { 149 selected = i; 150 break; 151 } 152 } 153 154 if (selected == -1) 155 pr_err("ERROR: unknown or unsupported cache policy\n"); 156 157 /* 158 * This restriction is partly to do with the way we boot; it is 159 * unpredictable to have memory mapped using two different sets of 160 * memory attributes (shared, type, and cache attribs). We can not 161 * change these attributes once the initial assembly has setup the 162 * page tables. 163 */ 164 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) { 165 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n", 166 cache_policies[cachepolicy].policy); 167 return 0; 168 } 169 170 if (selected != cachepolicy) { 171 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); 172 cachepolicy = selected; 173 flush_cache_all(); 174 set_cr(cr); 175 } 176 return 0; 177 } 178 early_param("cachepolicy", early_cachepolicy); 179 180 static int __init early_nocache(char *__unused) 181 { 182 char *p = "buffered"; 183 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p); 184 early_cachepolicy(p); 185 return 0; 186 } 187 early_param("nocache", early_nocache); 188 189 static int __init early_nowrite(char *__unused) 190 { 191 char *p = "uncached"; 192 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p); 193 early_cachepolicy(p); 194 return 0; 195 } 196 early_param("nowb", early_nowrite); 197 198 #ifndef CONFIG_ARM_LPAE 199 static int __init early_ecc(char *p) 200 { 201 if (memcmp(p, "on", 2) == 0) 202 ecc_mask = PMD_PROTECTION; 203 else if (memcmp(p, "off", 3) == 0) 204 ecc_mask = 0; 205 return 0; 206 } 207 early_param("ecc", early_ecc); 208 #endif 209 210 #else /* ifdef CONFIG_CPU_CP15 */ 211 212 static int __init early_cachepolicy(char *p) 213 { 214 pr_warn("cachepolicy kernel parameter not supported without cp15\n"); 215 } 216 early_param("cachepolicy", early_cachepolicy); 217 218 static int __init noalign_setup(char *__unused) 219 { 220 pr_warn("noalign kernel parameter not supported without cp15\n"); 221 } 222 __setup("noalign", noalign_setup); 223 224 #endif /* ifdef CONFIG_CPU_CP15 / else */ 225 226 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN 227 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE 228 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE 229 230 static struct mem_type mem_types[] __ro_after_init = { 231 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 232 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | 233 L_PTE_SHARED, 234 .prot_l1 = PMD_TYPE_TABLE, 235 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, 236 .domain = DOMAIN_IO, 237 }, 238 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 239 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 240 .prot_l1 = PMD_TYPE_TABLE, 241 .prot_sect = PROT_SECT_DEVICE, 242 .domain = DOMAIN_IO, 243 }, 244 [MT_DEVICE_CACHED] = { /* ioremap_cache */ 245 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, 246 .prot_l1 = PMD_TYPE_TABLE, 247 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 248 .domain = DOMAIN_IO, 249 }, 250 [MT_DEVICE_WC] = { /* ioremap_wc */ 251 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 252 .prot_l1 = PMD_TYPE_TABLE, 253 .prot_sect = PROT_SECT_DEVICE, 254 .domain = DOMAIN_IO, 255 }, 256 [MT_UNCACHED] = { 257 .prot_pte = PROT_PTE_DEVICE, 258 .prot_l1 = PMD_TYPE_TABLE, 259 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 260 .domain = DOMAIN_IO, 261 }, 262 [MT_CACHECLEAN] = { 263 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 264 .domain = DOMAIN_KERNEL, 265 }, 266 #ifndef CONFIG_ARM_LPAE 267 [MT_MINICLEAN] = { 268 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 269 .domain = DOMAIN_KERNEL, 270 }, 271 #endif 272 [MT_LOW_VECTORS] = { 273 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 274 L_PTE_RDONLY, 275 .prot_l1 = PMD_TYPE_TABLE, 276 .domain = DOMAIN_VECTORS, 277 }, 278 [MT_HIGH_VECTORS] = { 279 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 280 L_PTE_USER | L_PTE_RDONLY, 281 .prot_l1 = PMD_TYPE_TABLE, 282 .domain = DOMAIN_VECTORS, 283 }, 284 [MT_MEMORY_RWX] = { 285 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 286 .prot_l1 = PMD_TYPE_TABLE, 287 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 288 .domain = DOMAIN_KERNEL, 289 }, 290 [MT_MEMORY_RW] = { 291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 292 L_PTE_XN, 293 .prot_l1 = PMD_TYPE_TABLE, 294 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 295 .domain = DOMAIN_KERNEL, 296 }, 297 [MT_ROM] = { 298 .prot_sect = PMD_TYPE_SECT, 299 .domain = DOMAIN_KERNEL, 300 }, 301 [MT_MEMORY_RWX_NONCACHED] = { 302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 303 L_PTE_MT_BUFFERABLE, 304 .prot_l1 = PMD_TYPE_TABLE, 305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 306 .domain = DOMAIN_KERNEL, 307 }, 308 [MT_MEMORY_RW_DTCM] = { 309 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 310 L_PTE_XN, 311 .prot_l1 = PMD_TYPE_TABLE, 312 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 313 .domain = DOMAIN_KERNEL, 314 }, 315 [MT_MEMORY_RWX_ITCM] = { 316 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 317 .prot_l1 = PMD_TYPE_TABLE, 318 .domain = DOMAIN_KERNEL, 319 }, 320 [MT_MEMORY_RW_SO] = { 321 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 322 L_PTE_MT_UNCACHED | L_PTE_XN, 323 .prot_l1 = PMD_TYPE_TABLE, 324 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | 325 PMD_SECT_UNCACHED | PMD_SECT_XN, 326 .domain = DOMAIN_KERNEL, 327 }, 328 [MT_MEMORY_DMA_READY] = { 329 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 330 L_PTE_XN, 331 .prot_l1 = PMD_TYPE_TABLE, 332 .domain = DOMAIN_KERNEL, 333 }, 334 }; 335 336 const struct mem_type *get_mem_type(unsigned int type) 337 { 338 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 339 } 340 EXPORT_SYMBOL(get_mem_type); 341 342 static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr); 343 344 static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS] 345 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata; 346 347 static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr) 348 { 349 return &bm_pte[pte_index(addr)]; 350 } 351 352 static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr) 353 { 354 return pte_offset_kernel(dir, addr); 355 } 356 357 static inline pmd_t * __init fixmap_pmd(unsigned long addr) 358 { 359 pgd_t *pgd = pgd_offset_k(addr); 360 pud_t *pud = pud_offset(pgd, addr); 361 pmd_t *pmd = pmd_offset(pud, addr); 362 363 return pmd; 364 } 365 366 void __init early_fixmap_init(void) 367 { 368 pmd_t *pmd; 369 370 /* 371 * The early fixmap range spans multiple pmds, for which 372 * we are not prepared: 373 */ 374 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT) 375 != FIXADDR_TOP >> PMD_SHIFT); 376 377 pmd = fixmap_pmd(FIXADDR_TOP); 378 pmd_populate_kernel(&init_mm, pmd, bm_pte); 379 380 pte_offset_fixmap = pte_offset_early_fixmap; 381 } 382 383 /* 384 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). 385 * As a result, this can only be called with preemption disabled, as under 386 * stop_machine(). 387 */ 388 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) 389 { 390 unsigned long vaddr = __fix_to_virt(idx); 391 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr); 392 393 /* Make sure fixmap region does not exceed available allocation. */ 394 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) > 395 FIXADDR_END); 396 BUG_ON(idx >= __end_of_fixed_addresses); 397 398 /* we only support device mappings until pgprot_kernel has been set */ 399 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) && 400 pgprot_val(pgprot_kernel) == 0)) 401 return; 402 403 if (pgprot_val(prot)) 404 set_pte_at(NULL, vaddr, pte, 405 pfn_pte(phys >> PAGE_SHIFT, prot)); 406 else 407 pte_clear(NULL, vaddr, pte); 408 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); 409 } 410 411 /* 412 * Adjust the PMD section entries according to the CPU in use. 413 */ 414 static void __init build_mem_type_table(void) 415 { 416 struct cachepolicy *cp; 417 unsigned int cr = get_cr(); 418 pteval_t user_pgprot, kern_pgprot, vecs_pgprot; 419 int cpu_arch = cpu_architecture(); 420 int i; 421 422 if (cpu_arch < CPU_ARCH_ARMv6) { 423 #if defined(CONFIG_CPU_DCACHE_DISABLE) 424 if (cachepolicy > CPOLICY_BUFFERED) 425 cachepolicy = CPOLICY_BUFFERED; 426 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 427 if (cachepolicy > CPOLICY_WRITETHROUGH) 428 cachepolicy = CPOLICY_WRITETHROUGH; 429 #endif 430 } 431 if (cpu_arch < CPU_ARCH_ARMv5) { 432 if (cachepolicy >= CPOLICY_WRITEALLOC) 433 cachepolicy = CPOLICY_WRITEBACK; 434 ecc_mask = 0; 435 } 436 437 if (is_smp()) { 438 if (cachepolicy != CPOLICY_WRITEALLOC) { 439 pr_warn("Forcing write-allocate cache policy for SMP\n"); 440 cachepolicy = CPOLICY_WRITEALLOC; 441 } 442 if (!(initial_pmd_value & PMD_SECT_S)) { 443 pr_warn("Forcing shared mappings for SMP\n"); 444 initial_pmd_value |= PMD_SECT_S; 445 } 446 } 447 448 /* 449 * Strip out features not present on earlier architectures. 450 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those 451 * without extended page tables don't have the 'Shared' bit. 452 */ 453 if (cpu_arch < CPU_ARCH_ARMv5) 454 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 455 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); 456 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) 457 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 458 mem_types[i].prot_sect &= ~PMD_SECT_S; 459 460 /* 461 * ARMv5 and lower, bit 4 must be set for page tables (was: cache 462 * "update-able on write" bit on ARM610). However, Xscale and 463 * Xscale3 require this bit to be cleared. 464 */ 465 if (cpu_is_xscale_family()) { 466 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 467 mem_types[i].prot_sect &= ~PMD_BIT4; 468 mem_types[i].prot_l1 &= ~PMD_BIT4; 469 } 470 } else if (cpu_arch < CPU_ARCH_ARMv6) { 471 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 472 if (mem_types[i].prot_l1) 473 mem_types[i].prot_l1 |= PMD_BIT4; 474 if (mem_types[i].prot_sect) 475 mem_types[i].prot_sect |= PMD_BIT4; 476 } 477 } 478 479 /* 480 * Mark the device areas according to the CPU/architecture. 481 */ 482 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { 483 if (!cpu_is_xsc3()) { 484 /* 485 * Mark device regions on ARMv6+ as execute-never 486 * to prevent speculative instruction fetches. 487 */ 488 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; 489 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; 490 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; 491 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; 492 493 /* Also setup NX memory mapping */ 494 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; 495 } 496 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 497 /* 498 * For ARMv7 with TEX remapping, 499 * - shared device is SXCB=1100 500 * - nonshared device is SXCB=0100 501 * - write combine device mem is SXCB=0001 502 * (Uncached Normal memory) 503 */ 504 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); 505 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); 506 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 507 } else if (cpu_is_xsc3()) { 508 /* 509 * For Xscale3, 510 * - shared device is TEXCB=00101 511 * - nonshared device is TEXCB=01000 512 * - write combine device mem is TEXCB=00100 513 * (Inner/Outer Uncacheable in xsc3 parlance) 514 */ 515 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; 516 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 517 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 518 } else { 519 /* 520 * For ARMv6 and ARMv7 without TEX remapping, 521 * - shared device is TEXCB=00001 522 * - nonshared device is TEXCB=01000 523 * - write combine device mem is TEXCB=00100 524 * (Uncached Normal in ARMv6 parlance). 525 */ 526 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 527 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 528 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 529 } 530 } else { 531 /* 532 * On others, write combining is "Uncached/Buffered" 533 */ 534 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 535 } 536 537 /* 538 * Now deal with the memory-type mappings 539 */ 540 cp = &cache_policies[cachepolicy]; 541 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 542 543 #ifndef CONFIG_ARM_LPAE 544 /* 545 * We don't use domains on ARMv6 (since this causes problems with 546 * v6/v7 kernels), so we must use a separate memory type for user 547 * r/o, kernel r/w to map the vectors page. 548 */ 549 if (cpu_arch == CPU_ARCH_ARMv6) 550 vecs_pgprot |= L_PTE_MT_VECTORS; 551 552 /* 553 * Check is it with support for the PXN bit 554 * in the Short-descriptor translation table format descriptors. 555 */ 556 if (cpu_arch == CPU_ARCH_ARMv7 && 557 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) { 558 user_pmd_table |= PMD_PXNTABLE; 559 } 560 #endif 561 562 /* 563 * ARMv6 and above have extended page tables. 564 */ 565 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 566 #ifndef CONFIG_ARM_LPAE 567 /* 568 * Mark cache clean areas and XIP ROM read only 569 * from SVC mode and no access from userspace. 570 */ 571 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 572 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 573 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 574 #endif 575 576 /* 577 * If the initial page tables were created with the S bit 578 * set, then we need to do the same here for the same 579 * reasons given in early_cachepolicy(). 580 */ 581 if (initial_pmd_value & PMD_SECT_S) { 582 user_pgprot |= L_PTE_SHARED; 583 kern_pgprot |= L_PTE_SHARED; 584 vecs_pgprot |= L_PTE_SHARED; 585 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; 586 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 587 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 588 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 589 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; 590 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; 591 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; 592 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; 593 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; 594 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; 595 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; 596 } 597 } 598 599 /* 600 * Non-cacheable Normal - intended for memory areas that must 601 * not cause dirty cache line writebacks when used 602 */ 603 if (cpu_arch >= CPU_ARCH_ARMv6) { 604 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 605 /* Non-cacheable Normal is XCB = 001 */ 606 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= 607 PMD_SECT_BUFFERED; 608 } else { 609 /* For both ARMv6 and non-TEX-remapping ARMv7 */ 610 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= 611 PMD_SECT_TEX(1); 612 } 613 } else { 614 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; 615 } 616 617 #ifdef CONFIG_ARM_LPAE 618 /* 619 * Do not generate access flag faults for the kernel mappings. 620 */ 621 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 622 mem_types[i].prot_pte |= PTE_EXT_AF; 623 if (mem_types[i].prot_sect) 624 mem_types[i].prot_sect |= PMD_SECT_AF; 625 } 626 kern_pgprot |= PTE_EXT_AF; 627 vecs_pgprot |= PTE_EXT_AF; 628 629 /* 630 * Set PXN for user mappings 631 */ 632 user_pgprot |= PTE_EXT_PXN; 633 #endif 634 635 for (i = 0; i < 16; i++) { 636 pteval_t v = pgprot_val(protection_map[i]); 637 protection_map[i] = __pgprot(v | user_pgprot); 638 } 639 640 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; 641 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; 642 643 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 644 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 645 L_PTE_DIRTY | kern_pgprot); 646 647 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 648 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 649 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; 650 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; 651 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; 652 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; 653 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; 654 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; 655 mem_types[MT_ROM].prot_sect |= cp->pmd; 656 657 switch (cp->pmd) { 658 case PMD_SECT_WT: 659 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 660 break; 661 case PMD_SECT_WB: 662 case PMD_SECT_WBWA: 663 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 664 break; 665 } 666 pr_info("Memory policy: %sData cache %s\n", 667 ecc_mask ? "ECC enabled, " : "", cp->policy); 668 669 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 670 struct mem_type *t = &mem_types[i]; 671 if (t->prot_l1) 672 t->prot_l1 |= PMD_DOMAIN(t->domain); 673 if (t->prot_sect) 674 t->prot_sect |= PMD_DOMAIN(t->domain); 675 } 676 } 677 678 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 679 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 680 unsigned long size, pgprot_t vma_prot) 681 { 682 if (!pfn_valid(pfn)) 683 return pgprot_noncached(vma_prot); 684 else if (file->f_flags & O_SYNC) 685 return pgprot_writecombine(vma_prot); 686 return vma_prot; 687 } 688 EXPORT_SYMBOL(phys_mem_access_prot); 689 #endif 690 691 #define vectors_base() (vectors_high() ? 0xffff0000 : 0) 692 693 static void __init *early_alloc(unsigned long sz) 694 { 695 void *ptr = memblock_alloc(sz, sz); 696 697 if (!ptr) 698 panic("%s: Failed to allocate %lu bytes align=0x%lx\n", 699 __func__, sz, sz); 700 701 return ptr; 702 } 703 704 static void *__init late_alloc(unsigned long sz) 705 { 706 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz)); 707 708 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr))) 709 BUG(); 710 return ptr; 711 } 712 713 static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr, 714 unsigned long prot, 715 void *(*alloc)(unsigned long sz)) 716 { 717 if (pmd_none(*pmd)) { 718 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); 719 __pmd_populate(pmd, __pa(pte), prot); 720 } 721 BUG_ON(pmd_bad(*pmd)); 722 return pte_offset_kernel(pmd, addr); 723 } 724 725 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, 726 unsigned long prot) 727 { 728 return arm_pte_alloc(pmd, addr, prot, early_alloc); 729 } 730 731 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 732 unsigned long end, unsigned long pfn, 733 const struct mem_type *type, 734 void *(*alloc)(unsigned long sz), 735 bool ng) 736 { 737 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc); 738 do { 739 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 740 ng ? PTE_EXT_NG : 0); 741 pfn++; 742 } while (pte++, addr += PAGE_SIZE, addr != end); 743 } 744 745 static void __init __map_init_section(pmd_t *pmd, unsigned long addr, 746 unsigned long end, phys_addr_t phys, 747 const struct mem_type *type, bool ng) 748 { 749 pmd_t *p = pmd; 750 751 #ifndef CONFIG_ARM_LPAE 752 /* 753 * In classic MMU format, puds and pmds are folded in to 754 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a 755 * group of L1 entries making up one logical pointer to 756 * an L2 table (2MB), where as PMDs refer to the individual 757 * L1 entries (1MB). Hence increment to get the correct 758 * offset for odd 1MB sections. 759 * (See arch/arm/include/asm/pgtable-2level.h) 760 */ 761 if (addr & SECTION_SIZE) 762 pmd++; 763 #endif 764 do { 765 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0)); 766 phys += SECTION_SIZE; 767 } while (pmd++, addr += SECTION_SIZE, addr != end); 768 769 flush_pmd_entry(p); 770 } 771 772 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, 773 unsigned long end, phys_addr_t phys, 774 const struct mem_type *type, 775 void *(*alloc)(unsigned long sz), bool ng) 776 { 777 pmd_t *pmd = pmd_offset(pud, addr); 778 unsigned long next; 779 780 do { 781 /* 782 * With LPAE, we must loop over to map 783 * all the pmds for the given range. 784 */ 785 next = pmd_addr_end(addr, end); 786 787 /* 788 * Try a section mapping - addr, next and phys must all be 789 * aligned to a section boundary. 790 */ 791 if (type->prot_sect && 792 ((addr | next | phys) & ~SECTION_MASK) == 0) { 793 __map_init_section(pmd, addr, next, phys, type, ng); 794 } else { 795 alloc_init_pte(pmd, addr, next, 796 __phys_to_pfn(phys), type, alloc, ng); 797 } 798 799 phys += next - addr; 800 801 } while (pmd++, addr = next, addr != end); 802 } 803 804 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 805 unsigned long end, phys_addr_t phys, 806 const struct mem_type *type, 807 void *(*alloc)(unsigned long sz), bool ng) 808 { 809 pud_t *pud = pud_offset(pgd, addr); 810 unsigned long next; 811 812 do { 813 next = pud_addr_end(addr, end); 814 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng); 815 phys += next - addr; 816 } while (pud++, addr = next, addr != end); 817 } 818 819 #ifndef CONFIG_ARM_LPAE 820 static void __init create_36bit_mapping(struct mm_struct *mm, 821 struct map_desc *md, 822 const struct mem_type *type, 823 bool ng) 824 { 825 unsigned long addr, length, end; 826 phys_addr_t phys; 827 pgd_t *pgd; 828 829 addr = md->virtual; 830 phys = __pfn_to_phys(md->pfn); 831 length = PAGE_ALIGN(md->length); 832 833 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 834 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n", 835 (long long)__pfn_to_phys((u64)md->pfn), addr); 836 return; 837 } 838 839 /* N.B. ARMv6 supersections are only defined to work with domain 0. 840 * Since domain assignments can in fact be arbitrary, the 841 * 'domain == 0' check below is required to insure that ARMv6 842 * supersections are only allocated for domain 0 regardless 843 * of the actual domain assignments in use. 844 */ 845 if (type->domain) { 846 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n", 847 (long long)__pfn_to_phys((u64)md->pfn), addr); 848 return; 849 } 850 851 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 852 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n", 853 (long long)__pfn_to_phys((u64)md->pfn), addr); 854 return; 855 } 856 857 /* 858 * Shift bits [35:32] of address into bits [23:20] of PMD 859 * (See ARMv6 spec). 860 */ 861 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 862 863 pgd = pgd_offset(mm, addr); 864 end = addr + length; 865 do { 866 pud_t *pud = pud_offset(pgd, addr); 867 pmd_t *pmd = pmd_offset(pud, addr); 868 int i; 869 870 for (i = 0; i < 16; i++) 871 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER | 872 (ng ? PMD_SECT_nG : 0)); 873 874 addr += SUPERSECTION_SIZE; 875 phys += SUPERSECTION_SIZE; 876 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 877 } while (addr != end); 878 } 879 #endif /* !CONFIG_ARM_LPAE */ 880 881 static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md, 882 void *(*alloc)(unsigned long sz), 883 bool ng) 884 { 885 unsigned long addr, length, end; 886 phys_addr_t phys; 887 const struct mem_type *type; 888 pgd_t *pgd; 889 890 type = &mem_types[md->type]; 891 892 #ifndef CONFIG_ARM_LPAE 893 /* 894 * Catch 36-bit addresses 895 */ 896 if (md->pfn >= 0x100000) { 897 create_36bit_mapping(mm, md, type, ng); 898 return; 899 } 900 #endif 901 902 addr = md->virtual & PAGE_MASK; 903 phys = __pfn_to_phys(md->pfn); 904 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 905 906 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 907 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n", 908 (long long)__pfn_to_phys(md->pfn), addr); 909 return; 910 } 911 912 pgd = pgd_offset(mm, addr); 913 end = addr + length; 914 do { 915 unsigned long next = pgd_addr_end(addr, end); 916 917 alloc_init_pud(pgd, addr, next, phys, type, alloc, ng); 918 919 phys += next - addr; 920 addr = next; 921 } while (pgd++, addr != end); 922 } 923 924 /* 925 * Create the page directory entries and any necessary 926 * page tables for the mapping specified by `md'. We 927 * are able to cope here with varying sizes and address 928 * offsets, and we take full advantage of sections and 929 * supersections. 930 */ 931 static void __init create_mapping(struct map_desc *md) 932 { 933 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 934 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n", 935 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 936 return; 937 } 938 939 if ((md->type == MT_DEVICE || md->type == MT_ROM) && 940 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && 941 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { 942 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", 943 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 944 } 945 946 __create_mapping(&init_mm, md, early_alloc, false); 947 } 948 949 void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md, 950 bool ng) 951 { 952 #ifdef CONFIG_ARM_LPAE 953 pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual); 954 if (WARN_ON(!pud)) 955 return; 956 pmd_alloc(mm, pud, 0); 957 #endif 958 __create_mapping(mm, md, late_alloc, ng); 959 } 960 961 /* 962 * Create the architecture specific mappings 963 */ 964 void __init iotable_init(struct map_desc *io_desc, int nr) 965 { 966 struct map_desc *md; 967 struct vm_struct *vm; 968 struct static_vm *svm; 969 970 if (!nr) 971 return; 972 973 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm)); 974 if (!svm) 975 panic("%s: Failed to allocate %zu bytes align=0x%zx\n", 976 __func__, sizeof(*svm) * nr, __alignof__(*svm)); 977 978 for (md = io_desc; nr; md++, nr--) { 979 create_mapping(md); 980 981 vm = &svm->vm; 982 vm->addr = (void *)(md->virtual & PAGE_MASK); 983 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 984 vm->phys_addr = __pfn_to_phys(md->pfn); 985 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 986 vm->flags |= VM_ARM_MTYPE(md->type); 987 vm->caller = iotable_init; 988 add_static_vm_early(svm++); 989 } 990 } 991 992 void __init vm_reserve_area_early(unsigned long addr, unsigned long size, 993 void *caller) 994 { 995 struct vm_struct *vm; 996 struct static_vm *svm; 997 998 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm)); 999 if (!svm) 1000 panic("%s: Failed to allocate %zu bytes align=0x%zx\n", 1001 __func__, sizeof(*svm), __alignof__(*svm)); 1002 1003 vm = &svm->vm; 1004 vm->addr = (void *)addr; 1005 vm->size = size; 1006 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; 1007 vm->caller = caller; 1008 add_static_vm_early(svm); 1009 } 1010 1011 #ifndef CONFIG_ARM_LPAE 1012 1013 /* 1014 * The Linux PMD is made of two consecutive section entries covering 2MB 1015 * (see definition in include/asm/pgtable-2level.h). However a call to 1016 * create_mapping() may optimize static mappings by using individual 1017 * 1MB section mappings. This leaves the actual PMD potentially half 1018 * initialized if the top or bottom section entry isn't used, leaving it 1019 * open to problems if a subsequent ioremap() or vmalloc() tries to use 1020 * the virtual space left free by that unused section entry. 1021 * 1022 * Let's avoid the issue by inserting dummy vm entries covering the unused 1023 * PMD halves once the static mappings are in place. 1024 */ 1025 1026 static void __init pmd_empty_section_gap(unsigned long addr) 1027 { 1028 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); 1029 } 1030 1031 static void __init fill_pmd_gaps(void) 1032 { 1033 struct static_vm *svm; 1034 struct vm_struct *vm; 1035 unsigned long addr, next = 0; 1036 pmd_t *pmd; 1037 1038 list_for_each_entry(svm, &static_vmlist, list) { 1039 vm = &svm->vm; 1040 addr = (unsigned long)vm->addr; 1041 if (addr < next) 1042 continue; 1043 1044 /* 1045 * Check if this vm starts on an odd section boundary. 1046 * If so and the first section entry for this PMD is free 1047 * then we block the corresponding virtual address. 1048 */ 1049 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 1050 pmd = pmd_off_k(addr); 1051 if (pmd_none(*pmd)) 1052 pmd_empty_section_gap(addr & PMD_MASK); 1053 } 1054 1055 /* 1056 * Then check if this vm ends on an odd section boundary. 1057 * If so and the second section entry for this PMD is empty 1058 * then we block the corresponding virtual address. 1059 */ 1060 addr += vm->size; 1061 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 1062 pmd = pmd_off_k(addr) + 1; 1063 if (pmd_none(*pmd)) 1064 pmd_empty_section_gap(addr); 1065 } 1066 1067 /* no need to look at any vm entry until we hit the next PMD */ 1068 next = (addr + PMD_SIZE - 1) & PMD_MASK; 1069 } 1070 } 1071 1072 #else 1073 #define fill_pmd_gaps() do { } while (0) 1074 #endif 1075 1076 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) 1077 static void __init pci_reserve_io(void) 1078 { 1079 struct static_vm *svm; 1080 1081 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); 1082 if (svm) 1083 return; 1084 1085 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); 1086 } 1087 #else 1088 #define pci_reserve_io() do { } while (0) 1089 #endif 1090 1091 #ifdef CONFIG_DEBUG_LL 1092 void __init debug_ll_io_init(void) 1093 { 1094 struct map_desc map; 1095 1096 debug_ll_addr(&map.pfn, &map.virtual); 1097 if (!map.pfn || !map.virtual) 1098 return; 1099 map.pfn = __phys_to_pfn(map.pfn); 1100 map.virtual &= PAGE_MASK; 1101 map.length = PAGE_SIZE; 1102 map.type = MT_DEVICE; 1103 iotable_init(&map, 1); 1104 } 1105 #endif 1106 1107 static void * __initdata vmalloc_min = 1108 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); 1109 1110 /* 1111 * vmalloc=size forces the vmalloc area to be exactly 'size' 1112 * bytes. This can be used to increase (or decrease) the vmalloc 1113 * area - the default is 240m. 1114 */ 1115 static int __init early_vmalloc(char *arg) 1116 { 1117 unsigned long vmalloc_reserve = memparse(arg, NULL); 1118 1119 if (vmalloc_reserve < SZ_16M) { 1120 vmalloc_reserve = SZ_16M; 1121 pr_warn("vmalloc area too small, limiting to %luMB\n", 1122 vmalloc_reserve >> 20); 1123 } 1124 1125 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { 1126 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); 1127 pr_warn("vmalloc area is too big, limiting to %luMB\n", 1128 vmalloc_reserve >> 20); 1129 } 1130 1131 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); 1132 return 0; 1133 } 1134 early_param("vmalloc", early_vmalloc); 1135 1136 phys_addr_t arm_lowmem_limit __initdata = 0; 1137 1138 void __init adjust_lowmem_bounds(void) 1139 { 1140 phys_addr_t memblock_limit = 0; 1141 u64 vmalloc_limit; 1142 struct memblock_region *reg; 1143 phys_addr_t lowmem_limit = 0; 1144 1145 /* 1146 * Let's use our own (unoptimized) equivalent of __pa() that is 1147 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4. 1148 * The result is used as the upper bound on physical memory address 1149 * and may itself be outside the valid range for which phys_addr_t 1150 * and therefore __pa() is defined. 1151 */ 1152 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET; 1153 1154 /* 1155 * The first usable region must be PMD aligned. Mark its start 1156 * as MEMBLOCK_NOMAP if it isn't 1157 */ 1158 for_each_memblock(memory, reg) { 1159 if (!memblock_is_nomap(reg)) { 1160 if (!IS_ALIGNED(reg->base, PMD_SIZE)) { 1161 phys_addr_t len; 1162 1163 len = round_up(reg->base, PMD_SIZE) - reg->base; 1164 memblock_mark_nomap(reg->base, len); 1165 } 1166 break; 1167 } 1168 } 1169 1170 for_each_memblock(memory, reg) { 1171 phys_addr_t block_start = reg->base; 1172 phys_addr_t block_end = reg->base + reg->size; 1173 1174 if (memblock_is_nomap(reg)) 1175 continue; 1176 1177 if (reg->base < vmalloc_limit) { 1178 if (block_end > lowmem_limit) 1179 /* 1180 * Compare as u64 to ensure vmalloc_limit does 1181 * not get truncated. block_end should always 1182 * fit in phys_addr_t so there should be no 1183 * issue with assignment. 1184 */ 1185 lowmem_limit = min_t(u64, 1186 vmalloc_limit, 1187 block_end); 1188 1189 /* 1190 * Find the first non-pmd-aligned page, and point 1191 * memblock_limit at it. This relies on rounding the 1192 * limit down to be pmd-aligned, which happens at the 1193 * end of this function. 1194 * 1195 * With this algorithm, the start or end of almost any 1196 * bank can be non-pmd-aligned. The only exception is 1197 * that the start of the bank 0 must be section- 1198 * aligned, since otherwise memory would need to be 1199 * allocated when mapping the start of bank 0, which 1200 * occurs before any free memory is mapped. 1201 */ 1202 if (!memblock_limit) { 1203 if (!IS_ALIGNED(block_start, PMD_SIZE)) 1204 memblock_limit = block_start; 1205 else if (!IS_ALIGNED(block_end, PMD_SIZE)) 1206 memblock_limit = lowmem_limit; 1207 } 1208 1209 } 1210 } 1211 1212 arm_lowmem_limit = lowmem_limit; 1213 1214 high_memory = __va(arm_lowmem_limit - 1) + 1; 1215 1216 if (!memblock_limit) 1217 memblock_limit = arm_lowmem_limit; 1218 1219 /* 1220 * Round the memblock limit down to a pmd size. This 1221 * helps to ensure that we will allocate memory from the 1222 * last full pmd, which should be mapped. 1223 */ 1224 memblock_limit = round_down(memblock_limit, PMD_SIZE); 1225 1226 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) { 1227 if (memblock_end_of_DRAM() > arm_lowmem_limit) { 1228 phys_addr_t end = memblock_end_of_DRAM(); 1229 1230 pr_notice("Ignoring RAM at %pa-%pa\n", 1231 &memblock_limit, &end); 1232 pr_notice("Consider using a HIGHMEM enabled kernel.\n"); 1233 1234 memblock_remove(memblock_limit, end - memblock_limit); 1235 } 1236 } 1237 1238 memblock_set_current_limit(memblock_limit); 1239 } 1240 1241 static inline void prepare_page_table(void) 1242 { 1243 unsigned long addr; 1244 phys_addr_t end; 1245 1246 /* 1247 * Clear out all the mappings below the kernel image. 1248 */ 1249 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) 1250 pmd_clear(pmd_off_k(addr)); 1251 1252 #ifdef CONFIG_XIP_KERNEL 1253 /* The XIP kernel is mapped in the module area -- skip over it */ 1254 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK; 1255 #endif 1256 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) 1257 pmd_clear(pmd_off_k(addr)); 1258 1259 /* 1260 * Find the end of the first block of lowmem. 1261 */ 1262 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; 1263 if (end >= arm_lowmem_limit) 1264 end = arm_lowmem_limit; 1265 1266 /* 1267 * Clear out all the kernel space mappings, except for the first 1268 * memory bank, up to the vmalloc region. 1269 */ 1270 for (addr = __phys_to_virt(end); 1271 addr < VMALLOC_START; addr += PMD_SIZE) 1272 pmd_clear(pmd_off_k(addr)); 1273 } 1274 1275 #ifdef CONFIG_ARM_LPAE 1276 /* the first page is reserved for pgd */ 1277 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ 1278 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) 1279 #else 1280 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) 1281 #endif 1282 1283 /* 1284 * Reserve the special regions of memory 1285 */ 1286 void __init arm_mm_memblock_reserve(void) 1287 { 1288 /* 1289 * Reserve the page tables. These are already in use, 1290 * and can only be in node 0. 1291 */ 1292 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); 1293 1294 #ifdef CONFIG_SA1111 1295 /* 1296 * Because of the SA1111 DMA bug, we want to preserve our 1297 * precious DMA-able memory... 1298 */ 1299 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); 1300 #endif 1301 } 1302 1303 /* 1304 * Set up the device mappings. Since we clear out the page tables for all 1305 * mappings above VMALLOC_START, except early fixmap, we might remove debug 1306 * device mappings. This means earlycon can be used to debug this function 1307 * Any other function or debugging method which may touch any device _will_ 1308 * crash the kernel. 1309 */ 1310 static void __init devicemaps_init(const struct machine_desc *mdesc) 1311 { 1312 struct map_desc map; 1313 unsigned long addr; 1314 void *vectors; 1315 1316 /* 1317 * Allocate the vector page early. 1318 */ 1319 vectors = early_alloc(PAGE_SIZE * 2); 1320 1321 early_trap_init(vectors); 1322 1323 /* 1324 * Clear page table except top pmd used by early fixmaps 1325 */ 1326 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) 1327 pmd_clear(pmd_off_k(addr)); 1328 1329 /* 1330 * Map the kernel if it is XIP. 1331 * It is always first in the modulearea. 1332 */ 1333 #ifdef CONFIG_XIP_KERNEL 1334 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 1335 map.virtual = MODULES_VADDR; 1336 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK; 1337 map.type = MT_ROM; 1338 create_mapping(&map); 1339 #endif 1340 1341 /* 1342 * Map the cache flushing regions. 1343 */ 1344 #ifdef FLUSH_BASE 1345 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 1346 map.virtual = FLUSH_BASE; 1347 map.length = SZ_1M; 1348 map.type = MT_CACHECLEAN; 1349 create_mapping(&map); 1350 #endif 1351 #ifdef FLUSH_BASE_MINICACHE 1352 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 1353 map.virtual = FLUSH_BASE_MINICACHE; 1354 map.length = SZ_1M; 1355 map.type = MT_MINICLEAN; 1356 create_mapping(&map); 1357 #endif 1358 1359 /* 1360 * Create a mapping for the machine vectors at the high-vectors 1361 * location (0xffff0000). If we aren't using high-vectors, also 1362 * create a mapping at the low-vectors virtual address. 1363 */ 1364 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 1365 map.virtual = 0xffff0000; 1366 map.length = PAGE_SIZE; 1367 #ifdef CONFIG_KUSER_HELPERS 1368 map.type = MT_HIGH_VECTORS; 1369 #else 1370 map.type = MT_LOW_VECTORS; 1371 #endif 1372 create_mapping(&map); 1373 1374 if (!vectors_high()) { 1375 map.virtual = 0; 1376 map.length = PAGE_SIZE * 2; 1377 map.type = MT_LOW_VECTORS; 1378 create_mapping(&map); 1379 } 1380 1381 /* Now create a kernel read-only mapping */ 1382 map.pfn += 1; 1383 map.virtual = 0xffff0000 + PAGE_SIZE; 1384 map.length = PAGE_SIZE; 1385 map.type = MT_LOW_VECTORS; 1386 create_mapping(&map); 1387 1388 /* 1389 * Ask the machine support to map in the statically mapped devices. 1390 */ 1391 if (mdesc->map_io) 1392 mdesc->map_io(); 1393 else 1394 debug_ll_io_init(); 1395 fill_pmd_gaps(); 1396 1397 /* Reserve fixed i/o space in VMALLOC region */ 1398 pci_reserve_io(); 1399 1400 /* 1401 * Finally flush the caches and tlb to ensure that we're in a 1402 * consistent state wrt the writebuffer. This also ensures that 1403 * any write-allocated cache lines in the vector page are written 1404 * back. After this point, we can start to touch devices again. 1405 */ 1406 local_flush_tlb_all(); 1407 flush_cache_all(); 1408 1409 /* Enable asynchronous aborts */ 1410 early_abt_enable(); 1411 } 1412 1413 static void __init kmap_init(void) 1414 { 1415 #ifdef CONFIG_HIGHMEM 1416 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), 1417 PKMAP_BASE, _PAGE_KERNEL_TABLE); 1418 #endif 1419 1420 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START, 1421 _PAGE_KERNEL_TABLE); 1422 } 1423 1424 static void __init map_lowmem(void) 1425 { 1426 struct memblock_region *reg; 1427 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE); 1428 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); 1429 1430 /* Map all the lowmem memory banks. */ 1431 for_each_memblock(memory, reg) { 1432 phys_addr_t start = reg->base; 1433 phys_addr_t end = start + reg->size; 1434 struct map_desc map; 1435 1436 if (memblock_is_nomap(reg)) 1437 continue; 1438 1439 if (end > arm_lowmem_limit) 1440 end = arm_lowmem_limit; 1441 if (start >= end) 1442 break; 1443 1444 if (end < kernel_x_start) { 1445 map.pfn = __phys_to_pfn(start); 1446 map.virtual = __phys_to_virt(start); 1447 map.length = end - start; 1448 map.type = MT_MEMORY_RWX; 1449 1450 create_mapping(&map); 1451 } else if (start >= kernel_x_end) { 1452 map.pfn = __phys_to_pfn(start); 1453 map.virtual = __phys_to_virt(start); 1454 map.length = end - start; 1455 map.type = MT_MEMORY_RW; 1456 1457 create_mapping(&map); 1458 } else { 1459 /* This better cover the entire kernel */ 1460 if (start < kernel_x_start) { 1461 map.pfn = __phys_to_pfn(start); 1462 map.virtual = __phys_to_virt(start); 1463 map.length = kernel_x_start - start; 1464 map.type = MT_MEMORY_RW; 1465 1466 create_mapping(&map); 1467 } 1468 1469 map.pfn = __phys_to_pfn(kernel_x_start); 1470 map.virtual = __phys_to_virt(kernel_x_start); 1471 map.length = kernel_x_end - kernel_x_start; 1472 map.type = MT_MEMORY_RWX; 1473 1474 create_mapping(&map); 1475 1476 if (kernel_x_end < end) { 1477 map.pfn = __phys_to_pfn(kernel_x_end); 1478 map.virtual = __phys_to_virt(kernel_x_end); 1479 map.length = end - kernel_x_end; 1480 map.type = MT_MEMORY_RW; 1481 1482 create_mapping(&map); 1483 } 1484 } 1485 } 1486 } 1487 1488 #ifdef CONFIG_ARM_PV_FIXUP 1489 extern unsigned long __atags_pointer; 1490 typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata); 1491 pgtables_remap lpae_pgtables_remap_asm; 1492 1493 /* 1494 * early_paging_init() recreates boot time page table setup, allowing machines 1495 * to switch over to a high (>4G) address space on LPAE systems 1496 */ 1497 static void __init early_paging_init(const struct machine_desc *mdesc) 1498 { 1499 pgtables_remap *lpae_pgtables_remap; 1500 unsigned long pa_pgd; 1501 unsigned int cr, ttbcr; 1502 long long offset; 1503 void *boot_data; 1504 1505 if (!mdesc->pv_fixup) 1506 return; 1507 1508 offset = mdesc->pv_fixup(); 1509 if (offset == 0) 1510 return; 1511 1512 /* 1513 * Get the address of the remap function in the 1:1 identity 1514 * mapping setup by the early page table assembly code. We 1515 * must get this prior to the pv update. The following barrier 1516 * ensures that this is complete before we fixup any P:V offsets. 1517 */ 1518 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); 1519 pa_pgd = __pa(swapper_pg_dir); 1520 boot_data = __va(__atags_pointer); 1521 barrier(); 1522 1523 pr_info("Switching physical address space to 0x%08llx\n", 1524 (u64)PHYS_OFFSET + offset); 1525 1526 /* Re-set the phys pfn offset, and the pv offset */ 1527 __pv_offset += offset; 1528 __pv_phys_pfn_offset += PFN_DOWN(offset); 1529 1530 /* Run the patch stub to update the constants */ 1531 fixup_pv_table(&__pv_table_begin, 1532 (&__pv_table_end - &__pv_table_begin) << 2); 1533 1534 /* 1535 * We changing not only the virtual to physical mapping, but also 1536 * the physical addresses used to access memory. We need to flush 1537 * all levels of cache in the system with caching disabled to 1538 * ensure that all data is written back, and nothing is prefetched 1539 * into the caches. We also need to prevent the TLB walkers 1540 * allocating into the caches too. Note that this is ARMv7 LPAE 1541 * specific. 1542 */ 1543 cr = get_cr(); 1544 set_cr(cr & ~(CR_I | CR_C)); 1545 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr)); 1546 asm volatile("mcr p15, 0, %0, c2, c0, 2" 1547 : : "r" (ttbcr & ~(3 << 8 | 3 << 10))); 1548 flush_cache_all(); 1549 1550 /* 1551 * Fixup the page tables - this must be in the idmap region as 1552 * we need to disable the MMU to do this safely, and hence it 1553 * needs to be assembly. It's fairly simple, as we're using the 1554 * temporary tables setup by the initial assembly code. 1555 */ 1556 lpae_pgtables_remap(offset, pa_pgd, boot_data); 1557 1558 /* Re-enable the caches and cacheable TLB walks */ 1559 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr)); 1560 set_cr(cr); 1561 } 1562 1563 #else 1564 1565 static void __init early_paging_init(const struct machine_desc *mdesc) 1566 { 1567 long long offset; 1568 1569 if (!mdesc->pv_fixup) 1570 return; 1571 1572 offset = mdesc->pv_fixup(); 1573 if (offset == 0) 1574 return; 1575 1576 pr_crit("Physical address space modification is only to support Keystone2.\n"); 1577 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n"); 1578 pr_crit("feature. Your kernel may crash now, have a good day.\n"); 1579 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1580 } 1581 1582 #endif 1583 1584 static void __init early_fixmap_shutdown(void) 1585 { 1586 int i; 1587 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1); 1588 1589 pte_offset_fixmap = pte_offset_late_fixmap; 1590 pmd_clear(fixmap_pmd(va)); 1591 local_flush_tlb_kernel_page(va); 1592 1593 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) { 1594 pte_t *pte; 1595 struct map_desc map; 1596 1597 map.virtual = fix_to_virt(i); 1598 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual); 1599 1600 /* Only i/o device mappings are supported ATM */ 1601 if (pte_none(*pte) || 1602 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED) 1603 continue; 1604 1605 map.pfn = pte_pfn(*pte); 1606 map.type = MT_DEVICE; 1607 map.length = PAGE_SIZE; 1608 1609 create_mapping(&map); 1610 } 1611 } 1612 1613 /* 1614 * paging_init() sets up the page tables, initialises the zone memory 1615 * maps, and sets up the zero page, bad page and bad page tables. 1616 */ 1617 void __init paging_init(const struct machine_desc *mdesc) 1618 { 1619 void *zero_page; 1620 1621 prepare_page_table(); 1622 map_lowmem(); 1623 memblock_set_current_limit(arm_lowmem_limit); 1624 dma_contiguous_remap(); 1625 early_fixmap_shutdown(); 1626 devicemaps_init(mdesc); 1627 kmap_init(); 1628 tcm_init(); 1629 1630 top_pmd = pmd_off_k(0xffff0000); 1631 1632 /* allocate the zero page. */ 1633 zero_page = early_alloc(PAGE_SIZE); 1634 1635 bootmem_init(); 1636 1637 empty_zero_page = virt_to_page(zero_page); 1638 __flush_dcache_page(NULL, empty_zero_page); 1639 1640 /* Compute the virt/idmap offset, mostly for the sake of KVM */ 1641 kimage_voffset = (unsigned long)&kimage_voffset - virt_to_idmap(&kimage_voffset); 1642 } 1643 1644 void __init early_mm_init(const struct machine_desc *mdesc) 1645 { 1646 build_mem_type_table(); 1647 early_paging_init(mdesc); 1648 } 1649 1650 void set_pte_at(struct mm_struct *mm, unsigned long addr, 1651 pte_t *ptep, pte_t pteval) 1652 { 1653 unsigned long ext = 0; 1654 1655 if (addr < TASK_SIZE && pte_valid_user(pteval)) { 1656 if (!pte_special(pteval)) 1657 __sync_icache_dcache(pteval); 1658 ext |= PTE_EXT_NG; 1659 } 1660 1661 set_pte_ext(ptep, pteval, ext); 1662 } 1663