1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * wm8991.c -- WM8991 ALSA Soc Audio driver 4 * 5 * Copyright 2007-2010 Wolfson Microelectronics PLC. 6 * Author: Graeme Gregory 7 * Graeme.Gregory@wolfsonmicro.com 8 */ 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/initval.h> 25 #include <sound/tlv.h> 26 #include <asm/div64.h> 27 28 #include "wm8991.h" 29 30 struct wm8991_priv { 31 struct regmap *regmap; 32 unsigned int pcmclk; 33 }; 34 35 static const struct reg_default wm8991_reg_defaults[] = { 36 { 1, 0x0000 }, /* R1 - Power Management (1) */ 37 { 2, 0x6000 }, /* R2 - Power Management (2) */ 38 { 3, 0x0000 }, /* R3 - Power Management (3) */ 39 { 4, 0x4050 }, /* R4 - Audio Interface (1) */ 40 { 5, 0x4000 }, /* R5 - Audio Interface (2) */ 41 { 6, 0x01C8 }, /* R6 - Clocking (1) */ 42 { 7, 0x0000 }, /* R7 - Clocking (2) */ 43 { 8, 0x0040 }, /* R8 - Audio Interface (3) */ 44 { 9, 0x0040 }, /* R9 - Audio Interface (4) */ 45 { 10, 0x0004 }, /* R10 - DAC CTRL */ 46 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */ 47 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */ 48 { 13, 0x0000 }, /* R13 - Digital Side Tone */ 49 { 14, 0x0100 }, /* R14 - ADC CTRL */ 50 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */ 51 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */ 52 53 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */ 54 { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */ 55 { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */ 56 { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */ 57 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */ 58 { 23, 0x0800 }, /* R23 - GPIO_POL */ 59 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ 60 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ 61 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ 62 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ 63 { 28, 0x0000 }, /* R28 - Left Output Volume */ 64 { 29, 0x0000 }, /* R29 - Right Output Volume */ 65 { 30, 0x0066 }, /* R30 - Line Outputs Volume */ 66 { 31, 0x0022 }, /* R31 - Out3/4 Volume */ 67 { 32, 0x0079 }, /* R32 - Left OPGA Volume */ 68 { 33, 0x0079 }, /* R33 - Right OPGA Volume */ 69 { 34, 0x0003 }, /* R34 - Speaker Volume */ 70 { 35, 0x0003 }, /* R35 - ClassD1 */ 71 72 { 37, 0x0100 }, /* R37 - ClassD3 */ 73 74 { 39, 0x0000 }, /* R39 - Input Mixer1 */ 75 { 40, 0x0000 }, /* R40 - Input Mixer2 */ 76 { 41, 0x0000 }, /* R41 - Input Mixer3 */ 77 { 42, 0x0000 }, /* R42 - Input Mixer4 */ 78 { 43, 0x0000 }, /* R43 - Input Mixer5 */ 79 { 44, 0x0000 }, /* R44 - Input Mixer6 */ 80 { 45, 0x0000 }, /* R45 - Output Mixer1 */ 81 { 46, 0x0000 }, /* R46 - Output Mixer2 */ 82 { 47, 0x0000 }, /* R47 - Output Mixer3 */ 83 { 48, 0x0000 }, /* R48 - Output Mixer4 */ 84 { 49, 0x0000 }, /* R49 - Output Mixer5 */ 85 { 50, 0x0000 }, /* R50 - Output Mixer6 */ 86 { 51, 0x0180 }, /* R51 - Out3/4 Mixer */ 87 { 52, 0x0000 }, /* R52 - Line Mixer1 */ 88 { 53, 0x0000 }, /* R53 - Line Mixer2 */ 89 { 54, 0x0000 }, /* R54 - Speaker Mixer */ 90 { 55, 0x0000 }, /* R55 - Additional Control */ 91 { 56, 0x0000 }, /* R56 - AntiPOP1 */ 92 { 57, 0x0000 }, /* R57 - AntiPOP2 */ 93 { 58, 0x0000 }, /* R58 - MICBIAS */ 94 95 { 60, 0x0008 }, /* R60 - PLL1 */ 96 { 61, 0x0031 }, /* R61 - PLL2 */ 97 { 62, 0x0026 }, /* R62 - PLL3 */ 98 }; 99 100 static bool wm8991_volatile(struct device *dev, unsigned int reg) 101 { 102 switch (reg) { 103 case WM8991_RESET: 104 return true; 105 default: 106 return false; 107 } 108 } 109 110 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_pga_tlv, -1650, 150, 0); 111 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(out_mix_tlv, -2100, 300, 0); 112 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_pga_tlv, 113 0x00, 0x2f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(SNDRV_CTL_TLVD_DB_GAIN_MUTE, 0, 1), 114 0x30, 0x7f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-7300, 100, 0), 115 ); 116 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_dac_tlv, 117 0x00, 0xbf, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1), 118 0xc0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0), 119 ); 120 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(in_adc_tlv, 121 0x00, 0xef, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1), 122 0xf0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(17625, 0, 0), 123 ); 124 static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_sidetone_tlv, 125 0x00, 0x0c, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-3600, 300, 0), 126 0x0d, 0x0f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0), 127 ); 128 129 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 130 struct snd_ctl_elem_value *ucontrol) 131 { 132 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 133 int reg = kcontrol->private_value & 0xff; 134 int ret; 135 u16 val; 136 137 ret = snd_soc_put_volsw(kcontrol, ucontrol); 138 if (ret < 0) 139 return ret; 140 141 /* now hit the volume update bits (always bit 8) */ 142 val = snd_soc_component_read32(component, reg); 143 return snd_soc_component_write(component, reg, val | 0x0100); 144 } 145 146 static const char *wm8991_digital_sidetone[] = 147 {"None", "Left ADC", "Right ADC", "Reserved"}; 148 149 static SOC_ENUM_SINGLE_DECL(wm8991_left_digital_sidetone_enum, 150 WM8991_DIGITAL_SIDE_TONE, 151 WM8991_ADC_TO_DACL_SHIFT, 152 wm8991_digital_sidetone); 153 154 static SOC_ENUM_SINGLE_DECL(wm8991_right_digital_sidetone_enum, 155 WM8991_DIGITAL_SIDE_TONE, 156 WM8991_ADC_TO_DACR_SHIFT, 157 wm8991_digital_sidetone); 158 159 static const char *wm8991_adcmode[] = 160 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 161 162 static SOC_ENUM_SINGLE_DECL(wm8991_right_adcmode_enum, 163 WM8991_ADC_CTRL, 164 WM8991_ADC_HPF_CUT_SHIFT, 165 wm8991_adcmode); 166 167 static const struct snd_kcontrol_new wm8991_snd_controls[] = { 168 /* INMIXL */ 169 SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0), 170 SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0), 171 /* INMIXR */ 172 SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0), 173 SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0), 174 175 /* LOMIX */ 176 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3, 177 WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv), 178 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, 179 WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv), 180 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, 181 WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv), 182 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5, 183 WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv), 184 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5, 185 WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), 186 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5, 187 WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), 188 189 /* ROMIX */ 190 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4, 191 WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv), 192 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, 193 WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv), 194 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, 195 WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv), 196 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6, 197 WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv), 198 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6, 199 WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv), 200 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6, 201 WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv), 202 203 /* LOUT */ 204 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME, 205 WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv), 206 SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0), 207 208 /* ROUT */ 209 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME, 210 WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv), 211 SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0), 212 213 /* LOPGA */ 214 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME, 215 WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv), 216 SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME, 217 WM8991_LOPGAZC_BIT, 1, 0), 218 219 /* ROPGA */ 220 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME, 221 WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv), 222 SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME, 223 WM8991_ROPGAZC_BIT, 1, 0), 224 225 SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 226 WM8991_LONMUTE_BIT, 1, 0), 227 SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 228 WM8991_LOPMUTE_BIT, 1, 0), 229 SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, 230 WM8991_LOATTN_BIT, 1, 0), 231 SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 232 WM8991_RONMUTE_BIT, 1, 0), 233 SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 234 WM8991_ROPMUTE_BIT, 1, 0), 235 SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, 236 WM8991_ROATTN_BIT, 1, 0), 237 238 SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME, 239 WM8991_OUT3MUTE_BIT, 1, 0), 240 SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME, 241 WM8991_OUT3ATTN_BIT, 1, 0), 242 243 SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME, 244 WM8991_OUT4MUTE_BIT, 1, 0), 245 SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME, 246 WM8991_OUT4ATTN_BIT, 1, 0), 247 248 SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1, 249 WM8991_CDMODE_BIT, 1, 0), 250 251 SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME, 252 WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0), 253 SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3, 254 WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0), 255 SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3, 256 WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0), 257 258 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 259 WM8991_LEFT_DAC_DIGITAL_VOLUME, 260 WM8991_DACL_VOL_SHIFT, 261 WM8991_DACL_VOL_MASK, 262 0, 263 out_dac_tlv), 264 265 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 266 WM8991_RIGHT_DAC_DIGITAL_VOLUME, 267 WM8991_DACR_VOL_SHIFT, 268 WM8991_DACR_VOL_MASK, 269 0, 270 out_dac_tlv), 271 272 SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum), 273 SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum), 274 275 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, 276 WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0, 277 out_sidetone_tlv), 278 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, 279 WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0, 280 out_sidetone_tlv), 281 282 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL, 283 WM8991_ADC_HPF_ENA_BIT, 1, 0), 284 285 SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum), 286 287 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 288 WM8991_LEFT_ADC_DIGITAL_VOLUME, 289 WM8991_ADCL_VOL_SHIFT, 290 WM8991_ADCL_VOL_MASK, 291 0, 292 in_adc_tlv), 293 294 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 295 WM8991_RIGHT_ADC_DIGITAL_VOLUME, 296 WM8991_ADCR_VOL_SHIFT, 297 WM8991_ADCR_VOL_MASK, 298 0, 299 in_adc_tlv), 300 301 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 302 WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 303 WM8991_LIN12VOL_SHIFT, 304 WM8991_LIN12VOL_MASK, 305 0, 306 in_pga_tlv), 307 308 SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 309 WM8991_LI12ZC_BIT, 1, 0), 310 311 SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 312 WM8991_LI12MUTE_BIT, 1, 0), 313 314 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 315 WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 316 WM8991_LIN34VOL_SHIFT, 317 WM8991_LIN34VOL_MASK, 318 0, 319 in_pga_tlv), 320 321 SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 322 WM8991_LI34ZC_BIT, 1, 0), 323 324 SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 325 WM8991_LI34MUTE_BIT, 1, 0), 326 327 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 328 WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 329 WM8991_RIN12VOL_SHIFT, 330 WM8991_RIN12VOL_MASK, 331 0, 332 in_pga_tlv), 333 334 SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 335 WM8991_RI12ZC_BIT, 1, 0), 336 337 SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 338 WM8991_RI12MUTE_BIT, 1, 0), 339 340 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 341 WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 342 WM8991_RIN34VOL_SHIFT, 343 WM8991_RIN34VOL_MASK, 344 0, 345 in_pga_tlv), 346 347 SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 348 WM8991_RI34ZC_BIT, 1, 0), 349 350 SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 351 WM8991_RI34MUTE_BIT, 1, 0), 352 }; 353 354 /* 355 * _DAPM_ Controls 356 */ 357 static int outmixer_event(struct snd_soc_dapm_widget *w, 358 struct snd_kcontrol *kcontrol, int event) 359 { 360 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 361 u32 reg_shift = kcontrol->private_value & 0xfff; 362 int ret = 0; 363 u16 reg; 364 365 switch (reg_shift) { 366 case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8): 367 reg = snd_soc_component_read32(component, WM8991_OUTPUT_MIXER1); 368 if (reg & WM8991_LDLO) { 369 printk(KERN_WARNING 370 "Cannot set as Output Mixer 1 LDLO Set\n"); 371 ret = -1; 372 } 373 break; 374 375 case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8): 376 reg = snd_soc_component_read32(component, WM8991_OUTPUT_MIXER2); 377 if (reg & WM8991_RDRO) { 378 printk(KERN_WARNING 379 "Cannot set as Output Mixer 2 RDRO Set\n"); 380 ret = -1; 381 } 382 break; 383 384 case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8): 385 reg = snd_soc_component_read32(component, WM8991_SPEAKER_MIXER); 386 if (reg & WM8991_LDSPK) { 387 printk(KERN_WARNING 388 "Cannot set as Speaker Mixer LDSPK Set\n"); 389 ret = -1; 390 } 391 break; 392 393 case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8): 394 reg = snd_soc_component_read32(component, WM8991_SPEAKER_MIXER); 395 if (reg & WM8991_RDSPK) { 396 printk(KERN_WARNING 397 "Cannot set as Speaker Mixer RDSPK Set\n"); 398 ret = -1; 399 } 400 break; 401 } 402 403 return ret; 404 } 405 406 /* INMIX dB values */ 407 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_mix_tlv, -1200, 300, 1); 408 409 /* Left In PGA Connections */ 410 static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = { 411 SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0), 412 SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0), 413 }; 414 415 static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = { 416 SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0), 417 SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0), 418 }; 419 420 /* Right In PGA Connections */ 421 static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = { 422 SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0), 423 SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0), 424 }; 425 426 static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = { 427 SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0), 428 SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0), 429 }; 430 431 /* INMIXL */ 432 static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = { 433 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3, 434 WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv), 435 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT, 436 7, 0, in_mix_tlv), 437 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, 438 1, 0), 439 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, 440 1, 0), 441 }; 442 443 /* INMIXR */ 444 static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = { 445 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4, 446 WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv), 447 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT, 448 7, 0, in_mix_tlv), 449 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, 450 1, 0), 451 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, 452 1, 0), 453 }; 454 455 /* AINLMUX */ 456 static const char *wm8991_ainlmux[] = 457 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 458 459 static SOC_ENUM_SINGLE_DECL(wm8991_ainlmux_enum, 460 WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT, 461 wm8991_ainlmux); 462 463 static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls = 464 SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum); 465 466 /* DIFFINL */ 467 468 /* AINRMUX */ 469 static const char *wm8991_ainrmux[] = 470 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 471 472 static SOC_ENUM_SINGLE_DECL(wm8991_ainrmux_enum, 473 WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT, 474 wm8991_ainrmux); 475 476 static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls = 477 SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum); 478 479 /* RXVOICE */ 480 static const struct snd_kcontrol_new wm8991_dapm_rxvoice_controls[] = { 481 SOC_DAPM_SINGLE_TLV("LIN4RXN", WM8991_INPUT_MIXER5, WM8991_LR4BVOL_SHIFT, 482 WM8991_LR4BVOL_MASK, 0, in_mix_tlv), 483 SOC_DAPM_SINGLE_TLV("RIN4RXP", WM8991_INPUT_MIXER6, WM8991_RL4BVOL_SHIFT, 484 WM8991_RL4BVOL_MASK, 0, in_mix_tlv), 485 }; 486 487 /* LOMIX */ 488 static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = { 489 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1, 490 WM8991_LRBLO_BIT, 1, 0), 491 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1, 492 WM8991_LLBLO_BIT, 1, 0), 493 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, 494 WM8991_LRI3LO_BIT, 1, 0), 495 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, 496 WM8991_LLI3LO_BIT, 1, 0), 497 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, 498 WM8991_LR12LO_BIT, 1, 0), 499 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, 500 WM8991_LL12LO_BIT, 1, 0), 501 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1, 502 WM8991_LDLO_BIT, 1, 0), 503 }; 504 505 /* ROMIX */ 506 static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = { 507 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2, 508 WM8991_RLBRO_BIT, 1, 0), 509 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2, 510 WM8991_RRBRO_BIT, 1, 0), 511 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, 512 WM8991_RLI3RO_BIT, 1, 0), 513 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, 514 WM8991_RRI3RO_BIT, 1, 0), 515 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, 516 WM8991_RL12RO_BIT, 1, 0), 517 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, 518 WM8991_RR12RO_BIT, 1, 0), 519 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2, 520 WM8991_RDRO_BIT, 1, 0), 521 }; 522 523 /* LONMIX */ 524 static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = { 525 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, 526 WM8991_LLOPGALON_BIT, 1, 0), 527 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1, 528 WM8991_LROPGALON_BIT, 1, 0), 529 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1, 530 WM8991_LOPLON_BIT, 1, 0), 531 }; 532 533 /* LOPMIX */ 534 static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = { 535 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1, 536 WM8991_LR12LOP_BIT, 1, 0), 537 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1, 538 WM8991_LL12LOP_BIT, 1, 0), 539 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, 540 WM8991_LLOPGALOP_BIT, 1, 0), 541 }; 542 543 /* RONMIX */ 544 static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = { 545 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, 546 WM8991_RROPGARON_BIT, 1, 0), 547 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2, 548 WM8991_RLOPGARON_BIT, 1, 0), 549 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2, 550 WM8991_ROPRON_BIT, 1, 0), 551 }; 552 553 /* ROPMIX */ 554 static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = { 555 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2, 556 WM8991_RL12ROP_BIT, 1, 0), 557 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2, 558 WM8991_RR12ROP_BIT, 1, 0), 559 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, 560 WM8991_RROPGAROP_BIT, 1, 0), 561 }; 562 563 /* OUT3MIX */ 564 static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = { 565 SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER, 566 WM8991_LI4O3_BIT, 1, 0), 567 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER, 568 WM8991_LPGAO3_BIT, 1, 0), 569 }; 570 571 /* OUT4MIX */ 572 static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = { 573 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER, 574 WM8991_RPGAO4_BIT, 1, 0), 575 SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER, 576 WM8991_RI4O4_BIT, 1, 0), 577 }; 578 579 /* SPKMIX */ 580 static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = { 581 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER, 582 WM8991_LI2SPK_BIT, 1, 0), 583 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER, 584 WM8991_LB2SPK_BIT, 1, 0), 585 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER, 586 WM8991_LOPGASPK_BIT, 1, 0), 587 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER, 588 WM8991_LDSPK_BIT, 1, 0), 589 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER, 590 WM8991_RDSPK_BIT, 1, 0), 591 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER, 592 WM8991_ROPGASPK_BIT, 1, 0), 593 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER, 594 WM8991_RL12ROP_BIT, 1, 0), 595 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER, 596 WM8991_RI2SPK_BIT, 1, 0), 597 }; 598 599 static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = { 600 /* Input Side */ 601 /* Input Lines */ 602 SND_SOC_DAPM_INPUT("LIN1"), 603 SND_SOC_DAPM_INPUT("LIN2"), 604 SND_SOC_DAPM_INPUT("LIN3"), 605 SND_SOC_DAPM_INPUT("LIN4RXN"), 606 SND_SOC_DAPM_INPUT("RIN3"), 607 SND_SOC_DAPM_INPUT("RIN4RXP"), 608 SND_SOC_DAPM_INPUT("RIN1"), 609 SND_SOC_DAPM_INPUT("RIN2"), 610 SND_SOC_DAPM_INPUT("Internal ADC Source"), 611 612 SND_SOC_DAPM_SUPPLY("INL", WM8991_POWER_MANAGEMENT_2, 613 WM8991_AINL_ENA_BIT, 0, NULL, 0), 614 SND_SOC_DAPM_SUPPLY("INR", WM8991_POWER_MANAGEMENT_2, 615 WM8991_AINR_ENA_BIT, 0, NULL, 0), 616 617 /* DACs */ 618 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2, 619 WM8991_ADCL_ENA_BIT, 0), 620 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2, 621 WM8991_ADCR_ENA_BIT, 0), 622 623 /* Input PGAs */ 624 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT, 625 0, &wm8991_dapm_lin12_pga_controls[0], 626 ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)), 627 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT, 628 0, &wm8991_dapm_lin34_pga_controls[0], 629 ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)), 630 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT, 631 0, &wm8991_dapm_rin12_pga_controls[0], 632 ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)), 633 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT, 634 0, &wm8991_dapm_rin34_pga_controls[0], 635 ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)), 636 637 /* INMIXL */ 638 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0, 639 &wm8991_dapm_inmixl_controls[0], 640 ARRAY_SIZE(wm8991_dapm_inmixl_controls)), 641 642 /* AINLMUX */ 643 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, 644 &wm8991_dapm_ainlmux_controls), 645 646 /* INMIXR */ 647 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0, 648 &wm8991_dapm_inmixr_controls[0], 649 ARRAY_SIZE(wm8991_dapm_inmixr_controls)), 650 651 /* AINRMUX */ 652 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, 653 &wm8991_dapm_ainrmux_controls), 654 655 /* Output Side */ 656 /* DACs */ 657 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3, 658 WM8991_DACL_ENA_BIT, 0), 659 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3, 660 WM8991_DACR_ENA_BIT, 0), 661 662 /* LOMIX */ 663 SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT, 664 0, &wm8991_dapm_lomix_controls[0], 665 ARRAY_SIZE(wm8991_dapm_lomix_controls), 666 outmixer_event, SND_SOC_DAPM_PRE_REG), 667 668 /* LONMIX */ 669 SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0, 670 &wm8991_dapm_lonmix_controls[0], 671 ARRAY_SIZE(wm8991_dapm_lonmix_controls)), 672 673 /* LOPMIX */ 674 SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0, 675 &wm8991_dapm_lopmix_controls[0], 676 ARRAY_SIZE(wm8991_dapm_lopmix_controls)), 677 678 /* OUT3MIX */ 679 SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0, 680 &wm8991_dapm_out3mix_controls[0], 681 ARRAY_SIZE(wm8991_dapm_out3mix_controls)), 682 683 /* SPKMIX */ 684 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0, 685 &wm8991_dapm_spkmix_controls[0], 686 ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event, 687 SND_SOC_DAPM_PRE_REG), 688 689 /* OUT4MIX */ 690 SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0, 691 &wm8991_dapm_out4mix_controls[0], 692 ARRAY_SIZE(wm8991_dapm_out4mix_controls)), 693 694 /* ROPMIX */ 695 SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0, 696 &wm8991_dapm_ropmix_controls[0], 697 ARRAY_SIZE(wm8991_dapm_ropmix_controls)), 698 699 /* RONMIX */ 700 SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0, 701 &wm8991_dapm_ronmix_controls[0], 702 ARRAY_SIZE(wm8991_dapm_ronmix_controls)), 703 704 /* ROMIX */ 705 SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT, 706 0, &wm8991_dapm_romix_controls[0], 707 ARRAY_SIZE(wm8991_dapm_romix_controls), 708 outmixer_event, SND_SOC_DAPM_PRE_REG), 709 710 /* LOUT PGA */ 711 SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0, 712 NULL, 0), 713 714 /* ROUT PGA */ 715 SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0, 716 NULL, 0), 717 718 /* LOPGA */ 719 SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0, 720 NULL, 0), 721 722 /* ROPGA */ 723 SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0, 724 NULL, 0), 725 726 /* MICBIAS */ 727 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8991_POWER_MANAGEMENT_1, 728 WM8991_MICBIAS_ENA_BIT, 0, NULL, 0), 729 730 SND_SOC_DAPM_OUTPUT("LON"), 731 SND_SOC_DAPM_OUTPUT("LOP"), 732 SND_SOC_DAPM_OUTPUT("OUT3"), 733 SND_SOC_DAPM_OUTPUT("LOUT"), 734 SND_SOC_DAPM_OUTPUT("SPKN"), 735 SND_SOC_DAPM_OUTPUT("SPKP"), 736 SND_SOC_DAPM_OUTPUT("ROUT"), 737 SND_SOC_DAPM_OUTPUT("OUT4"), 738 SND_SOC_DAPM_OUTPUT("ROP"), 739 SND_SOC_DAPM_OUTPUT("RON"), 740 SND_SOC_DAPM_OUTPUT("OUT"), 741 742 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 743 }; 744 745 static const struct snd_soc_dapm_route wm8991_dapm_routes[] = { 746 /* Make DACs turn on when playing even if not mixed into any outputs */ 747 {"Internal DAC Sink", NULL, "Left DAC"}, 748 {"Internal DAC Sink", NULL, "Right DAC"}, 749 750 /* Make ADCs turn on when recording even if not mixed from any inputs */ 751 {"Left ADC", NULL, "Internal ADC Source"}, 752 {"Right ADC", NULL, "Internal ADC Source"}, 753 754 /* Input Side */ 755 {"INMIXL", NULL, "INL"}, 756 {"AINLMUX", NULL, "INL"}, 757 {"INMIXR", NULL, "INR"}, 758 {"AINRMUX", NULL, "INR"}, 759 /* LIN12 PGA */ 760 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 761 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 762 /* LIN34 PGA */ 763 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 764 {"LIN34 PGA", "LIN4 Switch", "LIN4RXN"}, 765 /* INMIXL */ 766 {"INMIXL", "Record Left Volume", "LOMIX"}, 767 {"INMIXL", "LIN2 Volume", "LIN2"}, 768 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 769 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 770 /* AINLMUX */ 771 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 772 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 773 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 774 {"AINLMUX", "RXVOICE Mix", "LIN4RXN"}, 775 {"AINLMUX", "RXVOICE Mix", "RIN4RXP"}, 776 /* ADC */ 777 {"Left ADC", NULL, "AINLMUX"}, 778 779 /* RIN12 PGA */ 780 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 781 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 782 /* RIN34 PGA */ 783 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 784 {"RIN34 PGA", "RIN4 Switch", "RIN4RXP"}, 785 /* INMIXL */ 786 {"INMIXR", "Record Right Volume", "ROMIX"}, 787 {"INMIXR", "RIN2 Volume", "RIN2"}, 788 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 789 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 790 /* AINRMUX */ 791 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 792 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 793 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 794 {"AINRMUX", "RXVOICE Mix", "LIN4RXN"}, 795 {"AINRMUX", "RXVOICE Mix", "RIN4RXP"}, 796 /* ADC */ 797 {"Right ADC", NULL, "AINRMUX"}, 798 799 /* LOMIX */ 800 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 801 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 802 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 803 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 804 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 805 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 806 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 807 808 /* ROMIX */ 809 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 810 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 811 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 812 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 813 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 814 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 815 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 816 817 /* SPKMIX */ 818 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 819 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 820 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 821 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 822 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 823 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 824 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 825 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, 826 827 /* LONMIX */ 828 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 829 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 830 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 831 832 /* LOPMIX */ 833 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 834 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 835 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 836 837 /* OUT3MIX */ 838 {"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"}, 839 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 840 841 /* OUT4MIX */ 842 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 843 {"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"}, 844 845 /* RONMIX */ 846 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 847 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 848 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 849 850 /* ROPMIX */ 851 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 852 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 853 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 854 855 /* Out Mixer PGAs */ 856 {"LOPGA", NULL, "LOMIX"}, 857 {"ROPGA", NULL, "ROMIX"}, 858 859 {"LOUT PGA", NULL, "LOMIX"}, 860 {"ROUT PGA", NULL, "ROMIX"}, 861 862 /* Output Pins */ 863 {"LON", NULL, "LONMIX"}, 864 {"LOP", NULL, "LOPMIX"}, 865 {"OUT", NULL, "OUT3MIX"}, 866 {"LOUT", NULL, "LOUT PGA"}, 867 {"SPKN", NULL, "SPKMIX"}, 868 {"ROUT", NULL, "ROUT PGA"}, 869 {"OUT4", NULL, "OUT4MIX"}, 870 {"ROP", NULL, "ROPMIX"}, 871 {"RON", NULL, "RONMIX"}, 872 }; 873 874 /* PLL divisors */ 875 struct _pll_div { 876 u32 div2; 877 u32 n; 878 u32 k; 879 }; 880 881 /* The size in bits of the pll divide multiplied by 10 882 * to allow rounding later */ 883 #define FIXED_PLL_SIZE ((1 << 16) * 10) 884 885 static void pll_factors(struct _pll_div *pll_div, unsigned int target, 886 unsigned int source) 887 { 888 u64 Kpart; 889 unsigned int K, Ndiv, Nmod; 890 891 892 Ndiv = target / source; 893 if (Ndiv < 6) { 894 source >>= 1; 895 pll_div->div2 = 1; 896 Ndiv = target / source; 897 } else 898 pll_div->div2 = 0; 899 900 if ((Ndiv < 6) || (Ndiv > 12)) 901 printk(KERN_WARNING 902 "WM8991 N value outwith recommended range! N = %d\n", Ndiv); 903 904 pll_div->n = Ndiv; 905 Nmod = target % source; 906 Kpart = FIXED_PLL_SIZE * (long long)Nmod; 907 908 do_div(Kpart, source); 909 910 K = Kpart & 0xFFFFFFFF; 911 912 /* Check if we need to round */ 913 if ((K % 10) >= 5) 914 K += 5; 915 916 /* Move down to proper range now rounding is done */ 917 K /= 10; 918 919 pll_div->k = K; 920 } 921 922 static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai, 923 int pll_id, int src, unsigned int freq_in, unsigned int freq_out) 924 { 925 u16 reg; 926 struct snd_soc_component *component = codec_dai->component; 927 struct _pll_div pll_div; 928 929 if (freq_in && freq_out) { 930 pll_factors(&pll_div, freq_out * 4, freq_in); 931 932 /* Turn on PLL */ 933 reg = snd_soc_component_read32(component, WM8991_POWER_MANAGEMENT_2); 934 reg |= WM8991_PLL_ENA; 935 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg); 936 937 /* sysclk comes from PLL */ 938 reg = snd_soc_component_read32(component, WM8991_CLOCKING_2); 939 snd_soc_component_write(component, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC); 940 941 /* set up N , fractional mode and pre-divisor if necessary */ 942 snd_soc_component_write(component, WM8991_PLL1, pll_div.n | WM8991_SDM | 943 (pll_div.div2 ? WM8991_PRESCALE : 0)); 944 snd_soc_component_write(component, WM8991_PLL2, (u8)(pll_div.k>>8)); 945 snd_soc_component_write(component, WM8991_PLL3, (u8)(pll_div.k & 0xFF)); 946 } else { 947 /* Turn on PLL */ 948 reg = snd_soc_component_read32(component, WM8991_POWER_MANAGEMENT_2); 949 reg &= ~WM8991_PLL_ENA; 950 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg); 951 } 952 return 0; 953 } 954 955 /* 956 * Set's ADC and Voice DAC format. 957 */ 958 static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai, 959 unsigned int fmt) 960 { 961 struct snd_soc_component *component = codec_dai->component; 962 u16 audio1, audio3; 963 964 audio1 = snd_soc_component_read32(component, WM8991_AUDIO_INTERFACE_1); 965 audio3 = snd_soc_component_read32(component, WM8991_AUDIO_INTERFACE_3); 966 967 /* set master/slave audio interface */ 968 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 969 case SND_SOC_DAIFMT_CBS_CFS: 970 audio3 &= ~WM8991_AIF_MSTR1; 971 break; 972 case SND_SOC_DAIFMT_CBM_CFM: 973 audio3 |= WM8991_AIF_MSTR1; 974 break; 975 default: 976 return -EINVAL; 977 } 978 979 audio1 &= ~WM8991_AIF_FMT_MASK; 980 981 /* interface format */ 982 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 983 case SND_SOC_DAIFMT_I2S: 984 audio1 |= WM8991_AIF_TMF_I2S; 985 audio1 &= ~WM8991_AIF_LRCLK_INV; 986 break; 987 case SND_SOC_DAIFMT_RIGHT_J: 988 audio1 |= WM8991_AIF_TMF_RIGHTJ; 989 audio1 &= ~WM8991_AIF_LRCLK_INV; 990 break; 991 case SND_SOC_DAIFMT_LEFT_J: 992 audio1 |= WM8991_AIF_TMF_LEFTJ; 993 audio1 &= ~WM8991_AIF_LRCLK_INV; 994 break; 995 case SND_SOC_DAIFMT_DSP_A: 996 audio1 |= WM8991_AIF_TMF_DSP; 997 audio1 &= ~WM8991_AIF_LRCLK_INV; 998 break; 999 case SND_SOC_DAIFMT_DSP_B: 1000 audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV; 1001 break; 1002 default: 1003 return -EINVAL; 1004 } 1005 1006 snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_1, audio1); 1007 snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_3, audio3); 1008 return 0; 1009 } 1010 1011 static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1012 int div_id, int div) 1013 { 1014 struct snd_soc_component *component = codec_dai->component; 1015 u16 reg; 1016 1017 switch (div_id) { 1018 case WM8991_MCLK_DIV: 1019 reg = snd_soc_component_read32(component, WM8991_CLOCKING_2) & 1020 ~WM8991_MCLK_DIV_MASK; 1021 snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); 1022 break; 1023 case WM8991_DACCLK_DIV: 1024 reg = snd_soc_component_read32(component, WM8991_CLOCKING_2) & 1025 ~WM8991_DAC_CLKDIV_MASK; 1026 snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); 1027 break; 1028 case WM8991_ADCCLK_DIV: 1029 reg = snd_soc_component_read32(component, WM8991_CLOCKING_2) & 1030 ~WM8991_ADC_CLKDIV_MASK; 1031 snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); 1032 break; 1033 case WM8991_BCLK_DIV: 1034 reg = snd_soc_component_read32(component, WM8991_CLOCKING_1) & 1035 ~WM8991_BCLK_DIV_MASK; 1036 snd_soc_component_write(component, WM8991_CLOCKING_1, reg | div); 1037 break; 1038 default: 1039 return -EINVAL; 1040 } 1041 1042 return 0; 1043 } 1044 1045 /* 1046 * Set PCM DAI bit size and sample rate. 1047 */ 1048 static int wm8991_hw_params(struct snd_pcm_substream *substream, 1049 struct snd_pcm_hw_params *params, 1050 struct snd_soc_dai *dai) 1051 { 1052 struct snd_soc_component *component = dai->component; 1053 u16 audio1 = snd_soc_component_read32(component, WM8991_AUDIO_INTERFACE_1); 1054 1055 audio1 &= ~WM8991_AIF_WL_MASK; 1056 /* bit size */ 1057 switch (params_width(params)) { 1058 case 16: 1059 break; 1060 case 20: 1061 audio1 |= WM8991_AIF_WL_20BITS; 1062 break; 1063 case 24: 1064 audio1 |= WM8991_AIF_WL_24BITS; 1065 break; 1066 case 32: 1067 audio1 |= WM8991_AIF_WL_32BITS; 1068 break; 1069 } 1070 1071 snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_1, audio1); 1072 return 0; 1073 } 1074 1075 static int wm8991_mute(struct snd_soc_dai *dai, int mute) 1076 { 1077 struct snd_soc_component *component = dai->component; 1078 u16 val; 1079 1080 val = snd_soc_component_read32(component, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE; 1081 if (mute) 1082 snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); 1083 else 1084 snd_soc_component_write(component, WM8991_DAC_CTRL, val); 1085 return 0; 1086 } 1087 1088 static int wm8991_set_bias_level(struct snd_soc_component *component, 1089 enum snd_soc_bias_level level) 1090 { 1091 struct wm8991_priv *wm8991 = snd_soc_component_get_drvdata(component); 1092 u16 val; 1093 1094 switch (level) { 1095 case SND_SOC_BIAS_ON: 1096 break; 1097 1098 case SND_SOC_BIAS_PREPARE: 1099 /* VMID=2*50k */ 1100 val = snd_soc_component_read32(component, WM8991_POWER_MANAGEMENT_1) & 1101 ~WM8991_VMID_MODE_MASK; 1102 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x2); 1103 break; 1104 1105 case SND_SOC_BIAS_STANDBY: 1106 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1107 regcache_sync(wm8991->regmap); 1108 /* Enable all output discharge bits */ 1109 snd_soc_component_write(component, WM8991_ANTIPOP1, WM8991_DIS_LLINE | 1110 WM8991_DIS_RLINE | WM8991_DIS_OUT3 | 1111 WM8991_DIS_OUT4 | WM8991_DIS_LOUT | 1112 WM8991_DIS_ROUT); 1113 1114 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1115 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1116 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1117 WM8991_VMIDTOG); 1118 1119 /* Delay to allow output caps to discharge */ 1120 msleep(300); 1121 1122 /* Disable VMIDTOG */ 1123 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1124 WM8991_BUFDCOPEN | WM8991_POBCTRL); 1125 1126 /* disable all output discharge bits */ 1127 snd_soc_component_write(component, WM8991_ANTIPOP1, 0); 1128 1129 /* Enable outputs */ 1130 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1b00); 1131 1132 msleep(50); 1133 1134 /* Enable VMID at 2x50k */ 1135 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f02); 1136 1137 msleep(100); 1138 1139 /* Enable VREF */ 1140 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f03); 1141 1142 msleep(600); 1143 1144 /* Enable BUFIOEN */ 1145 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1146 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1147 WM8991_BUFIOEN); 1148 1149 /* Disable outputs */ 1150 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x3); 1151 1152 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1153 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_BUFIOEN); 1154 } 1155 1156 /* VMID=2*250k */ 1157 val = snd_soc_component_read32(component, WM8991_POWER_MANAGEMENT_1) & 1158 ~WM8991_VMID_MODE_MASK; 1159 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x4); 1160 break; 1161 1162 case SND_SOC_BIAS_OFF: 1163 /* Enable POBCTRL and SOFT_ST */ 1164 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1165 WM8991_POBCTRL | WM8991_BUFIOEN); 1166 1167 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1168 snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST | 1169 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1170 WM8991_BUFIOEN); 1171 1172 /* mute DAC */ 1173 val = snd_soc_component_read32(component, WM8991_DAC_CTRL); 1174 snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); 1175 1176 /* Enable any disabled outputs */ 1177 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f03); 1178 1179 /* Disable VMID */ 1180 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f01); 1181 1182 msleep(300); 1183 1184 /* Enable all output discharge bits */ 1185 snd_soc_component_write(component, WM8991_ANTIPOP1, WM8991_DIS_LLINE | 1186 WM8991_DIS_RLINE | WM8991_DIS_OUT3 | 1187 WM8991_DIS_OUT4 | WM8991_DIS_LOUT | 1188 WM8991_DIS_ROUT); 1189 1190 /* Disable VREF */ 1191 snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x0); 1192 1193 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1194 snd_soc_component_write(component, WM8991_ANTIPOP2, 0x0); 1195 regcache_mark_dirty(wm8991->regmap); 1196 break; 1197 } 1198 1199 return 0; 1200 } 1201 1202 #define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1203 SNDRV_PCM_FMTBIT_S24_LE) 1204 1205 static const struct snd_soc_dai_ops wm8991_ops = { 1206 .hw_params = wm8991_hw_params, 1207 .digital_mute = wm8991_mute, 1208 .set_fmt = wm8991_set_dai_fmt, 1209 .set_clkdiv = wm8991_set_dai_clkdiv, 1210 .set_pll = wm8991_set_dai_pll 1211 }; 1212 1213 /* 1214 * The WM8991 supports 2 different and mutually exclusive DAI 1215 * configurations. 1216 * 1217 * 1. ADC/DAC on Primary Interface 1218 * 2. ADC on Primary Interface/DAC on secondary 1219 */ 1220 static struct snd_soc_dai_driver wm8991_dai = { 1221 /* ADC/DAC on primary */ 1222 .name = "wm8991", 1223 .id = 1, 1224 .playback = { 1225 .stream_name = "Playback", 1226 .channels_min = 1, 1227 .channels_max = 2, 1228 .rates = SNDRV_PCM_RATE_8000_96000, 1229 .formats = WM8991_FORMATS 1230 }, 1231 .capture = { 1232 .stream_name = "Capture", 1233 .channels_min = 1, 1234 .channels_max = 2, 1235 .rates = SNDRV_PCM_RATE_8000_96000, 1236 .formats = WM8991_FORMATS 1237 }, 1238 .ops = &wm8991_ops 1239 }; 1240 1241 static const struct snd_soc_component_driver soc_component_dev_wm8991 = { 1242 .set_bias_level = wm8991_set_bias_level, 1243 .controls = wm8991_snd_controls, 1244 .num_controls = ARRAY_SIZE(wm8991_snd_controls), 1245 .dapm_widgets = wm8991_dapm_widgets, 1246 .num_dapm_widgets = ARRAY_SIZE(wm8991_dapm_widgets), 1247 .dapm_routes = wm8991_dapm_routes, 1248 .num_dapm_routes = ARRAY_SIZE(wm8991_dapm_routes), 1249 .suspend_bias_off = 1, 1250 .idle_bias_on = 1, 1251 .use_pmdown_time = 1, 1252 .endianness = 1, 1253 .non_legacy_dai_naming = 1, 1254 }; 1255 1256 static const struct regmap_config wm8991_regmap = { 1257 .reg_bits = 8, 1258 .val_bits = 16, 1259 1260 .max_register = WM8991_PLL3, 1261 .volatile_reg = wm8991_volatile, 1262 .reg_defaults = wm8991_reg_defaults, 1263 .num_reg_defaults = ARRAY_SIZE(wm8991_reg_defaults), 1264 .cache_type = REGCACHE_RBTREE, 1265 }; 1266 1267 static int wm8991_i2c_probe(struct i2c_client *i2c, 1268 const struct i2c_device_id *id) 1269 { 1270 struct wm8991_priv *wm8991; 1271 unsigned int val; 1272 int ret; 1273 1274 wm8991 = devm_kzalloc(&i2c->dev, sizeof(*wm8991), GFP_KERNEL); 1275 if (!wm8991) 1276 return -ENOMEM; 1277 1278 wm8991->regmap = devm_regmap_init_i2c(i2c, &wm8991_regmap); 1279 if (IS_ERR(wm8991->regmap)) 1280 return PTR_ERR(wm8991->regmap); 1281 1282 i2c_set_clientdata(i2c, wm8991); 1283 1284 ret = regmap_read(wm8991->regmap, WM8991_RESET, &val); 1285 if (ret != 0) { 1286 dev_err(&i2c->dev, "Failed to read device ID: %d\n", ret); 1287 return ret; 1288 } 1289 if (val != 0x8991) { 1290 dev_err(&i2c->dev, "Device with ID %x is not a WM8991\n", val); 1291 return -EINVAL; 1292 } 1293 1294 ret = regmap_write(wm8991->regmap, WM8991_RESET, 0); 1295 if (ret < 0) { 1296 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 1297 return ret; 1298 } 1299 1300 regmap_update_bits(wm8991->regmap, WM8991_AUDIO_INTERFACE_4, 1301 WM8991_ALRCGPIO1, WM8991_ALRCGPIO1); 1302 1303 regmap_update_bits(wm8991->regmap, WM8991_GPIO1_GPIO2, 1304 WM8991_GPIO1_SEL_MASK, 1); 1305 1306 regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_1, 1307 WM8991_VREF_ENA | WM8991_VMID_MODE_MASK, 1308 WM8991_VREF_ENA | WM8991_VMID_MODE_MASK); 1309 1310 regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_2, 1311 WM8991_OPCLK_ENA, WM8991_OPCLK_ENA); 1312 1313 regmap_write(wm8991->regmap, WM8991_DAC_CTRL, 0); 1314 regmap_write(wm8991->regmap, WM8991_LEFT_OUTPUT_VOLUME, 1315 0x50 | (1<<8)); 1316 regmap_write(wm8991->regmap, WM8991_RIGHT_OUTPUT_VOLUME, 1317 0x50 | (1<<8)); 1318 1319 ret = devm_snd_soc_register_component(&i2c->dev, 1320 &soc_component_dev_wm8991, &wm8991_dai, 1); 1321 1322 return ret; 1323 } 1324 1325 static const struct i2c_device_id wm8991_i2c_id[] = { 1326 { "wm8991", 0 }, 1327 { } 1328 }; 1329 MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id); 1330 1331 static struct i2c_driver wm8991_i2c_driver = { 1332 .driver = { 1333 .name = "wm8991", 1334 }, 1335 .probe = wm8991_i2c_probe, 1336 .id_table = wm8991_i2c_id, 1337 }; 1338 1339 module_i2c_driver(wm8991_i2c_driver); 1340 1341 MODULE_DESCRIPTION("ASoC WM8991 driver"); 1342 MODULE_AUTHOR("Graeme Gregory"); 1343 MODULE_LICENSE("GPL"); 1344