1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * An RTC driver for the NVIDIA Tegra 200 series internal RTC. 4 * 5 * Copyright (c) 2010, NVIDIA Corporation. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/irq.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/rtc.h> 19 #include <linux/slab.h> 20 21 /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */ 22 #define TEGRA_RTC_REG_BUSY 0x004 23 #define TEGRA_RTC_REG_SECONDS 0x008 24 /* when msec is read, the seconds are buffered into shadow seconds. */ 25 #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c 26 #define TEGRA_RTC_REG_MILLI_SECONDS 0x010 27 #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014 28 #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018 29 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c 30 #define TEGRA_RTC_REG_INTR_MASK 0x028 31 /* write 1 bits to clear status bits */ 32 #define TEGRA_RTC_REG_INTR_STATUS 0x02c 33 34 /* bits in INTR_MASK */ 35 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4) 36 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3) 37 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2) 38 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1) 39 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0) 40 41 /* bits in INTR_STATUS */ 42 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4) 43 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3) 44 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2) 45 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1) 46 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0) 47 48 struct tegra_rtc_info { 49 struct platform_device *pdev; 50 struct rtc_device *rtc_dev; 51 void __iomem *rtc_base; /* NULL if not initialized. */ 52 struct clk *clk; 53 int tegra_rtc_irq; /* alarm and periodic irq */ 54 spinlock_t tegra_rtc_lock; 55 }; 56 57 /* RTC hardware is busy when it is updating its values over AHB once 58 * every eight 32kHz clocks (~250uS). 59 * outside of these updates the CPU is free to write. 60 * CPU is always free to read. 61 */ 62 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info) 63 { 64 return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1; 65 } 66 67 /* Wait for hardware to be ready for writing. 68 * This function tries to maximize the amount of time before the next update. 69 * It does this by waiting for the RTC to become busy with its periodic update, 70 * then returning once the RTC first becomes not busy. 71 * This periodic update (where the seconds and milliseconds are copied to the 72 * AHB side) occurs every eight 32kHz clocks (~250uS). 73 * The behavior of this function allows us to make some assumptions without 74 * introducing a race, because 250uS is plenty of time to read/write a value. 75 */ 76 static int tegra_rtc_wait_while_busy(struct device *dev) 77 { 78 struct tegra_rtc_info *info = dev_get_drvdata(dev); 79 80 int retries = 500; /* ~490 us is the worst case, ~250 us is best. */ 81 82 /* first wait for the RTC to become busy. this is when it 83 * posts its updated seconds+msec registers to AHB side. */ 84 while (tegra_rtc_check_busy(info)) { 85 if (!retries--) 86 goto retry_failed; 87 udelay(1); 88 } 89 90 /* now we have about 250 us to manipulate registers */ 91 return 0; 92 93 retry_failed: 94 dev_err(dev, "write failed:retry count exceeded.\n"); 95 return -ETIMEDOUT; 96 } 97 98 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm) 99 { 100 struct tegra_rtc_info *info = dev_get_drvdata(dev); 101 unsigned long sec, msec; 102 unsigned long sl_irq_flags; 103 104 /* RTC hardware copies seconds to shadow seconds when a read 105 * of milliseconds occurs. use a lock to keep other threads out. */ 106 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); 107 108 msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS); 109 sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS); 110 111 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); 112 113 rtc_time64_to_tm(sec, tm); 114 115 dev_vdbg(dev, "time read as %lu. %ptR\n", sec, tm); 116 117 return 0; 118 } 119 120 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm) 121 { 122 struct tegra_rtc_info *info = dev_get_drvdata(dev); 123 unsigned long sec; 124 int ret; 125 126 /* convert tm to seconds. */ 127 sec = rtc_tm_to_time64(tm); 128 129 dev_vdbg(dev, "time set to %lu. %ptR\n", sec, tm); 130 131 /* seconds only written if wait succeeded. */ 132 ret = tegra_rtc_wait_while_busy(dev); 133 if (!ret) 134 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS); 135 136 dev_vdbg(dev, "time read back as %d\n", 137 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS)); 138 139 return ret; 140 } 141 142 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 143 { 144 struct tegra_rtc_info *info = dev_get_drvdata(dev); 145 unsigned long sec; 146 unsigned tmp; 147 148 sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); 149 150 if (sec == 0) { 151 /* alarm is disabled. */ 152 alarm->enabled = 0; 153 } else { 154 /* alarm is enabled. */ 155 alarm->enabled = 1; 156 rtc_time64_to_tm(sec, &alarm->time); 157 } 158 159 tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 160 alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0; 161 162 return 0; 163 } 164 165 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 166 { 167 struct tegra_rtc_info *info = dev_get_drvdata(dev); 168 unsigned status; 169 unsigned long sl_irq_flags; 170 171 tegra_rtc_wait_while_busy(dev); 172 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); 173 174 /* read the original value, and OR in the flag. */ 175 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 176 if (enabled) 177 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */ 178 else 179 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */ 180 181 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 182 183 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); 184 185 return 0; 186 } 187 188 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 189 { 190 struct tegra_rtc_info *info = dev_get_drvdata(dev); 191 unsigned long sec; 192 193 if (alarm->enabled) 194 sec = rtc_tm_to_time64(&alarm->time); 195 else 196 sec = 0; 197 198 tegra_rtc_wait_while_busy(dev); 199 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); 200 dev_vdbg(dev, "alarm read back as %d\n", 201 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); 202 203 /* if successfully written and alarm is enabled ... */ 204 if (sec) { 205 tegra_rtc_alarm_irq_enable(dev, 1); 206 dev_vdbg(dev, "alarm set as %lu. %ptR\n", sec, &alarm->time); 207 } else { 208 /* disable alarm if 0 or write error. */ 209 dev_vdbg(dev, "alarm disabled\n"); 210 tegra_rtc_alarm_irq_enable(dev, 0); 211 } 212 213 return 0; 214 } 215 216 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq) 217 { 218 if (!dev || !dev->driver) 219 return 0; 220 221 seq_printf(seq, "name\t\t: %s\n", dev_name(dev)); 222 223 return 0; 224 } 225 226 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data) 227 { 228 struct device *dev = data; 229 struct tegra_rtc_info *info = dev_get_drvdata(dev); 230 unsigned long events = 0; 231 unsigned status; 232 unsigned long sl_irq_flags; 233 234 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 235 if (status) { 236 /* clear the interrupt masks and status on any irq. */ 237 tegra_rtc_wait_while_busy(dev); 238 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); 239 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 240 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 241 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); 242 } 243 244 /* check if Alarm */ 245 if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)) 246 events |= RTC_IRQF | RTC_AF; 247 248 /* check if Periodic */ 249 if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)) 250 events |= RTC_IRQF | RTC_PF; 251 252 rtc_update_irq(info->rtc_dev, 1, events); 253 254 return IRQ_HANDLED; 255 } 256 257 static const struct rtc_class_ops tegra_rtc_ops = { 258 .read_time = tegra_rtc_read_time, 259 .set_time = tegra_rtc_set_time, 260 .read_alarm = tegra_rtc_read_alarm, 261 .set_alarm = tegra_rtc_set_alarm, 262 .proc = tegra_rtc_proc, 263 .alarm_irq_enable = tegra_rtc_alarm_irq_enable, 264 }; 265 266 static const struct of_device_id tegra_rtc_dt_match[] = { 267 { .compatible = "nvidia,tegra20-rtc", }, 268 {} 269 }; 270 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match); 271 272 static int __init tegra_rtc_probe(struct platform_device *pdev) 273 { 274 struct tegra_rtc_info *info; 275 struct resource *res; 276 int ret; 277 278 info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info), 279 GFP_KERNEL); 280 if (!info) 281 return -ENOMEM; 282 283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 284 info->rtc_base = devm_ioremap_resource(&pdev->dev, res); 285 if (IS_ERR(info->rtc_base)) 286 return PTR_ERR(info->rtc_base); 287 288 ret = platform_get_irq(pdev, 0); 289 if (ret <= 0) { 290 dev_err(&pdev->dev, "failed to get platform IRQ: %d\n", ret); 291 return ret; 292 } 293 294 info->tegra_rtc_irq = ret; 295 296 info->rtc_dev = devm_rtc_allocate_device(&pdev->dev); 297 if (IS_ERR(info->rtc_dev)) 298 return PTR_ERR(info->rtc_dev); 299 300 info->rtc_dev->ops = &tegra_rtc_ops; 301 info->rtc_dev->range_max = U32_MAX; 302 303 info->clk = devm_clk_get(&pdev->dev, NULL); 304 if (IS_ERR(info->clk)) 305 return PTR_ERR(info->clk); 306 307 ret = clk_prepare_enable(info->clk); 308 if (ret < 0) 309 return ret; 310 311 /* set context info. */ 312 info->pdev = pdev; 313 spin_lock_init(&info->tegra_rtc_lock); 314 315 platform_set_drvdata(pdev, info); 316 317 /* clear out the hardware. */ 318 writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); 319 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 320 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 321 322 device_init_wakeup(&pdev->dev, 1); 323 324 ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq, 325 tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH, 326 dev_name(&pdev->dev), &pdev->dev); 327 if (ret) { 328 dev_err(&pdev->dev, 329 "Unable to request interrupt for device (err=%d).\n", 330 ret); 331 goto disable_clk; 332 } 333 334 ret = rtc_register_device(info->rtc_dev); 335 if (ret) { 336 dev_err(&pdev->dev, "Unable to register device (err=%d).\n", 337 ret); 338 goto disable_clk; 339 } 340 341 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n"); 342 343 return 0; 344 345 disable_clk: 346 clk_disable_unprepare(info->clk); 347 return ret; 348 } 349 350 static int tegra_rtc_remove(struct platform_device *pdev) 351 { 352 struct tegra_rtc_info *info = platform_get_drvdata(pdev); 353 354 clk_disable_unprepare(info->clk); 355 356 return 0; 357 } 358 359 #ifdef CONFIG_PM_SLEEP 360 static int tegra_rtc_suspend(struct device *dev) 361 { 362 struct tegra_rtc_info *info = dev_get_drvdata(dev); 363 364 tegra_rtc_wait_while_busy(dev); 365 366 /* only use ALARM0 as a wake source. */ 367 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 368 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0, 369 info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 370 371 dev_vdbg(dev, "alarm sec = %d\n", 372 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); 373 374 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n", 375 device_may_wakeup(dev), info->tegra_rtc_irq); 376 377 /* leave the alarms on as a wake source. */ 378 if (device_may_wakeup(dev)) 379 enable_irq_wake(info->tegra_rtc_irq); 380 381 return 0; 382 } 383 384 static int tegra_rtc_resume(struct device *dev) 385 { 386 struct tegra_rtc_info *info = dev_get_drvdata(dev); 387 388 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n", 389 device_may_wakeup(dev)); 390 /* alarms were left on as a wake source, turn them off. */ 391 if (device_may_wakeup(dev)) 392 disable_irq_wake(info->tegra_rtc_irq); 393 394 return 0; 395 } 396 #endif 397 398 static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume); 399 400 static void tegra_rtc_shutdown(struct platform_device *pdev) 401 { 402 dev_vdbg(&pdev->dev, "disabling interrupts.\n"); 403 tegra_rtc_alarm_irq_enable(&pdev->dev, 0); 404 } 405 406 MODULE_ALIAS("platform:tegra_rtc"); 407 static struct platform_driver tegra_rtc_driver = { 408 .remove = tegra_rtc_remove, 409 .shutdown = tegra_rtc_shutdown, 410 .driver = { 411 .name = "tegra_rtc", 412 .of_match_table = tegra_rtc_dt_match, 413 .pm = &tegra_rtc_pm_ops, 414 }, 415 }; 416 417 module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe); 418 419 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>"); 420 MODULE_DESCRIPTION("driver for Tegra internal RTC"); 421 MODULE_LICENSE("GPL"); 422