1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/stddef.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/export.h> 16 #include <linux/nmi.h> 17 18 #include <asm/cpufeature.h> 19 #include <asm/hardirq.h> 20 #include <asm/intel-family.h> 21 #include <asm/intel_pt.h> 22 #include <asm/apic.h> 23 #include <asm/cpu_device_id.h> 24 25 #include "../perf_event.h" 26 27 /* 28 * Intel PerfMon, used on Core and later. 29 */ 30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 31 { 32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 40 }; 41 42 static struct event_constraint intel_core_event_constraints[] __read_mostly = 43 { 44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 50 EVENT_CONSTRAINT_END 51 }; 52 53 static struct event_constraint intel_core2_event_constraints[] __read_mostly = 54 { 55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 68 EVENT_CONSTRAINT_END 69 }; 70 71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 72 { 73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 84 EVENT_CONSTRAINT_END 85 }; 86 87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 88 { 89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 92 EVENT_EXTRA_END 93 }; 94 95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 96 { 97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 104 EVENT_CONSTRAINT_END 105 }; 106 107 static struct event_constraint intel_snb_event_constraints[] __read_mostly = 108 { 109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 121 122 /* 123 * When HT is off these events can only run on the bottom 4 counters 124 * When HT is on, they are impacted by the HT bug and require EXCL access 125 */ 126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 130 131 EVENT_CONSTRAINT_END 132 }; 133 134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 135 { 136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */ 141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 149 150 /* 151 * When HT is off these events can only run on the bottom 4 counters 152 * When HT is on, they are impacted by the HT bug and require EXCL access 153 */ 154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 158 159 EVENT_CONSTRAINT_END 160 }; 161 162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 163 { 164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 168 EVENT_EXTRA_END 169 }; 170 171 static struct event_constraint intel_v1_event_constraints[] __read_mostly = 172 { 173 EVENT_CONSTRAINT_END 174 }; 175 176 static struct event_constraint intel_gen_event_constraints[] __read_mostly = 177 { 178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 181 EVENT_CONSTRAINT_END 182 }; 183 184 static struct event_constraint intel_slm_event_constraints[] __read_mostly = 185 { 186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 189 EVENT_CONSTRAINT_END 190 }; 191 192 static struct event_constraint intel_skl_event_constraints[] = { 193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 197 198 /* 199 * when HT is off, these can only run on the bottom 4 counters 200 */ 201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 206 207 EVENT_CONSTRAINT_END 208 }; 209 210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 213 EVENT_EXTRA_END 214 }; 215 216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 221 EVENT_EXTRA_END 222 }; 223 224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 229 EVENT_EXTRA_END 230 }; 231 232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 236 /* 237 * Note the low 8 bits eventsel code is not a continuous field, containing 238 * some #GPing bits. These are masked out. 239 */ 240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 241 EVENT_EXTRA_END 242 }; 243 244 static struct event_constraint intel_icl_event_constraints[] = { 245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */ 247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 249 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 250 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 252 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 253 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 254 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 255 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 256 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 257 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), 258 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 259 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 260 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 261 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 262 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 263 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 264 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 265 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 266 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 267 EVENT_CONSTRAINT_END 268 }; 269 270 static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 271 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 272 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 273 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 274 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 275 EVENT_EXTRA_END 276 }; 277 278 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 279 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 280 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 281 282 static struct attribute *nhm_mem_events_attrs[] = { 283 EVENT_PTR(mem_ld_nhm), 284 NULL, 285 }; 286 287 /* 288 * topdown events for Intel Core CPUs. 289 * 290 * The events are all in slots, which is a free slot in a 4 wide 291 * pipeline. Some events are already reported in slots, for cycle 292 * events we multiply by the pipeline width (4). 293 * 294 * With Hyper Threading on, topdown metrics are either summed or averaged 295 * between the threads of a core: (count_t0 + count_t1). 296 * 297 * For the average case the metric is always scaled to pipeline width, 298 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 299 */ 300 301 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 302 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 303 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 304 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 305 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 306 "event=0xe,umask=0x1"); /* uops_issued.any */ 307 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 308 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 309 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 310 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 311 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 312 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 313 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 314 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 315 "4", "2"); 316 317 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 318 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 319 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 320 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 321 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 322 323 static struct attribute *snb_events_attrs[] = { 324 EVENT_PTR(td_slots_issued), 325 EVENT_PTR(td_slots_retired), 326 EVENT_PTR(td_fetch_bubbles), 327 EVENT_PTR(td_total_slots), 328 EVENT_PTR(td_total_slots_scale), 329 EVENT_PTR(td_recovery_bubbles), 330 EVENT_PTR(td_recovery_bubbles_scale), 331 NULL, 332 }; 333 334 static struct attribute *snb_mem_events_attrs[] = { 335 EVENT_PTR(mem_ld_snb), 336 EVENT_PTR(mem_st_snb), 337 NULL, 338 }; 339 340 static struct event_constraint intel_hsw_event_constraints[] = { 341 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 342 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 343 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 344 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 345 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 346 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 347 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 348 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 349 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 350 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 351 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 352 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 353 354 /* 355 * When HT is off these events can only run on the bottom 4 counters 356 * When HT is on, they are impacted by the HT bug and require EXCL access 357 */ 358 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 359 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 360 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 361 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 362 363 EVENT_CONSTRAINT_END 364 }; 365 366 static struct event_constraint intel_bdw_event_constraints[] = { 367 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 368 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 369 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 370 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 371 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 372 /* 373 * when HT is off, these can only run on the bottom 4 counters 374 */ 375 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 376 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 377 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 378 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 379 EVENT_CONSTRAINT_END 380 }; 381 382 static u64 intel_pmu_event_map(int hw_event) 383 { 384 return intel_perfmon_event_map[hw_event]; 385 } 386 387 /* 388 * Notes on the events: 389 * - data reads do not include code reads (comparable to earlier tables) 390 * - data counts include speculative execution (except L1 write, dtlb, bpu) 391 * - remote node access includes remote memory, remote cache, remote mmio. 392 * - prefetches are not included in the counts. 393 * - icache miss does not include decoded icache 394 */ 395 396 #define SKL_DEMAND_DATA_RD BIT_ULL(0) 397 #define SKL_DEMAND_RFO BIT_ULL(1) 398 #define SKL_ANY_RESPONSE BIT_ULL(16) 399 #define SKL_SUPPLIER_NONE BIT_ULL(17) 400 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 401 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 402 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 403 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 404 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 405 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 406 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 407 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 408 #define SKL_SPL_HIT BIT_ULL(30) 409 #define SKL_SNOOP_NONE BIT_ULL(31) 410 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 411 #define SKL_SNOOP_MISS BIT_ULL(33) 412 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 413 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 414 #define SKL_SNOOP_HITM BIT_ULL(36) 415 #define SKL_SNOOP_NON_DRAM BIT_ULL(37) 416 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 417 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 418 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 419 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 420 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 421 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 422 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 423 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 424 SKL_SNOOP_HITM|SKL_SPL_HIT) 425 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO 426 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE 427 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 428 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 429 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 430 431 static __initconst const u64 skl_hw_cache_event_ids 432 [PERF_COUNT_HW_CACHE_MAX] 433 [PERF_COUNT_HW_CACHE_OP_MAX] 434 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 435 { 436 [ C(L1D ) ] = { 437 [ C(OP_READ) ] = { 438 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 439 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 440 }, 441 [ C(OP_WRITE) ] = { 442 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 443 [ C(RESULT_MISS) ] = 0x0, 444 }, 445 [ C(OP_PREFETCH) ] = { 446 [ C(RESULT_ACCESS) ] = 0x0, 447 [ C(RESULT_MISS) ] = 0x0, 448 }, 449 }, 450 [ C(L1I ) ] = { 451 [ C(OP_READ) ] = { 452 [ C(RESULT_ACCESS) ] = 0x0, 453 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 454 }, 455 [ C(OP_WRITE) ] = { 456 [ C(RESULT_ACCESS) ] = -1, 457 [ C(RESULT_MISS) ] = -1, 458 }, 459 [ C(OP_PREFETCH) ] = { 460 [ C(RESULT_ACCESS) ] = 0x0, 461 [ C(RESULT_MISS) ] = 0x0, 462 }, 463 }, 464 [ C(LL ) ] = { 465 [ C(OP_READ) ] = { 466 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 467 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 468 }, 469 [ C(OP_WRITE) ] = { 470 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 471 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 472 }, 473 [ C(OP_PREFETCH) ] = { 474 [ C(RESULT_ACCESS) ] = 0x0, 475 [ C(RESULT_MISS) ] = 0x0, 476 }, 477 }, 478 [ C(DTLB) ] = { 479 [ C(OP_READ) ] = { 480 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 481 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 482 }, 483 [ C(OP_WRITE) ] = { 484 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 485 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 486 }, 487 [ C(OP_PREFETCH) ] = { 488 [ C(RESULT_ACCESS) ] = 0x0, 489 [ C(RESULT_MISS) ] = 0x0, 490 }, 491 }, 492 [ C(ITLB) ] = { 493 [ C(OP_READ) ] = { 494 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 495 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 496 }, 497 [ C(OP_WRITE) ] = { 498 [ C(RESULT_ACCESS) ] = -1, 499 [ C(RESULT_MISS) ] = -1, 500 }, 501 [ C(OP_PREFETCH) ] = { 502 [ C(RESULT_ACCESS) ] = -1, 503 [ C(RESULT_MISS) ] = -1, 504 }, 505 }, 506 [ C(BPU ) ] = { 507 [ C(OP_READ) ] = { 508 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 509 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 510 }, 511 [ C(OP_WRITE) ] = { 512 [ C(RESULT_ACCESS) ] = -1, 513 [ C(RESULT_MISS) ] = -1, 514 }, 515 [ C(OP_PREFETCH) ] = { 516 [ C(RESULT_ACCESS) ] = -1, 517 [ C(RESULT_MISS) ] = -1, 518 }, 519 }, 520 [ C(NODE) ] = { 521 [ C(OP_READ) ] = { 522 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 523 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 524 }, 525 [ C(OP_WRITE) ] = { 526 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 527 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 528 }, 529 [ C(OP_PREFETCH) ] = { 530 [ C(RESULT_ACCESS) ] = 0x0, 531 [ C(RESULT_MISS) ] = 0x0, 532 }, 533 }, 534 }; 535 536 static __initconst const u64 skl_hw_cache_extra_regs 537 [PERF_COUNT_HW_CACHE_MAX] 538 [PERF_COUNT_HW_CACHE_OP_MAX] 539 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 540 { 541 [ C(LL ) ] = { 542 [ C(OP_READ) ] = { 543 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 544 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 545 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 546 SKL_L3_MISS|SKL_ANY_SNOOP| 547 SKL_SUPPLIER_NONE, 548 }, 549 [ C(OP_WRITE) ] = { 550 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 551 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 552 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 553 SKL_L3_MISS|SKL_ANY_SNOOP| 554 SKL_SUPPLIER_NONE, 555 }, 556 [ C(OP_PREFETCH) ] = { 557 [ C(RESULT_ACCESS) ] = 0x0, 558 [ C(RESULT_MISS) ] = 0x0, 559 }, 560 }, 561 [ C(NODE) ] = { 562 [ C(OP_READ) ] = { 563 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 564 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 565 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 566 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 567 }, 568 [ C(OP_WRITE) ] = { 569 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 570 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 571 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 572 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 573 }, 574 [ C(OP_PREFETCH) ] = { 575 [ C(RESULT_ACCESS) ] = 0x0, 576 [ C(RESULT_MISS) ] = 0x0, 577 }, 578 }, 579 }; 580 581 #define SNB_DMND_DATA_RD (1ULL << 0) 582 #define SNB_DMND_RFO (1ULL << 1) 583 #define SNB_DMND_IFETCH (1ULL << 2) 584 #define SNB_DMND_WB (1ULL << 3) 585 #define SNB_PF_DATA_RD (1ULL << 4) 586 #define SNB_PF_RFO (1ULL << 5) 587 #define SNB_PF_IFETCH (1ULL << 6) 588 #define SNB_LLC_DATA_RD (1ULL << 7) 589 #define SNB_LLC_RFO (1ULL << 8) 590 #define SNB_LLC_IFETCH (1ULL << 9) 591 #define SNB_BUS_LOCKS (1ULL << 10) 592 #define SNB_STRM_ST (1ULL << 11) 593 #define SNB_OTHER (1ULL << 15) 594 #define SNB_RESP_ANY (1ULL << 16) 595 #define SNB_NO_SUPP (1ULL << 17) 596 #define SNB_LLC_HITM (1ULL << 18) 597 #define SNB_LLC_HITE (1ULL << 19) 598 #define SNB_LLC_HITS (1ULL << 20) 599 #define SNB_LLC_HITF (1ULL << 21) 600 #define SNB_LOCAL (1ULL << 22) 601 #define SNB_REMOTE (0xffULL << 23) 602 #define SNB_SNP_NONE (1ULL << 31) 603 #define SNB_SNP_NOT_NEEDED (1ULL << 32) 604 #define SNB_SNP_MISS (1ULL << 33) 605 #define SNB_NO_FWD (1ULL << 34) 606 #define SNB_SNP_FWD (1ULL << 35) 607 #define SNB_HITM (1ULL << 36) 608 #define SNB_NON_DRAM (1ULL << 37) 609 610 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 611 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 612 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 613 614 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 615 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 616 SNB_HITM) 617 618 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 619 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 620 621 #define SNB_L3_ACCESS SNB_RESP_ANY 622 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 623 624 static __initconst const u64 snb_hw_cache_extra_regs 625 [PERF_COUNT_HW_CACHE_MAX] 626 [PERF_COUNT_HW_CACHE_OP_MAX] 627 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 628 { 629 [ C(LL ) ] = { 630 [ C(OP_READ) ] = { 631 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 632 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 633 }, 634 [ C(OP_WRITE) ] = { 635 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 636 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 637 }, 638 [ C(OP_PREFETCH) ] = { 639 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 640 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 641 }, 642 }, 643 [ C(NODE) ] = { 644 [ C(OP_READ) ] = { 645 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 646 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 647 }, 648 [ C(OP_WRITE) ] = { 649 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 650 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 651 }, 652 [ C(OP_PREFETCH) ] = { 653 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 654 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 655 }, 656 }, 657 }; 658 659 static __initconst const u64 snb_hw_cache_event_ids 660 [PERF_COUNT_HW_CACHE_MAX] 661 [PERF_COUNT_HW_CACHE_OP_MAX] 662 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 663 { 664 [ C(L1D) ] = { 665 [ C(OP_READ) ] = { 666 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 667 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 668 }, 669 [ C(OP_WRITE) ] = { 670 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 671 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 672 }, 673 [ C(OP_PREFETCH) ] = { 674 [ C(RESULT_ACCESS) ] = 0x0, 675 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 676 }, 677 }, 678 [ C(L1I ) ] = { 679 [ C(OP_READ) ] = { 680 [ C(RESULT_ACCESS) ] = 0x0, 681 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 682 }, 683 [ C(OP_WRITE) ] = { 684 [ C(RESULT_ACCESS) ] = -1, 685 [ C(RESULT_MISS) ] = -1, 686 }, 687 [ C(OP_PREFETCH) ] = { 688 [ C(RESULT_ACCESS) ] = 0x0, 689 [ C(RESULT_MISS) ] = 0x0, 690 }, 691 }, 692 [ C(LL ) ] = { 693 [ C(OP_READ) ] = { 694 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 695 [ C(RESULT_ACCESS) ] = 0x01b7, 696 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 697 [ C(RESULT_MISS) ] = 0x01b7, 698 }, 699 [ C(OP_WRITE) ] = { 700 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 701 [ C(RESULT_ACCESS) ] = 0x01b7, 702 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 703 [ C(RESULT_MISS) ] = 0x01b7, 704 }, 705 [ C(OP_PREFETCH) ] = { 706 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 707 [ C(RESULT_ACCESS) ] = 0x01b7, 708 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 709 [ C(RESULT_MISS) ] = 0x01b7, 710 }, 711 }, 712 [ C(DTLB) ] = { 713 [ C(OP_READ) ] = { 714 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 715 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 716 }, 717 [ C(OP_WRITE) ] = { 718 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 719 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 720 }, 721 [ C(OP_PREFETCH) ] = { 722 [ C(RESULT_ACCESS) ] = 0x0, 723 [ C(RESULT_MISS) ] = 0x0, 724 }, 725 }, 726 [ C(ITLB) ] = { 727 [ C(OP_READ) ] = { 728 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 729 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 730 }, 731 [ C(OP_WRITE) ] = { 732 [ C(RESULT_ACCESS) ] = -1, 733 [ C(RESULT_MISS) ] = -1, 734 }, 735 [ C(OP_PREFETCH) ] = { 736 [ C(RESULT_ACCESS) ] = -1, 737 [ C(RESULT_MISS) ] = -1, 738 }, 739 }, 740 [ C(BPU ) ] = { 741 [ C(OP_READ) ] = { 742 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 743 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 744 }, 745 [ C(OP_WRITE) ] = { 746 [ C(RESULT_ACCESS) ] = -1, 747 [ C(RESULT_MISS) ] = -1, 748 }, 749 [ C(OP_PREFETCH) ] = { 750 [ C(RESULT_ACCESS) ] = -1, 751 [ C(RESULT_MISS) ] = -1, 752 }, 753 }, 754 [ C(NODE) ] = { 755 [ C(OP_READ) ] = { 756 [ C(RESULT_ACCESS) ] = 0x01b7, 757 [ C(RESULT_MISS) ] = 0x01b7, 758 }, 759 [ C(OP_WRITE) ] = { 760 [ C(RESULT_ACCESS) ] = 0x01b7, 761 [ C(RESULT_MISS) ] = 0x01b7, 762 }, 763 [ C(OP_PREFETCH) ] = { 764 [ C(RESULT_ACCESS) ] = 0x01b7, 765 [ C(RESULT_MISS) ] = 0x01b7, 766 }, 767 }, 768 769 }; 770 771 /* 772 * Notes on the events: 773 * - data reads do not include code reads (comparable to earlier tables) 774 * - data counts include speculative execution (except L1 write, dtlb, bpu) 775 * - remote node access includes remote memory, remote cache, remote mmio. 776 * - prefetches are not included in the counts because they are not 777 * reliably counted. 778 */ 779 780 #define HSW_DEMAND_DATA_RD BIT_ULL(0) 781 #define HSW_DEMAND_RFO BIT_ULL(1) 782 #define HSW_ANY_RESPONSE BIT_ULL(16) 783 #define HSW_SUPPLIER_NONE BIT_ULL(17) 784 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 785 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 786 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 787 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 788 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 789 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 790 HSW_L3_MISS_REMOTE_HOP2P) 791 #define HSW_SNOOP_NONE BIT_ULL(31) 792 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 793 #define HSW_SNOOP_MISS BIT_ULL(33) 794 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 795 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 796 #define HSW_SNOOP_HITM BIT_ULL(36) 797 #define HSW_SNOOP_NON_DRAM BIT_ULL(37) 798 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 799 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 800 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 801 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 802 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 803 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 804 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO 805 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 806 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 807 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE 808 809 #define BDW_L3_MISS_LOCAL BIT(26) 810 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 811 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 812 HSW_L3_MISS_REMOTE_HOP2P) 813 814 815 static __initconst const u64 hsw_hw_cache_event_ids 816 [PERF_COUNT_HW_CACHE_MAX] 817 [PERF_COUNT_HW_CACHE_OP_MAX] 818 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 819 { 820 [ C(L1D ) ] = { 821 [ C(OP_READ) ] = { 822 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 823 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 824 }, 825 [ C(OP_WRITE) ] = { 826 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 827 [ C(RESULT_MISS) ] = 0x0, 828 }, 829 [ C(OP_PREFETCH) ] = { 830 [ C(RESULT_ACCESS) ] = 0x0, 831 [ C(RESULT_MISS) ] = 0x0, 832 }, 833 }, 834 [ C(L1I ) ] = { 835 [ C(OP_READ) ] = { 836 [ C(RESULT_ACCESS) ] = 0x0, 837 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 838 }, 839 [ C(OP_WRITE) ] = { 840 [ C(RESULT_ACCESS) ] = -1, 841 [ C(RESULT_MISS) ] = -1, 842 }, 843 [ C(OP_PREFETCH) ] = { 844 [ C(RESULT_ACCESS) ] = 0x0, 845 [ C(RESULT_MISS) ] = 0x0, 846 }, 847 }, 848 [ C(LL ) ] = { 849 [ C(OP_READ) ] = { 850 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 851 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 852 }, 853 [ C(OP_WRITE) ] = { 854 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 855 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 856 }, 857 [ C(OP_PREFETCH) ] = { 858 [ C(RESULT_ACCESS) ] = 0x0, 859 [ C(RESULT_MISS) ] = 0x0, 860 }, 861 }, 862 [ C(DTLB) ] = { 863 [ C(OP_READ) ] = { 864 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 865 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 866 }, 867 [ C(OP_WRITE) ] = { 868 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 869 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 870 }, 871 [ C(OP_PREFETCH) ] = { 872 [ C(RESULT_ACCESS) ] = 0x0, 873 [ C(RESULT_MISS) ] = 0x0, 874 }, 875 }, 876 [ C(ITLB) ] = { 877 [ C(OP_READ) ] = { 878 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 879 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 880 }, 881 [ C(OP_WRITE) ] = { 882 [ C(RESULT_ACCESS) ] = -1, 883 [ C(RESULT_MISS) ] = -1, 884 }, 885 [ C(OP_PREFETCH) ] = { 886 [ C(RESULT_ACCESS) ] = -1, 887 [ C(RESULT_MISS) ] = -1, 888 }, 889 }, 890 [ C(BPU ) ] = { 891 [ C(OP_READ) ] = { 892 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 893 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 894 }, 895 [ C(OP_WRITE) ] = { 896 [ C(RESULT_ACCESS) ] = -1, 897 [ C(RESULT_MISS) ] = -1, 898 }, 899 [ C(OP_PREFETCH) ] = { 900 [ C(RESULT_ACCESS) ] = -1, 901 [ C(RESULT_MISS) ] = -1, 902 }, 903 }, 904 [ C(NODE) ] = { 905 [ C(OP_READ) ] = { 906 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 907 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 908 }, 909 [ C(OP_WRITE) ] = { 910 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 911 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 912 }, 913 [ C(OP_PREFETCH) ] = { 914 [ C(RESULT_ACCESS) ] = 0x0, 915 [ C(RESULT_MISS) ] = 0x0, 916 }, 917 }, 918 }; 919 920 static __initconst const u64 hsw_hw_cache_extra_regs 921 [PERF_COUNT_HW_CACHE_MAX] 922 [PERF_COUNT_HW_CACHE_OP_MAX] 923 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 924 { 925 [ C(LL ) ] = { 926 [ C(OP_READ) ] = { 927 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 928 HSW_LLC_ACCESS, 929 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 930 HSW_L3_MISS|HSW_ANY_SNOOP, 931 }, 932 [ C(OP_WRITE) ] = { 933 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 934 HSW_LLC_ACCESS, 935 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 936 HSW_L3_MISS|HSW_ANY_SNOOP, 937 }, 938 [ C(OP_PREFETCH) ] = { 939 [ C(RESULT_ACCESS) ] = 0x0, 940 [ C(RESULT_MISS) ] = 0x0, 941 }, 942 }, 943 [ C(NODE) ] = { 944 [ C(OP_READ) ] = { 945 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 946 HSW_L3_MISS_LOCAL_DRAM| 947 HSW_SNOOP_DRAM, 948 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 949 HSW_L3_MISS_REMOTE| 950 HSW_SNOOP_DRAM, 951 }, 952 [ C(OP_WRITE) ] = { 953 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 954 HSW_L3_MISS_LOCAL_DRAM| 955 HSW_SNOOP_DRAM, 956 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 957 HSW_L3_MISS_REMOTE| 958 HSW_SNOOP_DRAM, 959 }, 960 [ C(OP_PREFETCH) ] = { 961 [ C(RESULT_ACCESS) ] = 0x0, 962 [ C(RESULT_MISS) ] = 0x0, 963 }, 964 }, 965 }; 966 967 static __initconst const u64 westmere_hw_cache_event_ids 968 [PERF_COUNT_HW_CACHE_MAX] 969 [PERF_COUNT_HW_CACHE_OP_MAX] 970 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 971 { 972 [ C(L1D) ] = { 973 [ C(OP_READ) ] = { 974 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 975 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 976 }, 977 [ C(OP_WRITE) ] = { 978 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 979 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 980 }, 981 [ C(OP_PREFETCH) ] = { 982 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 983 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 984 }, 985 }, 986 [ C(L1I ) ] = { 987 [ C(OP_READ) ] = { 988 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 989 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 990 }, 991 [ C(OP_WRITE) ] = { 992 [ C(RESULT_ACCESS) ] = -1, 993 [ C(RESULT_MISS) ] = -1, 994 }, 995 [ C(OP_PREFETCH) ] = { 996 [ C(RESULT_ACCESS) ] = 0x0, 997 [ C(RESULT_MISS) ] = 0x0, 998 }, 999 }, 1000 [ C(LL ) ] = { 1001 [ C(OP_READ) ] = { 1002 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1003 [ C(RESULT_ACCESS) ] = 0x01b7, 1004 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1005 [ C(RESULT_MISS) ] = 0x01b7, 1006 }, 1007 /* 1008 * Use RFO, not WRITEBACK, because a write miss would typically occur 1009 * on RFO. 1010 */ 1011 [ C(OP_WRITE) ] = { 1012 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1013 [ C(RESULT_ACCESS) ] = 0x01b7, 1014 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1015 [ C(RESULT_MISS) ] = 0x01b7, 1016 }, 1017 [ C(OP_PREFETCH) ] = { 1018 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1019 [ C(RESULT_ACCESS) ] = 0x01b7, 1020 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1021 [ C(RESULT_MISS) ] = 0x01b7, 1022 }, 1023 }, 1024 [ C(DTLB) ] = { 1025 [ C(OP_READ) ] = { 1026 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1027 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1028 }, 1029 [ C(OP_WRITE) ] = { 1030 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1031 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1032 }, 1033 [ C(OP_PREFETCH) ] = { 1034 [ C(RESULT_ACCESS) ] = 0x0, 1035 [ C(RESULT_MISS) ] = 0x0, 1036 }, 1037 }, 1038 [ C(ITLB) ] = { 1039 [ C(OP_READ) ] = { 1040 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1041 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1042 }, 1043 [ C(OP_WRITE) ] = { 1044 [ C(RESULT_ACCESS) ] = -1, 1045 [ C(RESULT_MISS) ] = -1, 1046 }, 1047 [ C(OP_PREFETCH) ] = { 1048 [ C(RESULT_ACCESS) ] = -1, 1049 [ C(RESULT_MISS) ] = -1, 1050 }, 1051 }, 1052 [ C(BPU ) ] = { 1053 [ C(OP_READ) ] = { 1054 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1055 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1056 }, 1057 [ C(OP_WRITE) ] = { 1058 [ C(RESULT_ACCESS) ] = -1, 1059 [ C(RESULT_MISS) ] = -1, 1060 }, 1061 [ C(OP_PREFETCH) ] = { 1062 [ C(RESULT_ACCESS) ] = -1, 1063 [ C(RESULT_MISS) ] = -1, 1064 }, 1065 }, 1066 [ C(NODE) ] = { 1067 [ C(OP_READ) ] = { 1068 [ C(RESULT_ACCESS) ] = 0x01b7, 1069 [ C(RESULT_MISS) ] = 0x01b7, 1070 }, 1071 [ C(OP_WRITE) ] = { 1072 [ C(RESULT_ACCESS) ] = 0x01b7, 1073 [ C(RESULT_MISS) ] = 0x01b7, 1074 }, 1075 [ C(OP_PREFETCH) ] = { 1076 [ C(RESULT_ACCESS) ] = 0x01b7, 1077 [ C(RESULT_MISS) ] = 0x01b7, 1078 }, 1079 }, 1080 }; 1081 1082 /* 1083 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1084 * See IA32 SDM Vol 3B 30.6.1.3 1085 */ 1086 1087 #define NHM_DMND_DATA_RD (1 << 0) 1088 #define NHM_DMND_RFO (1 << 1) 1089 #define NHM_DMND_IFETCH (1 << 2) 1090 #define NHM_DMND_WB (1 << 3) 1091 #define NHM_PF_DATA_RD (1 << 4) 1092 #define NHM_PF_DATA_RFO (1 << 5) 1093 #define NHM_PF_IFETCH (1 << 6) 1094 #define NHM_OFFCORE_OTHER (1 << 7) 1095 #define NHM_UNCORE_HIT (1 << 8) 1096 #define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1097 #define NHM_OTHER_CORE_HITM (1 << 10) 1098 /* reserved */ 1099 #define NHM_REMOTE_CACHE_FWD (1 << 12) 1100 #define NHM_REMOTE_DRAM (1 << 13) 1101 #define NHM_LOCAL_DRAM (1 << 14) 1102 #define NHM_NON_DRAM (1 << 15) 1103 1104 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1105 #define NHM_REMOTE (NHM_REMOTE_DRAM) 1106 1107 #define NHM_DMND_READ (NHM_DMND_DATA_RD) 1108 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1109 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1110 1111 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1112 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1113 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1114 1115 static __initconst const u64 nehalem_hw_cache_extra_regs 1116 [PERF_COUNT_HW_CACHE_MAX] 1117 [PERF_COUNT_HW_CACHE_OP_MAX] 1118 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1119 { 1120 [ C(LL ) ] = { 1121 [ C(OP_READ) ] = { 1122 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1123 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1124 }, 1125 [ C(OP_WRITE) ] = { 1126 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1127 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1128 }, 1129 [ C(OP_PREFETCH) ] = { 1130 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1131 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1132 }, 1133 }, 1134 [ C(NODE) ] = { 1135 [ C(OP_READ) ] = { 1136 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1137 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1138 }, 1139 [ C(OP_WRITE) ] = { 1140 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1141 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1142 }, 1143 [ C(OP_PREFETCH) ] = { 1144 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1145 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1146 }, 1147 }, 1148 }; 1149 1150 static __initconst const u64 nehalem_hw_cache_event_ids 1151 [PERF_COUNT_HW_CACHE_MAX] 1152 [PERF_COUNT_HW_CACHE_OP_MAX] 1153 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1154 { 1155 [ C(L1D) ] = { 1156 [ C(OP_READ) ] = { 1157 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1158 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1159 }, 1160 [ C(OP_WRITE) ] = { 1161 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1162 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1163 }, 1164 [ C(OP_PREFETCH) ] = { 1165 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1166 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1167 }, 1168 }, 1169 [ C(L1I ) ] = { 1170 [ C(OP_READ) ] = { 1171 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1172 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1173 }, 1174 [ C(OP_WRITE) ] = { 1175 [ C(RESULT_ACCESS) ] = -1, 1176 [ C(RESULT_MISS) ] = -1, 1177 }, 1178 [ C(OP_PREFETCH) ] = { 1179 [ C(RESULT_ACCESS) ] = 0x0, 1180 [ C(RESULT_MISS) ] = 0x0, 1181 }, 1182 }, 1183 [ C(LL ) ] = { 1184 [ C(OP_READ) ] = { 1185 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1186 [ C(RESULT_ACCESS) ] = 0x01b7, 1187 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1188 [ C(RESULT_MISS) ] = 0x01b7, 1189 }, 1190 /* 1191 * Use RFO, not WRITEBACK, because a write miss would typically occur 1192 * on RFO. 1193 */ 1194 [ C(OP_WRITE) ] = { 1195 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1196 [ C(RESULT_ACCESS) ] = 0x01b7, 1197 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1198 [ C(RESULT_MISS) ] = 0x01b7, 1199 }, 1200 [ C(OP_PREFETCH) ] = { 1201 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1202 [ C(RESULT_ACCESS) ] = 0x01b7, 1203 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1204 [ C(RESULT_MISS) ] = 0x01b7, 1205 }, 1206 }, 1207 [ C(DTLB) ] = { 1208 [ C(OP_READ) ] = { 1209 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1210 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1211 }, 1212 [ C(OP_WRITE) ] = { 1213 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1214 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1215 }, 1216 [ C(OP_PREFETCH) ] = { 1217 [ C(RESULT_ACCESS) ] = 0x0, 1218 [ C(RESULT_MISS) ] = 0x0, 1219 }, 1220 }, 1221 [ C(ITLB) ] = { 1222 [ C(OP_READ) ] = { 1223 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1224 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1225 }, 1226 [ C(OP_WRITE) ] = { 1227 [ C(RESULT_ACCESS) ] = -1, 1228 [ C(RESULT_MISS) ] = -1, 1229 }, 1230 [ C(OP_PREFETCH) ] = { 1231 [ C(RESULT_ACCESS) ] = -1, 1232 [ C(RESULT_MISS) ] = -1, 1233 }, 1234 }, 1235 [ C(BPU ) ] = { 1236 [ C(OP_READ) ] = { 1237 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1238 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1239 }, 1240 [ C(OP_WRITE) ] = { 1241 [ C(RESULT_ACCESS) ] = -1, 1242 [ C(RESULT_MISS) ] = -1, 1243 }, 1244 [ C(OP_PREFETCH) ] = { 1245 [ C(RESULT_ACCESS) ] = -1, 1246 [ C(RESULT_MISS) ] = -1, 1247 }, 1248 }, 1249 [ C(NODE) ] = { 1250 [ C(OP_READ) ] = { 1251 [ C(RESULT_ACCESS) ] = 0x01b7, 1252 [ C(RESULT_MISS) ] = 0x01b7, 1253 }, 1254 [ C(OP_WRITE) ] = { 1255 [ C(RESULT_ACCESS) ] = 0x01b7, 1256 [ C(RESULT_MISS) ] = 0x01b7, 1257 }, 1258 [ C(OP_PREFETCH) ] = { 1259 [ C(RESULT_ACCESS) ] = 0x01b7, 1260 [ C(RESULT_MISS) ] = 0x01b7, 1261 }, 1262 }, 1263 }; 1264 1265 static __initconst const u64 core2_hw_cache_event_ids 1266 [PERF_COUNT_HW_CACHE_MAX] 1267 [PERF_COUNT_HW_CACHE_OP_MAX] 1268 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1269 { 1270 [ C(L1D) ] = { 1271 [ C(OP_READ) ] = { 1272 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1273 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1274 }, 1275 [ C(OP_WRITE) ] = { 1276 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1277 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1278 }, 1279 [ C(OP_PREFETCH) ] = { 1280 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1281 [ C(RESULT_MISS) ] = 0, 1282 }, 1283 }, 1284 [ C(L1I ) ] = { 1285 [ C(OP_READ) ] = { 1286 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1287 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1288 }, 1289 [ C(OP_WRITE) ] = { 1290 [ C(RESULT_ACCESS) ] = -1, 1291 [ C(RESULT_MISS) ] = -1, 1292 }, 1293 [ C(OP_PREFETCH) ] = { 1294 [ C(RESULT_ACCESS) ] = 0, 1295 [ C(RESULT_MISS) ] = 0, 1296 }, 1297 }, 1298 [ C(LL ) ] = { 1299 [ C(OP_READ) ] = { 1300 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1301 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1302 }, 1303 [ C(OP_WRITE) ] = { 1304 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1305 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1306 }, 1307 [ C(OP_PREFETCH) ] = { 1308 [ C(RESULT_ACCESS) ] = 0, 1309 [ C(RESULT_MISS) ] = 0, 1310 }, 1311 }, 1312 [ C(DTLB) ] = { 1313 [ C(OP_READ) ] = { 1314 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1315 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1316 }, 1317 [ C(OP_WRITE) ] = { 1318 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1319 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1320 }, 1321 [ C(OP_PREFETCH) ] = { 1322 [ C(RESULT_ACCESS) ] = 0, 1323 [ C(RESULT_MISS) ] = 0, 1324 }, 1325 }, 1326 [ C(ITLB) ] = { 1327 [ C(OP_READ) ] = { 1328 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1329 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1330 }, 1331 [ C(OP_WRITE) ] = { 1332 [ C(RESULT_ACCESS) ] = -1, 1333 [ C(RESULT_MISS) ] = -1, 1334 }, 1335 [ C(OP_PREFETCH) ] = { 1336 [ C(RESULT_ACCESS) ] = -1, 1337 [ C(RESULT_MISS) ] = -1, 1338 }, 1339 }, 1340 [ C(BPU ) ] = { 1341 [ C(OP_READ) ] = { 1342 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1343 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1344 }, 1345 [ C(OP_WRITE) ] = { 1346 [ C(RESULT_ACCESS) ] = -1, 1347 [ C(RESULT_MISS) ] = -1, 1348 }, 1349 [ C(OP_PREFETCH) ] = { 1350 [ C(RESULT_ACCESS) ] = -1, 1351 [ C(RESULT_MISS) ] = -1, 1352 }, 1353 }, 1354 }; 1355 1356 static __initconst const u64 atom_hw_cache_event_ids 1357 [PERF_COUNT_HW_CACHE_MAX] 1358 [PERF_COUNT_HW_CACHE_OP_MAX] 1359 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1360 { 1361 [ C(L1D) ] = { 1362 [ C(OP_READ) ] = { 1363 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1364 [ C(RESULT_MISS) ] = 0, 1365 }, 1366 [ C(OP_WRITE) ] = { 1367 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1368 [ C(RESULT_MISS) ] = 0, 1369 }, 1370 [ C(OP_PREFETCH) ] = { 1371 [ C(RESULT_ACCESS) ] = 0x0, 1372 [ C(RESULT_MISS) ] = 0, 1373 }, 1374 }, 1375 [ C(L1I ) ] = { 1376 [ C(OP_READ) ] = { 1377 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1378 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1379 }, 1380 [ C(OP_WRITE) ] = { 1381 [ C(RESULT_ACCESS) ] = -1, 1382 [ C(RESULT_MISS) ] = -1, 1383 }, 1384 [ C(OP_PREFETCH) ] = { 1385 [ C(RESULT_ACCESS) ] = 0, 1386 [ C(RESULT_MISS) ] = 0, 1387 }, 1388 }, 1389 [ C(LL ) ] = { 1390 [ C(OP_READ) ] = { 1391 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1392 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1393 }, 1394 [ C(OP_WRITE) ] = { 1395 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1396 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1397 }, 1398 [ C(OP_PREFETCH) ] = { 1399 [ C(RESULT_ACCESS) ] = 0, 1400 [ C(RESULT_MISS) ] = 0, 1401 }, 1402 }, 1403 [ C(DTLB) ] = { 1404 [ C(OP_READ) ] = { 1405 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1406 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1407 }, 1408 [ C(OP_WRITE) ] = { 1409 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1410 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1411 }, 1412 [ C(OP_PREFETCH) ] = { 1413 [ C(RESULT_ACCESS) ] = 0, 1414 [ C(RESULT_MISS) ] = 0, 1415 }, 1416 }, 1417 [ C(ITLB) ] = { 1418 [ C(OP_READ) ] = { 1419 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1420 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1421 }, 1422 [ C(OP_WRITE) ] = { 1423 [ C(RESULT_ACCESS) ] = -1, 1424 [ C(RESULT_MISS) ] = -1, 1425 }, 1426 [ C(OP_PREFETCH) ] = { 1427 [ C(RESULT_ACCESS) ] = -1, 1428 [ C(RESULT_MISS) ] = -1, 1429 }, 1430 }, 1431 [ C(BPU ) ] = { 1432 [ C(OP_READ) ] = { 1433 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1434 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1435 }, 1436 [ C(OP_WRITE) ] = { 1437 [ C(RESULT_ACCESS) ] = -1, 1438 [ C(RESULT_MISS) ] = -1, 1439 }, 1440 [ C(OP_PREFETCH) ] = { 1441 [ C(RESULT_ACCESS) ] = -1, 1442 [ C(RESULT_MISS) ] = -1, 1443 }, 1444 }, 1445 }; 1446 1447 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1448 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1449 /* no_alloc_cycles.not_delivered */ 1450 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1451 "event=0xca,umask=0x50"); 1452 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1453 /* uops_retired.all */ 1454 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1455 "event=0xc2,umask=0x10"); 1456 /* uops_retired.all */ 1457 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1458 "event=0xc2,umask=0x10"); 1459 1460 static struct attribute *slm_events_attrs[] = { 1461 EVENT_PTR(td_total_slots_slm), 1462 EVENT_PTR(td_total_slots_scale_slm), 1463 EVENT_PTR(td_fetch_bubbles_slm), 1464 EVENT_PTR(td_fetch_bubbles_scale_slm), 1465 EVENT_PTR(td_slots_issued_slm), 1466 EVENT_PTR(td_slots_retired_slm), 1467 NULL 1468 }; 1469 1470 static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1471 { 1472 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1473 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1474 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1475 EVENT_EXTRA_END 1476 }; 1477 1478 #define SLM_DMND_READ SNB_DMND_DATA_RD 1479 #define SLM_DMND_WRITE SNB_DMND_RFO 1480 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1481 1482 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1483 #define SLM_LLC_ACCESS SNB_RESP_ANY 1484 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1485 1486 static __initconst const u64 slm_hw_cache_extra_regs 1487 [PERF_COUNT_HW_CACHE_MAX] 1488 [PERF_COUNT_HW_CACHE_OP_MAX] 1489 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1490 { 1491 [ C(LL ) ] = { 1492 [ C(OP_READ) ] = { 1493 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1494 [ C(RESULT_MISS) ] = 0, 1495 }, 1496 [ C(OP_WRITE) ] = { 1497 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1498 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1499 }, 1500 [ C(OP_PREFETCH) ] = { 1501 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1502 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1503 }, 1504 }, 1505 }; 1506 1507 static __initconst const u64 slm_hw_cache_event_ids 1508 [PERF_COUNT_HW_CACHE_MAX] 1509 [PERF_COUNT_HW_CACHE_OP_MAX] 1510 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1511 { 1512 [ C(L1D) ] = { 1513 [ C(OP_READ) ] = { 1514 [ C(RESULT_ACCESS) ] = 0, 1515 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1516 }, 1517 [ C(OP_WRITE) ] = { 1518 [ C(RESULT_ACCESS) ] = 0, 1519 [ C(RESULT_MISS) ] = 0, 1520 }, 1521 [ C(OP_PREFETCH) ] = { 1522 [ C(RESULT_ACCESS) ] = 0, 1523 [ C(RESULT_MISS) ] = 0, 1524 }, 1525 }, 1526 [ C(L1I ) ] = { 1527 [ C(OP_READ) ] = { 1528 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1529 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1530 }, 1531 [ C(OP_WRITE) ] = { 1532 [ C(RESULT_ACCESS) ] = -1, 1533 [ C(RESULT_MISS) ] = -1, 1534 }, 1535 [ C(OP_PREFETCH) ] = { 1536 [ C(RESULT_ACCESS) ] = 0, 1537 [ C(RESULT_MISS) ] = 0, 1538 }, 1539 }, 1540 [ C(LL ) ] = { 1541 [ C(OP_READ) ] = { 1542 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1543 [ C(RESULT_ACCESS) ] = 0x01b7, 1544 [ C(RESULT_MISS) ] = 0, 1545 }, 1546 [ C(OP_WRITE) ] = { 1547 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1548 [ C(RESULT_ACCESS) ] = 0x01b7, 1549 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1550 [ C(RESULT_MISS) ] = 0x01b7, 1551 }, 1552 [ C(OP_PREFETCH) ] = { 1553 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1554 [ C(RESULT_ACCESS) ] = 0x01b7, 1555 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1556 [ C(RESULT_MISS) ] = 0x01b7, 1557 }, 1558 }, 1559 [ C(DTLB) ] = { 1560 [ C(OP_READ) ] = { 1561 [ C(RESULT_ACCESS) ] = 0, 1562 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1563 }, 1564 [ C(OP_WRITE) ] = { 1565 [ C(RESULT_ACCESS) ] = 0, 1566 [ C(RESULT_MISS) ] = 0, 1567 }, 1568 [ C(OP_PREFETCH) ] = { 1569 [ C(RESULT_ACCESS) ] = 0, 1570 [ C(RESULT_MISS) ] = 0, 1571 }, 1572 }, 1573 [ C(ITLB) ] = { 1574 [ C(OP_READ) ] = { 1575 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1576 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1577 }, 1578 [ C(OP_WRITE) ] = { 1579 [ C(RESULT_ACCESS) ] = -1, 1580 [ C(RESULT_MISS) ] = -1, 1581 }, 1582 [ C(OP_PREFETCH) ] = { 1583 [ C(RESULT_ACCESS) ] = -1, 1584 [ C(RESULT_MISS) ] = -1, 1585 }, 1586 }, 1587 [ C(BPU ) ] = { 1588 [ C(OP_READ) ] = { 1589 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1590 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1591 }, 1592 [ C(OP_WRITE) ] = { 1593 [ C(RESULT_ACCESS) ] = -1, 1594 [ C(RESULT_MISS) ] = -1, 1595 }, 1596 [ C(OP_PREFETCH) ] = { 1597 [ C(RESULT_ACCESS) ] = -1, 1598 [ C(RESULT_MISS) ] = -1, 1599 }, 1600 }, 1601 }; 1602 1603 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1604 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1605 /* UOPS_NOT_DELIVERED.ANY */ 1606 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1607 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1608 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1609 /* UOPS_RETIRED.ANY */ 1610 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1611 /* UOPS_ISSUED.ANY */ 1612 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1613 1614 static struct attribute *glm_events_attrs[] = { 1615 EVENT_PTR(td_total_slots_glm), 1616 EVENT_PTR(td_total_slots_scale_glm), 1617 EVENT_PTR(td_fetch_bubbles_glm), 1618 EVENT_PTR(td_recovery_bubbles_glm), 1619 EVENT_PTR(td_slots_issued_glm), 1620 EVENT_PTR(td_slots_retired_glm), 1621 NULL 1622 }; 1623 1624 static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1625 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1626 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1627 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1628 EVENT_EXTRA_END 1629 }; 1630 1631 #define GLM_DEMAND_DATA_RD BIT_ULL(0) 1632 #define GLM_DEMAND_RFO BIT_ULL(1) 1633 #define GLM_ANY_RESPONSE BIT_ULL(16) 1634 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1635 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1636 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1637 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1638 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1639 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1640 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1641 1642 static __initconst const u64 glm_hw_cache_event_ids 1643 [PERF_COUNT_HW_CACHE_MAX] 1644 [PERF_COUNT_HW_CACHE_OP_MAX] 1645 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1646 [C(L1D)] = { 1647 [C(OP_READ)] = { 1648 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1649 [C(RESULT_MISS)] = 0x0, 1650 }, 1651 [C(OP_WRITE)] = { 1652 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1653 [C(RESULT_MISS)] = 0x0, 1654 }, 1655 [C(OP_PREFETCH)] = { 1656 [C(RESULT_ACCESS)] = 0x0, 1657 [C(RESULT_MISS)] = 0x0, 1658 }, 1659 }, 1660 [C(L1I)] = { 1661 [C(OP_READ)] = { 1662 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1663 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1664 }, 1665 [C(OP_WRITE)] = { 1666 [C(RESULT_ACCESS)] = -1, 1667 [C(RESULT_MISS)] = -1, 1668 }, 1669 [C(OP_PREFETCH)] = { 1670 [C(RESULT_ACCESS)] = 0x0, 1671 [C(RESULT_MISS)] = 0x0, 1672 }, 1673 }, 1674 [C(LL)] = { 1675 [C(OP_READ)] = { 1676 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1677 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1678 }, 1679 [C(OP_WRITE)] = { 1680 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1681 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1682 }, 1683 [C(OP_PREFETCH)] = { 1684 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1685 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1686 }, 1687 }, 1688 [C(DTLB)] = { 1689 [C(OP_READ)] = { 1690 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1691 [C(RESULT_MISS)] = 0x0, 1692 }, 1693 [C(OP_WRITE)] = { 1694 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1695 [C(RESULT_MISS)] = 0x0, 1696 }, 1697 [C(OP_PREFETCH)] = { 1698 [C(RESULT_ACCESS)] = 0x0, 1699 [C(RESULT_MISS)] = 0x0, 1700 }, 1701 }, 1702 [C(ITLB)] = { 1703 [C(OP_READ)] = { 1704 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1705 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1706 }, 1707 [C(OP_WRITE)] = { 1708 [C(RESULT_ACCESS)] = -1, 1709 [C(RESULT_MISS)] = -1, 1710 }, 1711 [C(OP_PREFETCH)] = { 1712 [C(RESULT_ACCESS)] = -1, 1713 [C(RESULT_MISS)] = -1, 1714 }, 1715 }, 1716 [C(BPU)] = { 1717 [C(OP_READ)] = { 1718 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1719 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1720 }, 1721 [C(OP_WRITE)] = { 1722 [C(RESULT_ACCESS)] = -1, 1723 [C(RESULT_MISS)] = -1, 1724 }, 1725 [C(OP_PREFETCH)] = { 1726 [C(RESULT_ACCESS)] = -1, 1727 [C(RESULT_MISS)] = -1, 1728 }, 1729 }, 1730 }; 1731 1732 static __initconst const u64 glm_hw_cache_extra_regs 1733 [PERF_COUNT_HW_CACHE_MAX] 1734 [PERF_COUNT_HW_CACHE_OP_MAX] 1735 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1736 [C(LL)] = { 1737 [C(OP_READ)] = { 1738 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1739 GLM_LLC_ACCESS, 1740 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1741 GLM_LLC_MISS, 1742 }, 1743 [C(OP_WRITE)] = { 1744 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1745 GLM_LLC_ACCESS, 1746 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1747 GLM_LLC_MISS, 1748 }, 1749 [C(OP_PREFETCH)] = { 1750 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 1751 GLM_LLC_ACCESS, 1752 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 1753 GLM_LLC_MISS, 1754 }, 1755 }, 1756 }; 1757 1758 static __initconst const u64 glp_hw_cache_event_ids 1759 [PERF_COUNT_HW_CACHE_MAX] 1760 [PERF_COUNT_HW_CACHE_OP_MAX] 1761 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1762 [C(L1D)] = { 1763 [C(OP_READ)] = { 1764 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1765 [C(RESULT_MISS)] = 0x0, 1766 }, 1767 [C(OP_WRITE)] = { 1768 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1769 [C(RESULT_MISS)] = 0x0, 1770 }, 1771 [C(OP_PREFETCH)] = { 1772 [C(RESULT_ACCESS)] = 0x0, 1773 [C(RESULT_MISS)] = 0x0, 1774 }, 1775 }, 1776 [C(L1I)] = { 1777 [C(OP_READ)] = { 1778 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1779 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1780 }, 1781 [C(OP_WRITE)] = { 1782 [C(RESULT_ACCESS)] = -1, 1783 [C(RESULT_MISS)] = -1, 1784 }, 1785 [C(OP_PREFETCH)] = { 1786 [C(RESULT_ACCESS)] = 0x0, 1787 [C(RESULT_MISS)] = 0x0, 1788 }, 1789 }, 1790 [C(LL)] = { 1791 [C(OP_READ)] = { 1792 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1793 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1794 }, 1795 [C(OP_WRITE)] = { 1796 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1797 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1798 }, 1799 [C(OP_PREFETCH)] = { 1800 [C(RESULT_ACCESS)] = 0x0, 1801 [C(RESULT_MISS)] = 0x0, 1802 }, 1803 }, 1804 [C(DTLB)] = { 1805 [C(OP_READ)] = { 1806 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1807 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1808 }, 1809 [C(OP_WRITE)] = { 1810 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1811 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1812 }, 1813 [C(OP_PREFETCH)] = { 1814 [C(RESULT_ACCESS)] = 0x0, 1815 [C(RESULT_MISS)] = 0x0, 1816 }, 1817 }, 1818 [C(ITLB)] = { 1819 [C(OP_READ)] = { 1820 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1821 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1822 }, 1823 [C(OP_WRITE)] = { 1824 [C(RESULT_ACCESS)] = -1, 1825 [C(RESULT_MISS)] = -1, 1826 }, 1827 [C(OP_PREFETCH)] = { 1828 [C(RESULT_ACCESS)] = -1, 1829 [C(RESULT_MISS)] = -1, 1830 }, 1831 }, 1832 [C(BPU)] = { 1833 [C(OP_READ)] = { 1834 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1835 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1836 }, 1837 [C(OP_WRITE)] = { 1838 [C(RESULT_ACCESS)] = -1, 1839 [C(RESULT_MISS)] = -1, 1840 }, 1841 [C(OP_PREFETCH)] = { 1842 [C(RESULT_ACCESS)] = -1, 1843 [C(RESULT_MISS)] = -1, 1844 }, 1845 }, 1846 }; 1847 1848 static __initconst const u64 glp_hw_cache_extra_regs 1849 [PERF_COUNT_HW_CACHE_MAX] 1850 [PERF_COUNT_HW_CACHE_OP_MAX] 1851 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1852 [C(LL)] = { 1853 [C(OP_READ)] = { 1854 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1855 GLM_LLC_ACCESS, 1856 [C(RESULT_MISS)] = GLM_DEMAND_READ| 1857 GLM_LLC_MISS, 1858 }, 1859 [C(OP_WRITE)] = { 1860 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1861 GLM_LLC_ACCESS, 1862 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1863 GLM_LLC_MISS, 1864 }, 1865 [C(OP_PREFETCH)] = { 1866 [C(RESULT_ACCESS)] = 0x0, 1867 [C(RESULT_MISS)] = 0x0, 1868 }, 1869 }, 1870 }; 1871 1872 #define TNT_LOCAL_DRAM BIT_ULL(26) 1873 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 1874 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO 1875 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE 1876 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 1877 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 1878 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 1879 1880 static __initconst const u64 tnt_hw_cache_extra_regs 1881 [PERF_COUNT_HW_CACHE_MAX] 1882 [PERF_COUNT_HW_CACHE_OP_MAX] 1883 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1884 [C(LL)] = { 1885 [C(OP_READ)] = { 1886 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 1887 TNT_LLC_ACCESS, 1888 [C(RESULT_MISS)] = TNT_DEMAND_READ| 1889 TNT_LLC_MISS, 1890 }, 1891 [C(OP_WRITE)] = { 1892 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 1893 TNT_LLC_ACCESS, 1894 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 1895 TNT_LLC_MISS, 1896 }, 1897 [C(OP_PREFETCH)] = { 1898 [C(RESULT_ACCESS)] = 0x0, 1899 [C(RESULT_MISS)] = 0x0, 1900 }, 1901 }, 1902 }; 1903 1904 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 1905 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 1906 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 1907 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 1908 1909 static struct attribute *tnt_events_attrs[] = { 1910 EVENT_PTR(td_fe_bound_tnt), 1911 EVENT_PTR(td_retiring_tnt), 1912 EVENT_PTR(td_bad_spec_tnt), 1913 EVENT_PTR(td_be_bound_tnt), 1914 NULL, 1915 }; 1916 1917 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 1918 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1919 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 1920 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 1921 EVENT_EXTRA_END 1922 }; 1923 1924 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1925 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1926 #define KNL_MCDRAM_LOCAL BIT_ULL(21) 1927 #define KNL_MCDRAM_FAR BIT_ULL(22) 1928 #define KNL_DDR_LOCAL BIT_ULL(23) 1929 #define KNL_DDR_FAR BIT_ULL(24) 1930 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 1931 KNL_DDR_LOCAL | KNL_DDR_FAR) 1932 #define KNL_L2_READ SLM_DMND_READ 1933 #define KNL_L2_WRITE SLM_DMND_WRITE 1934 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH 1935 #define KNL_L2_ACCESS SLM_LLC_ACCESS 1936 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 1937 KNL_DRAM_ANY | SNB_SNP_ANY | \ 1938 SNB_NON_DRAM) 1939 1940 static __initconst const u64 knl_hw_cache_extra_regs 1941 [PERF_COUNT_HW_CACHE_MAX] 1942 [PERF_COUNT_HW_CACHE_OP_MAX] 1943 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1944 [C(LL)] = { 1945 [C(OP_READ)] = { 1946 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 1947 [C(RESULT_MISS)] = 0, 1948 }, 1949 [C(OP_WRITE)] = { 1950 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 1951 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 1952 }, 1953 [C(OP_PREFETCH)] = { 1954 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 1955 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 1956 }, 1957 }, 1958 }; 1959 1960 /* 1961 * Used from PMIs where the LBRs are already disabled. 1962 * 1963 * This function could be called consecutively. It is required to remain in 1964 * disabled state if called consecutively. 1965 * 1966 * During consecutive calls, the same disable value will be written to related 1967 * registers, so the PMU state remains unchanged. 1968 * 1969 * intel_bts events don't coexist with intel PMU's BTS events because of 1970 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 1971 * disabled around intel PMU's event batching etc, only inside the PMI handler. 1972 * 1973 * Avoid PEBS_ENABLE MSR access in PMIs. 1974 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 1975 * It doesn't matter if the PEBS is enabled or not. 1976 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 1977 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 1978 * However, there are some cases which may change PEBS status, e.g. PMI 1979 * throttle. The PEBS_ENABLE should be updated where the status changes. 1980 */ 1981 static void __intel_pmu_disable_all(void) 1982 { 1983 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1984 1985 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 1986 1987 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 1988 intel_pmu_disable_bts(); 1989 } 1990 1991 static void intel_pmu_disable_all(void) 1992 { 1993 __intel_pmu_disable_all(); 1994 intel_pmu_pebs_disable_all(); 1995 intel_pmu_lbr_disable_all(); 1996 } 1997 1998 static void __intel_pmu_enable_all(int added, bool pmi) 1999 { 2000 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2001 2002 intel_pmu_lbr_enable_all(pmi); 2003 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2004 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2005 2006 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2007 struct perf_event *event = 2008 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2009 2010 if (WARN_ON_ONCE(!event)) 2011 return; 2012 2013 intel_pmu_enable_bts(event->hw.config); 2014 } 2015 } 2016 2017 static void intel_pmu_enable_all(int added) 2018 { 2019 intel_pmu_pebs_enable_all(); 2020 __intel_pmu_enable_all(added, false); 2021 } 2022 2023 /* 2024 * Workaround for: 2025 * Intel Errata AAK100 (model 26) 2026 * Intel Errata AAP53 (model 30) 2027 * Intel Errata BD53 (model 44) 2028 * 2029 * The official story: 2030 * These chips need to be 'reset' when adding counters by programming the 2031 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2032 * in sequence on the same PMC or on different PMCs. 2033 * 2034 * In practise it appears some of these events do in fact count, and 2035 * we need to program all 4 events. 2036 */ 2037 static void intel_pmu_nhm_workaround(void) 2038 { 2039 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2040 static const unsigned long nhm_magic[4] = { 2041 0x4300B5, 2042 0x4300D2, 2043 0x4300B1, 2044 0x4300B1 2045 }; 2046 struct perf_event *event; 2047 int i; 2048 2049 /* 2050 * The Errata requires below steps: 2051 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2052 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2053 * the corresponding PMCx; 2054 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2055 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2056 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2057 */ 2058 2059 /* 2060 * The real steps we choose are a little different from above. 2061 * A) To reduce MSR operations, we don't run step 1) as they 2062 * are already cleared before this function is called; 2063 * B) Call x86_perf_event_update to save PMCx before configuring 2064 * PERFEVTSELx with magic number; 2065 * C) With step 5), we do clear only when the PERFEVTSELx is 2066 * not used currently. 2067 * D) Call x86_perf_event_set_period to restore PMCx; 2068 */ 2069 2070 /* We always operate 4 pairs of PERF Counters */ 2071 for (i = 0; i < 4; i++) { 2072 event = cpuc->events[i]; 2073 if (event) 2074 x86_perf_event_update(event); 2075 } 2076 2077 for (i = 0; i < 4; i++) { 2078 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2079 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2080 } 2081 2082 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2083 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2084 2085 for (i = 0; i < 4; i++) { 2086 event = cpuc->events[i]; 2087 2088 if (event) { 2089 x86_perf_event_set_period(event); 2090 __x86_pmu_enable_event(&event->hw, 2091 ARCH_PERFMON_EVENTSEL_ENABLE); 2092 } else 2093 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2094 } 2095 } 2096 2097 static void intel_pmu_nhm_enable_all(int added) 2098 { 2099 if (added) 2100 intel_pmu_nhm_workaround(); 2101 intel_pmu_enable_all(added); 2102 } 2103 2104 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2105 { 2106 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2107 2108 if (cpuc->tfa_shadow != val) { 2109 cpuc->tfa_shadow = val; 2110 wrmsrl(MSR_TSX_FORCE_ABORT, val); 2111 } 2112 } 2113 2114 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2115 { 2116 /* 2117 * We're going to use PMC3, make sure TFA is set before we touch it. 2118 */ 2119 if (cntr == 3) 2120 intel_set_tfa(cpuc, true); 2121 } 2122 2123 static void intel_tfa_pmu_enable_all(int added) 2124 { 2125 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2126 2127 /* 2128 * If we find PMC3 is no longer used when we enable the PMU, we can 2129 * clear TFA. 2130 */ 2131 if (!test_bit(3, cpuc->active_mask)) 2132 intel_set_tfa(cpuc, false); 2133 2134 intel_pmu_enable_all(added); 2135 } 2136 2137 static void enable_counter_freeze(void) 2138 { 2139 update_debugctlmsr(get_debugctlmsr() | 2140 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2141 } 2142 2143 static void disable_counter_freeze(void) 2144 { 2145 update_debugctlmsr(get_debugctlmsr() & 2146 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); 2147 } 2148 2149 static inline u64 intel_pmu_get_status(void) 2150 { 2151 u64 status; 2152 2153 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2154 2155 return status; 2156 } 2157 2158 static inline void intel_pmu_ack_status(u64 ack) 2159 { 2160 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2161 } 2162 2163 static inline bool event_is_checkpointed(struct perf_event *event) 2164 { 2165 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2166 } 2167 2168 static inline void intel_set_masks(struct perf_event *event, int idx) 2169 { 2170 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2171 2172 if (event->attr.exclude_host) 2173 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2174 if (event->attr.exclude_guest) 2175 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2176 if (event_is_checkpointed(event)) 2177 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2178 } 2179 2180 static inline void intel_clear_masks(struct perf_event *event, int idx) 2181 { 2182 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2183 2184 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2185 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2186 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2187 } 2188 2189 static void intel_pmu_disable_fixed(struct perf_event *event) 2190 { 2191 struct hw_perf_event *hwc = &event->hw; 2192 u64 ctrl_val, mask; 2193 int idx = hwc->idx; 2194 2195 if (is_topdown_idx(idx)) { 2196 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2197 2198 /* 2199 * When there are other active TopDown events, 2200 * don't disable the fixed counter 3. 2201 */ 2202 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2203 return; 2204 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2205 } 2206 2207 intel_clear_masks(event, idx); 2208 2209 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4); 2210 rdmsrl(hwc->config_base, ctrl_val); 2211 ctrl_val &= ~mask; 2212 wrmsrl(hwc->config_base, ctrl_val); 2213 } 2214 2215 static void intel_pmu_disable_event(struct perf_event *event) 2216 { 2217 struct hw_perf_event *hwc = &event->hw; 2218 int idx = hwc->idx; 2219 2220 switch (idx) { 2221 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2222 intel_clear_masks(event, idx); 2223 x86_pmu_disable_event(event); 2224 break; 2225 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2226 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2227 intel_pmu_disable_fixed(event); 2228 break; 2229 case INTEL_PMC_IDX_FIXED_BTS: 2230 intel_pmu_disable_bts(); 2231 intel_pmu_drain_bts_buffer(); 2232 return; 2233 case INTEL_PMC_IDX_FIXED_VLBR: 2234 intel_clear_masks(event, idx); 2235 break; 2236 default: 2237 intel_clear_masks(event, idx); 2238 pr_warn("Failed to disable the event with invalid index %d\n", 2239 idx); 2240 return; 2241 } 2242 2243 /* 2244 * Needs to be called after x86_pmu_disable_event, 2245 * so we don't trigger the event without PEBS bit set. 2246 */ 2247 if (unlikely(event->attr.precise_ip)) 2248 intel_pmu_pebs_disable(event); 2249 } 2250 2251 static void intel_pmu_del_event(struct perf_event *event) 2252 { 2253 if (needs_branch_stack(event)) 2254 intel_pmu_lbr_del(event); 2255 if (event->attr.precise_ip) 2256 intel_pmu_pebs_del(event); 2257 } 2258 2259 static int icl_set_topdown_event_period(struct perf_event *event) 2260 { 2261 struct hw_perf_event *hwc = &event->hw; 2262 s64 left = local64_read(&hwc->period_left); 2263 2264 /* 2265 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2266 * Software should start both registers, PERF_METRICS and fixed 2267 * counter 3, from zero. 2268 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2269 * After that, both MSRs will be cleared for each read. 2270 * Don't need to clear them again. 2271 */ 2272 if (left == x86_pmu.max_period) { 2273 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2274 wrmsrl(MSR_PERF_METRICS, 0); 2275 hwc->saved_slots = 0; 2276 hwc->saved_metric = 0; 2277 } 2278 2279 if ((hwc->saved_slots) && is_slots_event(event)) { 2280 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2281 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2282 } 2283 2284 perf_event_update_userpage(event); 2285 2286 return 0; 2287 } 2288 2289 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2290 { 2291 u32 val; 2292 2293 /* 2294 * The metric is reported as an 8bit integer fraction 2295 * suming up to 0xff. 2296 * slots-in-metric = (Metric / 0xff) * slots 2297 */ 2298 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2299 return mul_u64_u32_div(slots, val, 0xff); 2300 } 2301 2302 static u64 icl_get_topdown_value(struct perf_event *event, 2303 u64 slots, u64 metrics) 2304 { 2305 int idx = event->hw.idx; 2306 u64 delta; 2307 2308 if (is_metric_idx(idx)) 2309 delta = icl_get_metrics_event_value(metrics, slots, idx); 2310 else 2311 delta = slots; 2312 2313 return delta; 2314 } 2315 2316 static void __icl_update_topdown_event(struct perf_event *event, 2317 u64 slots, u64 metrics, 2318 u64 last_slots, u64 last_metrics) 2319 { 2320 u64 delta, last = 0; 2321 2322 delta = icl_get_topdown_value(event, slots, metrics); 2323 if (last_slots) 2324 last = icl_get_topdown_value(event, last_slots, last_metrics); 2325 2326 /* 2327 * The 8bit integer fraction of metric may be not accurate, 2328 * especially when the changes is very small. 2329 * For example, if only a few bad_spec happens, the fraction 2330 * may be reduced from 1 to 0. If so, the bad_spec event value 2331 * will be 0 which is definitely less than the last value. 2332 * Avoid update event->count for this case. 2333 */ 2334 if (delta > last) { 2335 delta -= last; 2336 local64_add(delta, &event->count); 2337 } 2338 } 2339 2340 static void update_saved_topdown_regs(struct perf_event *event, 2341 u64 slots, u64 metrics) 2342 { 2343 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2344 struct perf_event *other; 2345 int idx; 2346 2347 event->hw.saved_slots = slots; 2348 event->hw.saved_metric = metrics; 2349 2350 for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) { 2351 if (!is_topdown_idx(idx)) 2352 continue; 2353 other = cpuc->events[idx]; 2354 other->hw.saved_slots = slots; 2355 other->hw.saved_metric = metrics; 2356 } 2357 } 2358 2359 /* 2360 * Update all active Topdown events. 2361 * 2362 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2363 * modify by a NMI. PMU has to be disabled before calling this function. 2364 */ 2365 static u64 icl_update_topdown_event(struct perf_event *event) 2366 { 2367 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2368 struct perf_event *other; 2369 u64 slots, metrics; 2370 bool reset = true; 2371 int idx; 2372 2373 /* read Fixed counter 3 */ 2374 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2375 if (!slots) 2376 return 0; 2377 2378 /* read PERF_METRICS */ 2379 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2380 2381 for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) { 2382 if (!is_topdown_idx(idx)) 2383 continue; 2384 other = cpuc->events[idx]; 2385 __icl_update_topdown_event(other, slots, metrics, 2386 event ? event->hw.saved_slots : 0, 2387 event ? event->hw.saved_metric : 0); 2388 } 2389 2390 /* 2391 * Check and update this event, which may have been cleared 2392 * in active_mask e.g. x86_pmu_stop() 2393 */ 2394 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2395 __icl_update_topdown_event(event, slots, metrics, 2396 event->hw.saved_slots, 2397 event->hw.saved_metric); 2398 2399 /* 2400 * In x86_pmu_stop(), the event is cleared in active_mask first, 2401 * then drain the delta, which indicates context switch for 2402 * counting. 2403 * Save metric and slots for context switch. 2404 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2405 * Because the values will be restored in next schedule in. 2406 */ 2407 update_saved_topdown_regs(event, slots, metrics); 2408 reset = false; 2409 } 2410 2411 if (reset) { 2412 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2413 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2414 wrmsrl(MSR_PERF_METRICS, 0); 2415 if (event) 2416 update_saved_topdown_regs(event, 0, 0); 2417 } 2418 2419 return slots; 2420 } 2421 2422 static void intel_pmu_read_topdown_event(struct perf_event *event) 2423 { 2424 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2425 2426 /* Only need to call update_topdown_event() once for group read. */ 2427 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && 2428 !is_slots_event(event)) 2429 return; 2430 2431 perf_pmu_disable(event->pmu); 2432 x86_pmu.update_topdown_event(event); 2433 perf_pmu_enable(event->pmu); 2434 } 2435 2436 static void intel_pmu_read_event(struct perf_event *event) 2437 { 2438 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) 2439 intel_pmu_auto_reload_read(event); 2440 else if (is_topdown_count(event) && x86_pmu.update_topdown_event) 2441 intel_pmu_read_topdown_event(event); 2442 else 2443 x86_perf_event_update(event); 2444 } 2445 2446 static void intel_pmu_enable_fixed(struct perf_event *event) 2447 { 2448 struct hw_perf_event *hwc = &event->hw; 2449 u64 ctrl_val, mask, bits = 0; 2450 int idx = hwc->idx; 2451 2452 if (is_topdown_idx(idx)) { 2453 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2454 /* 2455 * When there are other active TopDown events, 2456 * don't enable the fixed counter 3 again. 2457 */ 2458 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2459 return; 2460 2461 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2462 } 2463 2464 intel_set_masks(event, idx); 2465 2466 /* 2467 * Enable IRQ generation (0x8), if not PEBS, 2468 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2469 * if requested: 2470 */ 2471 if (!event->attr.precise_ip) 2472 bits |= 0x8; 2473 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2474 bits |= 0x2; 2475 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2476 bits |= 0x1; 2477 2478 /* 2479 * ANY bit is supported in v3 and up 2480 */ 2481 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2482 bits |= 0x4; 2483 2484 idx -= INTEL_PMC_IDX_FIXED; 2485 bits <<= (idx * 4); 2486 mask = 0xfULL << (idx * 4); 2487 2488 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2489 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2490 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); 2491 } 2492 2493 rdmsrl(hwc->config_base, ctrl_val); 2494 ctrl_val &= ~mask; 2495 ctrl_val |= bits; 2496 wrmsrl(hwc->config_base, ctrl_val); 2497 } 2498 2499 static void intel_pmu_enable_event(struct perf_event *event) 2500 { 2501 struct hw_perf_event *hwc = &event->hw; 2502 int idx = hwc->idx; 2503 2504 if (unlikely(event->attr.precise_ip)) 2505 intel_pmu_pebs_enable(event); 2506 2507 switch (idx) { 2508 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2509 intel_set_masks(event, idx); 2510 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 2511 break; 2512 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2513 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2514 intel_pmu_enable_fixed(event); 2515 break; 2516 case INTEL_PMC_IDX_FIXED_BTS: 2517 if (!__this_cpu_read(cpu_hw_events.enabled)) 2518 return; 2519 intel_pmu_enable_bts(hwc->config); 2520 break; 2521 case INTEL_PMC_IDX_FIXED_VLBR: 2522 intel_set_masks(event, idx); 2523 break; 2524 default: 2525 pr_warn("Failed to enable the event with invalid index %d\n", 2526 idx); 2527 } 2528 } 2529 2530 static void intel_pmu_add_event(struct perf_event *event) 2531 { 2532 if (event->attr.precise_ip) 2533 intel_pmu_pebs_add(event); 2534 if (needs_branch_stack(event)) 2535 intel_pmu_lbr_add(event); 2536 } 2537 2538 /* 2539 * Save and restart an expired event. Called by NMI contexts, 2540 * so it has to be careful about preempting normal event ops: 2541 */ 2542 int intel_pmu_save_and_restart(struct perf_event *event) 2543 { 2544 x86_perf_event_update(event); 2545 /* 2546 * For a checkpointed counter always reset back to 0. This 2547 * avoids a situation where the counter overflows, aborts the 2548 * transaction and is then set back to shortly before the 2549 * overflow, and overflows and aborts again. 2550 */ 2551 if (unlikely(event_is_checkpointed(event))) { 2552 /* No race with NMIs because the counter should not be armed */ 2553 wrmsrl(event->hw.event_base, 0); 2554 local64_set(&event->hw.prev_count, 0); 2555 } 2556 return x86_perf_event_set_period(event); 2557 } 2558 2559 static void intel_pmu_reset(void) 2560 { 2561 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 2562 unsigned long flags; 2563 int idx; 2564 2565 if (!x86_pmu.num_counters) 2566 return; 2567 2568 local_irq_save(flags); 2569 2570 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2571 2572 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 2573 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2574 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2575 } 2576 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) 2577 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); 2578 2579 if (ds) 2580 ds->bts_index = ds->bts_buffer_base; 2581 2582 /* Ack all overflows and disable fixed counters */ 2583 if (x86_pmu.version >= 2) { 2584 intel_pmu_ack_status(intel_pmu_get_status()); 2585 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2586 } 2587 2588 /* Reset LBRs and LBR freezing */ 2589 if (x86_pmu.lbr_nr) { 2590 update_debugctlmsr(get_debugctlmsr() & 2591 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 2592 } 2593 2594 local_irq_restore(flags); 2595 } 2596 2597 static int handle_pmi_common(struct pt_regs *regs, u64 status) 2598 { 2599 struct perf_sample_data data; 2600 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2601 int bit; 2602 int handled = 0; 2603 2604 inc_irq_stat(apic_perf_irqs); 2605 2606 /* 2607 * Ignore a range of extra bits in status that do not indicate 2608 * overflow by themselves. 2609 */ 2610 status &= ~(GLOBAL_STATUS_COND_CHG | 2611 GLOBAL_STATUS_ASIF | 2612 GLOBAL_STATUS_LBRS_FROZEN); 2613 if (!status) 2614 return 0; 2615 /* 2616 * In case multiple PEBS events are sampled at the same time, 2617 * it is possible to have GLOBAL_STATUS bit 62 set indicating 2618 * PEBS buffer overflow and also seeing at most 3 PEBS counters 2619 * having their bits set in the status register. This is a sign 2620 * that there was at least one PEBS record pending at the time 2621 * of the PMU interrupt. PEBS counters must only be processed 2622 * via the drain_pebs() calls and not via the regular sample 2623 * processing loop coming after that the function, otherwise 2624 * phony regular samples may be generated in the sampling buffer 2625 * not marked with the EXACT tag. Another possibility is to have 2626 * one PEBS event and at least one non-PEBS event whic hoverflows 2627 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 2628 * not be set, yet the overflow status bit for the PEBS counter will 2629 * be on Skylake. 2630 * 2631 * To avoid this problem, we systematically ignore the PEBS-enabled 2632 * counters from the GLOBAL_STATUS mask and we always process PEBS 2633 * events via drain_pebs(). 2634 */ 2635 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 2636 status &= ~cpuc->pebs_enabled; 2637 else 2638 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 2639 2640 /* 2641 * PEBS overflow sets bit 62 in the global status register 2642 */ 2643 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 2644 u64 pebs_enabled = cpuc->pebs_enabled; 2645 2646 handled++; 2647 x86_pmu.drain_pebs(regs, &data); 2648 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI; 2649 2650 /* 2651 * PMI throttle may be triggered, which stops the PEBS event. 2652 * Although cpuc->pebs_enabled is updated accordingly, the 2653 * MSR_IA32_PEBS_ENABLE is not updated. Because the 2654 * cpuc->enabled has been forced to 0 in PMI. 2655 * Update the MSR if pebs_enabled is changed. 2656 */ 2657 if (pebs_enabled != cpuc->pebs_enabled) 2658 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 2659 } 2660 2661 /* 2662 * Intel PT 2663 */ 2664 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 2665 handled++; 2666 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() && 2667 perf_guest_cbs->handle_intel_pt_intr)) 2668 perf_guest_cbs->handle_intel_pt_intr(); 2669 else 2670 intel_pt_interrupt(); 2671 } 2672 2673 /* 2674 * Intel Perf mertrics 2675 */ 2676 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 2677 handled++; 2678 if (x86_pmu.update_topdown_event) 2679 x86_pmu.update_topdown_event(NULL); 2680 } 2681 2682 /* 2683 * Checkpointed counters can lead to 'spurious' PMIs because the 2684 * rollback caused by the PMI will have cleared the overflow status 2685 * bit. Therefore always force probe these counters. 2686 */ 2687 status |= cpuc->intel_cp_status; 2688 2689 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 2690 struct perf_event *event = cpuc->events[bit]; 2691 2692 handled++; 2693 2694 if (!test_bit(bit, cpuc->active_mask)) 2695 continue; 2696 2697 if (!intel_pmu_save_and_restart(event)) 2698 continue; 2699 2700 perf_sample_data_init(&data, 0, event->hw.last_period); 2701 2702 if (has_branch_stack(event)) 2703 data.br_stack = &cpuc->lbr_stack; 2704 2705 if (perf_event_overflow(event, &data, regs)) 2706 x86_pmu_stop(event, 0); 2707 } 2708 2709 return handled; 2710 } 2711 2712 static bool disable_counter_freezing = true; 2713 static int __init intel_perf_counter_freezing_setup(char *s) 2714 { 2715 bool res; 2716 2717 if (kstrtobool(s, &res)) 2718 return -EINVAL; 2719 2720 disable_counter_freezing = !res; 2721 return 1; 2722 } 2723 __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup); 2724 2725 /* 2726 * Simplified handler for Arch Perfmon v4: 2727 * - We rely on counter freezing/unfreezing to enable/disable the PMU. 2728 * This is done automatically on PMU ack. 2729 * - Ack the PMU only after the APIC. 2730 */ 2731 2732 static int intel_pmu_handle_irq_v4(struct pt_regs *regs) 2733 { 2734 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2735 int handled = 0; 2736 bool bts = false; 2737 u64 status; 2738 int pmu_enabled = cpuc->enabled; 2739 int loops = 0; 2740 2741 /* PMU has been disabled because of counter freezing */ 2742 cpuc->enabled = 0; 2743 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2744 bts = true; 2745 intel_bts_disable_local(); 2746 handled = intel_pmu_drain_bts_buffer(); 2747 handled += intel_bts_interrupt(); 2748 } 2749 status = intel_pmu_get_status(); 2750 if (!status) 2751 goto done; 2752 again: 2753 intel_pmu_lbr_read(); 2754 if (++loops > 100) { 2755 static bool warned; 2756 2757 if (!warned) { 2758 WARN(1, "perfevents: irq loop stuck!\n"); 2759 perf_event_print_debug(); 2760 warned = true; 2761 } 2762 intel_pmu_reset(); 2763 goto done; 2764 } 2765 2766 2767 handled += handle_pmi_common(regs, status); 2768 done: 2769 /* Ack the PMI in the APIC */ 2770 apic_write(APIC_LVTPC, APIC_DM_NMI); 2771 2772 /* 2773 * The counters start counting immediately while ack the status. 2774 * Make it as close as possible to IRET. This avoids bogus 2775 * freezing on Skylake CPUs. 2776 */ 2777 if (status) { 2778 intel_pmu_ack_status(status); 2779 } else { 2780 /* 2781 * CPU may issues two PMIs very close to each other. 2782 * When the PMI handler services the first one, the 2783 * GLOBAL_STATUS is already updated to reflect both. 2784 * When it IRETs, the second PMI is immediately 2785 * handled and it sees clear status. At the meantime, 2786 * there may be a third PMI, because the freezing bit 2787 * isn't set since the ack in first PMI handlers. 2788 * Double check if there is more work to be done. 2789 */ 2790 status = intel_pmu_get_status(); 2791 if (status) 2792 goto again; 2793 } 2794 2795 if (bts) 2796 intel_bts_enable_local(); 2797 cpuc->enabled = pmu_enabled; 2798 return handled; 2799 } 2800 2801 /* 2802 * This handler is triggered by the local APIC, so the APIC IRQ handling 2803 * rules apply: 2804 */ 2805 static int intel_pmu_handle_irq(struct pt_regs *regs) 2806 { 2807 struct cpu_hw_events *cpuc; 2808 int loops; 2809 u64 status; 2810 int handled; 2811 int pmu_enabled; 2812 2813 cpuc = this_cpu_ptr(&cpu_hw_events); 2814 2815 /* 2816 * Save the PMU state. 2817 * It needs to be restored when leaving the handler. 2818 */ 2819 pmu_enabled = cpuc->enabled; 2820 /* 2821 * No known reason to not always do late ACK, 2822 * but just in case do it opt-in. 2823 */ 2824 if (!x86_pmu.late_ack) 2825 apic_write(APIC_LVTPC, APIC_DM_NMI); 2826 intel_bts_disable_local(); 2827 cpuc->enabled = 0; 2828 __intel_pmu_disable_all(); 2829 handled = intel_pmu_drain_bts_buffer(); 2830 handled += intel_bts_interrupt(); 2831 status = intel_pmu_get_status(); 2832 if (!status) 2833 goto done; 2834 2835 loops = 0; 2836 again: 2837 intel_pmu_lbr_read(); 2838 intel_pmu_ack_status(status); 2839 if (++loops > 100) { 2840 static bool warned; 2841 2842 if (!warned) { 2843 WARN(1, "perfevents: irq loop stuck!\n"); 2844 perf_event_print_debug(); 2845 warned = true; 2846 } 2847 intel_pmu_reset(); 2848 goto done; 2849 } 2850 2851 handled += handle_pmi_common(regs, status); 2852 2853 /* 2854 * Repeat if there is more work to be done: 2855 */ 2856 status = intel_pmu_get_status(); 2857 if (status) 2858 goto again; 2859 2860 done: 2861 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 2862 cpuc->enabled = pmu_enabled; 2863 if (pmu_enabled) 2864 __intel_pmu_enable_all(0, true); 2865 intel_bts_enable_local(); 2866 2867 /* 2868 * Only unmask the NMI after the overflow counters 2869 * have been reset. This avoids spurious NMIs on 2870 * Haswell CPUs. 2871 */ 2872 if (x86_pmu.late_ack) 2873 apic_write(APIC_LVTPC, APIC_DM_NMI); 2874 return handled; 2875 } 2876 2877 static struct event_constraint * 2878 intel_bts_constraints(struct perf_event *event) 2879 { 2880 if (unlikely(intel_pmu_has_bts(event))) 2881 return &bts_constraint; 2882 2883 return NULL; 2884 } 2885 2886 /* 2887 * Note: matches a fake event, like Fixed2. 2888 */ 2889 static struct event_constraint * 2890 intel_vlbr_constraints(struct perf_event *event) 2891 { 2892 struct event_constraint *c = &vlbr_constraint; 2893 2894 if (unlikely(constraint_match(c, event->hw.config))) 2895 return c; 2896 2897 return NULL; 2898 } 2899 2900 static int intel_alt_er(int idx, u64 config) 2901 { 2902 int alt_idx = idx; 2903 2904 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 2905 return idx; 2906 2907 if (idx == EXTRA_REG_RSP_0) 2908 alt_idx = EXTRA_REG_RSP_1; 2909 2910 if (idx == EXTRA_REG_RSP_1) 2911 alt_idx = EXTRA_REG_RSP_0; 2912 2913 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask) 2914 return idx; 2915 2916 return alt_idx; 2917 } 2918 2919 static void intel_fixup_er(struct perf_event *event, int idx) 2920 { 2921 event->hw.extra_reg.idx = idx; 2922 2923 if (idx == EXTRA_REG_RSP_0) { 2924 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2925 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; 2926 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 2927 } else if (idx == EXTRA_REG_RSP_1) { 2928 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 2929 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; 2930 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 2931 } 2932 } 2933 2934 /* 2935 * manage allocation of shared extra msr for certain events 2936 * 2937 * sharing can be: 2938 * per-cpu: to be shared between the various events on a single PMU 2939 * per-core: per-cpu + shared by HT threads 2940 */ 2941 static struct event_constraint * 2942 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 2943 struct perf_event *event, 2944 struct hw_perf_event_extra *reg) 2945 { 2946 struct event_constraint *c = &emptyconstraint; 2947 struct er_account *era; 2948 unsigned long flags; 2949 int idx = reg->idx; 2950 2951 /* 2952 * reg->alloc can be set due to existing state, so for fake cpuc we 2953 * need to ignore this, otherwise we might fail to allocate proper fake 2954 * state for this extra reg constraint. Also see the comment below. 2955 */ 2956 if (reg->alloc && !cpuc->is_fake) 2957 return NULL; /* call x86_get_event_constraint() */ 2958 2959 again: 2960 era = &cpuc->shared_regs->regs[idx]; 2961 /* 2962 * we use spin_lock_irqsave() to avoid lockdep issues when 2963 * passing a fake cpuc 2964 */ 2965 raw_spin_lock_irqsave(&era->lock, flags); 2966 2967 if (!atomic_read(&era->ref) || era->config == reg->config) { 2968 2969 /* 2970 * If its a fake cpuc -- as per validate_{group,event}() we 2971 * shouldn't touch event state and we can avoid doing so 2972 * since both will only call get_event_constraints() once 2973 * on each event, this avoids the need for reg->alloc. 2974 * 2975 * Not doing the ER fixup will only result in era->reg being 2976 * wrong, but since we won't actually try and program hardware 2977 * this isn't a problem either. 2978 */ 2979 if (!cpuc->is_fake) { 2980 if (idx != reg->idx) 2981 intel_fixup_er(event, idx); 2982 2983 /* 2984 * x86_schedule_events() can call get_event_constraints() 2985 * multiple times on events in the case of incremental 2986 * scheduling(). reg->alloc ensures we only do the ER 2987 * allocation once. 2988 */ 2989 reg->alloc = 1; 2990 } 2991 2992 /* lock in msr value */ 2993 era->config = reg->config; 2994 era->reg = reg->reg; 2995 2996 /* one more user */ 2997 atomic_inc(&era->ref); 2998 2999 /* 3000 * need to call x86_get_event_constraint() 3001 * to check if associated event has constraints 3002 */ 3003 c = NULL; 3004 } else { 3005 idx = intel_alt_er(idx, reg->config); 3006 if (idx != reg->idx) { 3007 raw_spin_unlock_irqrestore(&era->lock, flags); 3008 goto again; 3009 } 3010 } 3011 raw_spin_unlock_irqrestore(&era->lock, flags); 3012 3013 return c; 3014 } 3015 3016 static void 3017 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3018 struct hw_perf_event_extra *reg) 3019 { 3020 struct er_account *era; 3021 3022 /* 3023 * Only put constraint if extra reg was actually allocated. Also takes 3024 * care of event which do not use an extra shared reg. 3025 * 3026 * Also, if this is a fake cpuc we shouldn't touch any event state 3027 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3028 * either since it'll be thrown out. 3029 */ 3030 if (!reg->alloc || cpuc->is_fake) 3031 return; 3032 3033 era = &cpuc->shared_regs->regs[reg->idx]; 3034 3035 /* one fewer user */ 3036 atomic_dec(&era->ref); 3037 3038 /* allocate again next time */ 3039 reg->alloc = 0; 3040 } 3041 3042 static struct event_constraint * 3043 intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3044 struct perf_event *event) 3045 { 3046 struct event_constraint *c = NULL, *d; 3047 struct hw_perf_event_extra *xreg, *breg; 3048 3049 xreg = &event->hw.extra_reg; 3050 if (xreg->idx != EXTRA_REG_NONE) { 3051 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3052 if (c == &emptyconstraint) 3053 return c; 3054 } 3055 breg = &event->hw.branch_reg; 3056 if (breg->idx != EXTRA_REG_NONE) { 3057 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3058 if (d == &emptyconstraint) { 3059 __intel_shared_reg_put_constraints(cpuc, xreg); 3060 c = d; 3061 } 3062 } 3063 return c; 3064 } 3065 3066 struct event_constraint * 3067 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3068 struct perf_event *event) 3069 { 3070 struct event_constraint *c; 3071 3072 if (x86_pmu.event_constraints) { 3073 for_each_event_constraint(c, x86_pmu.event_constraints) { 3074 if (constraint_match(c, event->hw.config)) { 3075 event->hw.flags |= c->flags; 3076 return c; 3077 } 3078 } 3079 } 3080 3081 return &unconstrained; 3082 } 3083 3084 static struct event_constraint * 3085 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3086 struct perf_event *event) 3087 { 3088 struct event_constraint *c; 3089 3090 c = intel_vlbr_constraints(event); 3091 if (c) 3092 return c; 3093 3094 c = intel_bts_constraints(event); 3095 if (c) 3096 return c; 3097 3098 c = intel_shared_regs_constraints(cpuc, event); 3099 if (c) 3100 return c; 3101 3102 c = intel_pebs_constraints(event); 3103 if (c) 3104 return c; 3105 3106 return x86_get_event_constraints(cpuc, idx, event); 3107 } 3108 3109 static void 3110 intel_start_scheduling(struct cpu_hw_events *cpuc) 3111 { 3112 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3113 struct intel_excl_states *xl; 3114 int tid = cpuc->excl_thread_id; 3115 3116 /* 3117 * nothing needed if in group validation mode 3118 */ 3119 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3120 return; 3121 3122 /* 3123 * no exclusion needed 3124 */ 3125 if (WARN_ON_ONCE(!excl_cntrs)) 3126 return; 3127 3128 xl = &excl_cntrs->states[tid]; 3129 3130 xl->sched_started = true; 3131 /* 3132 * lock shared state until we are done scheduling 3133 * in stop_event_scheduling() 3134 * makes scheduling appear as a transaction 3135 */ 3136 raw_spin_lock(&excl_cntrs->lock); 3137 } 3138 3139 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3140 { 3141 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3142 struct event_constraint *c = cpuc->event_constraint[idx]; 3143 struct intel_excl_states *xl; 3144 int tid = cpuc->excl_thread_id; 3145 3146 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3147 return; 3148 3149 if (WARN_ON_ONCE(!excl_cntrs)) 3150 return; 3151 3152 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3153 return; 3154 3155 xl = &excl_cntrs->states[tid]; 3156 3157 lockdep_assert_held(&excl_cntrs->lock); 3158 3159 if (c->flags & PERF_X86_EVENT_EXCL) 3160 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3161 else 3162 xl->state[cntr] = INTEL_EXCL_SHARED; 3163 } 3164 3165 static void 3166 intel_stop_scheduling(struct cpu_hw_events *cpuc) 3167 { 3168 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3169 struct intel_excl_states *xl; 3170 int tid = cpuc->excl_thread_id; 3171 3172 /* 3173 * nothing needed if in group validation mode 3174 */ 3175 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3176 return; 3177 /* 3178 * no exclusion needed 3179 */ 3180 if (WARN_ON_ONCE(!excl_cntrs)) 3181 return; 3182 3183 xl = &excl_cntrs->states[tid]; 3184 3185 xl->sched_started = false; 3186 /* 3187 * release shared state lock (acquired in intel_start_scheduling()) 3188 */ 3189 raw_spin_unlock(&excl_cntrs->lock); 3190 } 3191 3192 static struct event_constraint * 3193 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3194 { 3195 WARN_ON_ONCE(!cpuc->constraint_list); 3196 3197 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3198 struct event_constraint *cx; 3199 3200 /* 3201 * grab pre-allocated constraint entry 3202 */ 3203 cx = &cpuc->constraint_list[idx]; 3204 3205 /* 3206 * initialize dynamic constraint 3207 * with static constraint 3208 */ 3209 *cx = *c; 3210 3211 /* 3212 * mark constraint as dynamic 3213 */ 3214 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3215 c = cx; 3216 } 3217 3218 return c; 3219 } 3220 3221 static struct event_constraint * 3222 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3223 int idx, struct event_constraint *c) 3224 { 3225 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3226 struct intel_excl_states *xlo; 3227 int tid = cpuc->excl_thread_id; 3228 int is_excl, i, w; 3229 3230 /* 3231 * validating a group does not require 3232 * enforcing cross-thread exclusion 3233 */ 3234 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3235 return c; 3236 3237 /* 3238 * no exclusion needed 3239 */ 3240 if (WARN_ON_ONCE(!excl_cntrs)) 3241 return c; 3242 3243 /* 3244 * because we modify the constraint, we need 3245 * to make a copy. Static constraints come 3246 * from static const tables. 3247 * 3248 * only needed when constraint has not yet 3249 * been cloned (marked dynamic) 3250 */ 3251 c = dyn_constraint(cpuc, c, idx); 3252 3253 /* 3254 * From here on, the constraint is dynamic. 3255 * Either it was just allocated above, or it 3256 * was allocated during a earlier invocation 3257 * of this function 3258 */ 3259 3260 /* 3261 * state of sibling HT 3262 */ 3263 xlo = &excl_cntrs->states[tid ^ 1]; 3264 3265 /* 3266 * event requires exclusive counter access 3267 * across HT threads 3268 */ 3269 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3270 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3271 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3272 if (!cpuc->n_excl++) 3273 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3274 } 3275 3276 /* 3277 * Modify static constraint with current dynamic 3278 * state of thread 3279 * 3280 * EXCLUSIVE: sibling counter measuring exclusive event 3281 * SHARED : sibling counter measuring non-exclusive event 3282 * UNUSED : sibling counter unused 3283 */ 3284 w = c->weight; 3285 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3286 /* 3287 * exclusive event in sibling counter 3288 * our corresponding counter cannot be used 3289 * regardless of our event 3290 */ 3291 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3292 __clear_bit(i, c->idxmsk); 3293 w--; 3294 continue; 3295 } 3296 /* 3297 * if measuring an exclusive event, sibling 3298 * measuring non-exclusive, then counter cannot 3299 * be used 3300 */ 3301 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3302 __clear_bit(i, c->idxmsk); 3303 w--; 3304 continue; 3305 } 3306 } 3307 3308 /* 3309 * if we return an empty mask, then switch 3310 * back to static empty constraint to avoid 3311 * the cost of freeing later on 3312 */ 3313 if (!w) 3314 c = &emptyconstraint; 3315 3316 c->weight = w; 3317 3318 return c; 3319 } 3320 3321 static struct event_constraint * 3322 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3323 struct perf_event *event) 3324 { 3325 struct event_constraint *c1, *c2; 3326 3327 c1 = cpuc->event_constraint[idx]; 3328 3329 /* 3330 * first time only 3331 * - static constraint: no change across incremental scheduling calls 3332 * - dynamic constraint: handled by intel_get_excl_constraints() 3333 */ 3334 c2 = __intel_get_event_constraints(cpuc, idx, event); 3335 if (c1) { 3336 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3337 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3338 c1->weight = c2->weight; 3339 c2 = c1; 3340 } 3341 3342 if (cpuc->excl_cntrs) 3343 return intel_get_excl_constraints(cpuc, event, idx, c2); 3344 3345 return c2; 3346 } 3347 3348 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3349 struct perf_event *event) 3350 { 3351 struct hw_perf_event *hwc = &event->hw; 3352 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3353 int tid = cpuc->excl_thread_id; 3354 struct intel_excl_states *xl; 3355 3356 /* 3357 * nothing needed if in group validation mode 3358 */ 3359 if (cpuc->is_fake) 3360 return; 3361 3362 if (WARN_ON_ONCE(!excl_cntrs)) 3363 return; 3364 3365 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 3366 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 3367 if (!--cpuc->n_excl) 3368 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 3369 } 3370 3371 /* 3372 * If event was actually assigned, then mark the counter state as 3373 * unused now. 3374 */ 3375 if (hwc->idx >= 0) { 3376 xl = &excl_cntrs->states[tid]; 3377 3378 /* 3379 * put_constraint may be called from x86_schedule_events() 3380 * which already has the lock held so here make locking 3381 * conditional. 3382 */ 3383 if (!xl->sched_started) 3384 raw_spin_lock(&excl_cntrs->lock); 3385 3386 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 3387 3388 if (!xl->sched_started) 3389 raw_spin_unlock(&excl_cntrs->lock); 3390 } 3391 } 3392 3393 static void 3394 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 3395 struct perf_event *event) 3396 { 3397 struct hw_perf_event_extra *reg; 3398 3399 reg = &event->hw.extra_reg; 3400 if (reg->idx != EXTRA_REG_NONE) 3401 __intel_shared_reg_put_constraints(cpuc, reg); 3402 3403 reg = &event->hw.branch_reg; 3404 if (reg->idx != EXTRA_REG_NONE) 3405 __intel_shared_reg_put_constraints(cpuc, reg); 3406 } 3407 3408 static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 3409 struct perf_event *event) 3410 { 3411 intel_put_shared_regs_event_constraints(cpuc, event); 3412 3413 /* 3414 * is PMU has exclusive counter restrictions, then 3415 * all events are subject to and must call the 3416 * put_excl_constraints() routine 3417 */ 3418 if (cpuc->excl_cntrs) 3419 intel_put_excl_constraints(cpuc, event); 3420 } 3421 3422 static void intel_pebs_aliases_core2(struct perf_event *event) 3423 { 3424 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3425 /* 3426 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3427 * (0x003c) so that we can use it with PEBS. 3428 * 3429 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3430 * PEBS capable. However we can use INST_RETIRED.ANY_P 3431 * (0x00c0), which is a PEBS capable event, to get the same 3432 * count. 3433 * 3434 * INST_RETIRED.ANY_P counts the number of cycles that retires 3435 * CNTMASK instructions. By setting CNTMASK to a value (16) 3436 * larger than the maximum number of instructions that can be 3437 * retired per cycle (4) and then inverting the condition, we 3438 * count all cycles that retire 16 or less instructions, which 3439 * is every cycle. 3440 * 3441 * Thereby we gain a PEBS capable cycle counter. 3442 */ 3443 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 3444 3445 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3446 event->hw.config = alt_config; 3447 } 3448 } 3449 3450 static void intel_pebs_aliases_snb(struct perf_event *event) 3451 { 3452 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3453 /* 3454 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3455 * (0x003c) so that we can use it with PEBS. 3456 * 3457 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3458 * PEBS capable. However we can use UOPS_RETIRED.ALL 3459 * (0x01c2), which is a PEBS capable event, to get the same 3460 * count. 3461 * 3462 * UOPS_RETIRED.ALL counts the number of cycles that retires 3463 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 3464 * larger than the maximum number of micro-ops that can be 3465 * retired per cycle (4) and then inverting the condition, we 3466 * count all cycles that retire 16 or less micro-ops, which 3467 * is every cycle. 3468 * 3469 * Thereby we gain a PEBS capable cycle counter. 3470 */ 3471 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 3472 3473 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3474 event->hw.config = alt_config; 3475 } 3476 } 3477 3478 static void intel_pebs_aliases_precdist(struct perf_event *event) 3479 { 3480 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 3481 /* 3482 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 3483 * (0x003c) so that we can use it with PEBS. 3484 * 3485 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 3486 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 3487 * (0x01c0), which is a PEBS capable event, to get the same 3488 * count. 3489 * 3490 * The PREC_DIST event has special support to minimize sample 3491 * shadowing effects. One drawback is that it can be 3492 * only programmed on counter 1, but that seems like an 3493 * acceptable trade off. 3494 */ 3495 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 3496 3497 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 3498 event->hw.config = alt_config; 3499 } 3500 } 3501 3502 static void intel_pebs_aliases_ivb(struct perf_event *event) 3503 { 3504 if (event->attr.precise_ip < 3) 3505 return intel_pebs_aliases_snb(event); 3506 return intel_pebs_aliases_precdist(event); 3507 } 3508 3509 static void intel_pebs_aliases_skl(struct perf_event *event) 3510 { 3511 if (event->attr.precise_ip < 3) 3512 return intel_pebs_aliases_core2(event); 3513 return intel_pebs_aliases_precdist(event); 3514 } 3515 3516 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 3517 { 3518 unsigned long flags = x86_pmu.large_pebs_flags; 3519 3520 if (event->attr.use_clockid) 3521 flags &= ~PERF_SAMPLE_TIME; 3522 if (!event->attr.exclude_kernel) 3523 flags &= ~PERF_SAMPLE_REGS_USER; 3524 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 3525 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR); 3526 return flags; 3527 } 3528 3529 static int intel_pmu_bts_config(struct perf_event *event) 3530 { 3531 struct perf_event_attr *attr = &event->attr; 3532 3533 if (unlikely(intel_pmu_has_bts(event))) { 3534 /* BTS is not supported by this architecture. */ 3535 if (!x86_pmu.bts_active) 3536 return -EOPNOTSUPP; 3537 3538 /* BTS is currently only allowed for user-mode. */ 3539 if (!attr->exclude_kernel) 3540 return -EOPNOTSUPP; 3541 3542 /* BTS is not allowed for precise events. */ 3543 if (attr->precise_ip) 3544 return -EOPNOTSUPP; 3545 3546 /* disallow bts if conflicting events are present */ 3547 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3548 return -EBUSY; 3549 3550 event->destroy = hw_perf_lbr_event_destroy; 3551 } 3552 3553 return 0; 3554 } 3555 3556 static int core_pmu_hw_config(struct perf_event *event) 3557 { 3558 int ret = x86_pmu_hw_config(event); 3559 3560 if (ret) 3561 return ret; 3562 3563 return intel_pmu_bts_config(event); 3564 } 3565 3566 static int intel_pmu_hw_config(struct perf_event *event) 3567 { 3568 int ret = x86_pmu_hw_config(event); 3569 3570 if (ret) 3571 return ret; 3572 3573 ret = intel_pmu_bts_config(event); 3574 if (ret) 3575 return ret; 3576 3577 if (event->attr.precise_ip) { 3578 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 3579 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 3580 if (!(event->attr.sample_type & 3581 ~intel_pmu_large_pebs_flags(event))) 3582 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 3583 } 3584 if (x86_pmu.pebs_aliases) 3585 x86_pmu.pebs_aliases(event); 3586 3587 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) 3588 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY; 3589 } 3590 3591 if (needs_branch_stack(event)) { 3592 ret = intel_pmu_setup_lbr_filter(event); 3593 if (ret) 3594 return ret; 3595 3596 /* 3597 * BTS is set up earlier in this path, so don't account twice 3598 */ 3599 if (!unlikely(intel_pmu_has_bts(event))) { 3600 /* disallow lbr if conflicting events are present */ 3601 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 3602 return -EBUSY; 3603 3604 event->destroy = hw_perf_lbr_event_destroy; 3605 } 3606 } 3607 3608 if (event->attr.aux_output) { 3609 if (!event->attr.precise_ip) 3610 return -EINVAL; 3611 3612 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 3613 } 3614 3615 if (event->attr.type != PERF_TYPE_RAW) 3616 return 0; 3617 3618 /* 3619 * Config Topdown slots and metric events 3620 * 3621 * The slots event on Fixed Counter 3 can support sampling, 3622 * which will be handled normally in x86_perf_event_update(). 3623 * 3624 * Metric events don't support sampling and require being paired 3625 * with a slots event as group leader. When the slots event 3626 * is used in a metrics group, it too cannot support sampling. 3627 */ 3628 if (x86_pmu.intel_cap.perf_metrics && is_topdown_event(event)) { 3629 if (event->attr.config1 || event->attr.config2) 3630 return -EINVAL; 3631 3632 /* 3633 * The TopDown metrics events and slots event don't 3634 * support any filters. 3635 */ 3636 if (event->attr.config & X86_ALL_EVENT_FLAGS) 3637 return -EINVAL; 3638 3639 if (is_metric_event(event)) { 3640 struct perf_event *leader = event->group_leader; 3641 3642 /* The metric events don't support sampling. */ 3643 if (is_sampling_event(event)) 3644 return -EINVAL; 3645 3646 /* The metric events require a slots group leader. */ 3647 if (!is_slots_event(leader)) 3648 return -EINVAL; 3649 3650 /* 3651 * The leader/SLOTS must not be a sampling event for 3652 * metric use; hardware requires it starts at 0 when used 3653 * in conjunction with MSR_PERF_METRICS. 3654 */ 3655 if (is_sampling_event(leader)) 3656 return -EINVAL; 3657 3658 event->event_caps |= PERF_EV_CAP_SIBLING; 3659 /* 3660 * Only once we have a METRICs sibling do we 3661 * need TopDown magic. 3662 */ 3663 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3664 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 3665 } 3666 } 3667 3668 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 3669 return 0; 3670 3671 if (x86_pmu.version < 3) 3672 return -EINVAL; 3673 3674 ret = perf_allow_cpu(&event->attr); 3675 if (ret) 3676 return ret; 3677 3678 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 3679 3680 return 0; 3681 } 3682 3683 #ifdef CONFIG_RETPOLINE 3684 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr); 3685 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr); 3686 #endif 3687 3688 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) 3689 { 3690 #ifdef CONFIG_RETPOLINE 3691 if (x86_pmu.guest_get_msrs == intel_guest_get_msrs) 3692 return intel_guest_get_msrs(nr); 3693 else if (x86_pmu.guest_get_msrs == core_guest_get_msrs) 3694 return core_guest_get_msrs(nr); 3695 #endif 3696 if (x86_pmu.guest_get_msrs) 3697 return x86_pmu.guest_get_msrs(nr); 3698 *nr = 0; 3699 return NULL; 3700 } 3701 EXPORT_SYMBOL_GPL(perf_guest_get_msrs); 3702 3703 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) 3704 { 3705 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3706 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3707 3708 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; 3709 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; 3710 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; 3711 if (x86_pmu.flags & PMU_FL_PEBS_ALL) 3712 arr[0].guest &= ~cpuc->pebs_enabled; 3713 else 3714 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK); 3715 *nr = 1; 3716 3717 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) { 3718 /* 3719 * If PMU counter has PEBS enabled it is not enough to 3720 * disable counter on a guest entry since PEBS memory 3721 * write can overshoot guest entry and corrupt guest 3722 * memory. Disabling PEBS solves the problem. 3723 * 3724 * Don't do this if the CPU already enforces it. 3725 */ 3726 arr[1].msr = MSR_IA32_PEBS_ENABLE; 3727 arr[1].host = cpuc->pebs_enabled; 3728 arr[1].guest = 0; 3729 *nr = 2; 3730 } 3731 3732 return arr; 3733 } 3734 3735 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) 3736 { 3737 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3738 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 3739 int idx; 3740 3741 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3742 struct perf_event *event = cpuc->events[idx]; 3743 3744 arr[idx].msr = x86_pmu_config_addr(idx); 3745 arr[idx].host = arr[idx].guest = 0; 3746 3747 if (!test_bit(idx, cpuc->active_mask)) 3748 continue; 3749 3750 arr[idx].host = arr[idx].guest = 3751 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 3752 3753 if (event->attr.exclude_host) 3754 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3755 else if (event->attr.exclude_guest) 3756 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 3757 } 3758 3759 *nr = x86_pmu.num_counters; 3760 return arr; 3761 } 3762 3763 static void core_pmu_enable_event(struct perf_event *event) 3764 { 3765 if (!event->attr.exclude_host) 3766 x86_pmu_enable_event(event); 3767 } 3768 3769 static void core_pmu_enable_all(int added) 3770 { 3771 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3772 int idx; 3773 3774 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 3775 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 3776 3777 if (!test_bit(idx, cpuc->active_mask) || 3778 cpuc->events[idx]->attr.exclude_host) 3779 continue; 3780 3781 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 3782 } 3783 } 3784 3785 static int hsw_hw_config(struct perf_event *event) 3786 { 3787 int ret = intel_pmu_hw_config(event); 3788 3789 if (ret) 3790 return ret; 3791 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 3792 return 0; 3793 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 3794 3795 /* 3796 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 3797 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 3798 * this combination. 3799 */ 3800 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 3801 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 3802 event->attr.precise_ip > 0)) 3803 return -EOPNOTSUPP; 3804 3805 if (event_is_checkpointed(event)) { 3806 /* 3807 * Sampling of checkpointed events can cause situations where 3808 * the CPU constantly aborts because of a overflow, which is 3809 * then checkpointed back and ignored. Forbid checkpointing 3810 * for sampling. 3811 * 3812 * But still allow a long sampling period, so that perf stat 3813 * from KVM works. 3814 */ 3815 if (event->attr.sample_period > 0 && 3816 event->attr.sample_period < 0x7fffffff) 3817 return -EOPNOTSUPP; 3818 } 3819 return 0; 3820 } 3821 3822 static struct event_constraint counter0_constraint = 3823 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3824 3825 static struct event_constraint counter2_constraint = 3826 EVENT_CONSTRAINT(0, 0x4, 0); 3827 3828 static struct event_constraint fixed0_constraint = 3829 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 3830 3831 static struct event_constraint fixed0_counter0_constraint = 3832 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 3833 3834 static struct event_constraint * 3835 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3836 struct perf_event *event) 3837 { 3838 struct event_constraint *c; 3839 3840 c = intel_get_event_constraints(cpuc, idx, event); 3841 3842 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 3843 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 3844 if (c->idxmsk64 & (1U << 2)) 3845 return &counter2_constraint; 3846 return &emptyconstraint; 3847 } 3848 3849 return c; 3850 } 3851 3852 static struct event_constraint * 3853 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3854 struct perf_event *event) 3855 { 3856 /* 3857 * Fixed counter 0 has less skid. 3858 * Force instruction:ppp in Fixed counter 0 3859 */ 3860 if ((event->attr.precise_ip == 3) && 3861 constraint_match(&fixed0_constraint, event->hw.config)) 3862 return &fixed0_constraint; 3863 3864 return hsw_get_event_constraints(cpuc, idx, event); 3865 } 3866 3867 static struct event_constraint * 3868 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3869 struct perf_event *event) 3870 { 3871 struct event_constraint *c; 3872 3873 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3874 if (event->attr.precise_ip == 3) 3875 return &counter0_constraint; 3876 3877 c = intel_get_event_constraints(cpuc, idx, event); 3878 3879 return c; 3880 } 3881 3882 static struct event_constraint * 3883 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3884 struct perf_event *event) 3885 { 3886 struct event_constraint *c; 3887 3888 /* 3889 * :ppp means to do reduced skid PEBS, 3890 * which is available on PMC0 and fixed counter 0. 3891 */ 3892 if (event->attr.precise_ip == 3) { 3893 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 3894 if (constraint_match(&fixed0_constraint, event->hw.config)) 3895 return &fixed0_counter0_constraint; 3896 3897 return &counter0_constraint; 3898 } 3899 3900 c = intel_get_event_constraints(cpuc, idx, event); 3901 3902 return c; 3903 } 3904 3905 static bool allow_tsx_force_abort = true; 3906 3907 static struct event_constraint * 3908 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3909 struct perf_event *event) 3910 { 3911 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 3912 3913 /* 3914 * Without TFA we must not use PMC3. 3915 */ 3916 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 3917 c = dyn_constraint(cpuc, c, idx); 3918 c->idxmsk64 &= ~(1ULL << 3); 3919 c->weight--; 3920 } 3921 3922 return c; 3923 } 3924 3925 /* 3926 * Broadwell: 3927 * 3928 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 3929 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 3930 * the two to enforce a minimum period of 128 (the smallest value that has bits 3931 * 0-5 cleared and >= 100). 3932 * 3933 * Because of how the code in x86_perf_event_set_period() works, the truncation 3934 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 3935 * to make up for the 'lost' events due to carrying the 'error' in period_left. 3936 * 3937 * Therefore the effective (average) period matches the requested period, 3938 * despite coarser hardware granularity. 3939 */ 3940 static u64 bdw_limit_period(struct perf_event *event, u64 left) 3941 { 3942 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == 3943 X86_CONFIG(.event=0xc0, .umask=0x01)) { 3944 if (left < 128) 3945 left = 128; 3946 left &= ~0x3fULL; 3947 } 3948 return left; 3949 } 3950 3951 static u64 nhm_limit_period(struct perf_event *event, u64 left) 3952 { 3953 return max(left, 32ULL); 3954 } 3955 3956 PMU_FORMAT_ATTR(event, "config:0-7" ); 3957 PMU_FORMAT_ATTR(umask, "config:8-15" ); 3958 PMU_FORMAT_ATTR(edge, "config:18" ); 3959 PMU_FORMAT_ATTR(pc, "config:19" ); 3960 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 3961 PMU_FORMAT_ATTR(inv, "config:23" ); 3962 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 3963 PMU_FORMAT_ATTR(in_tx, "config:32"); 3964 PMU_FORMAT_ATTR(in_tx_cp, "config:33"); 3965 3966 static struct attribute *intel_arch_formats_attr[] = { 3967 &format_attr_event.attr, 3968 &format_attr_umask.attr, 3969 &format_attr_edge.attr, 3970 &format_attr_pc.attr, 3971 &format_attr_inv.attr, 3972 &format_attr_cmask.attr, 3973 NULL, 3974 }; 3975 3976 ssize_t intel_event_sysfs_show(char *page, u64 config) 3977 { 3978 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 3979 3980 return x86_event_sysfs_show(page, config, event); 3981 } 3982 3983 static struct intel_shared_regs *allocate_shared_regs(int cpu) 3984 { 3985 struct intel_shared_regs *regs; 3986 int i; 3987 3988 regs = kzalloc_node(sizeof(struct intel_shared_regs), 3989 GFP_KERNEL, cpu_to_node(cpu)); 3990 if (regs) { 3991 /* 3992 * initialize the locks to keep lockdep happy 3993 */ 3994 for (i = 0; i < EXTRA_REG_MAX; i++) 3995 raw_spin_lock_init(®s->regs[i].lock); 3996 3997 regs->core_id = -1; 3998 } 3999 return regs; 4000 } 4001 4002 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 4003 { 4004 struct intel_excl_cntrs *c; 4005 4006 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 4007 GFP_KERNEL, cpu_to_node(cpu)); 4008 if (c) { 4009 raw_spin_lock_init(&c->lock); 4010 c->core_id = -1; 4011 } 4012 return c; 4013 } 4014 4015 4016 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 4017 { 4018 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 4019 4020 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 4021 cpuc->shared_regs = allocate_shared_regs(cpu); 4022 if (!cpuc->shared_regs) 4023 goto err; 4024 } 4025 4026 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { 4027 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 4028 4029 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 4030 if (!cpuc->constraint_list) 4031 goto err_shared_regs; 4032 } 4033 4034 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4035 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 4036 if (!cpuc->excl_cntrs) 4037 goto err_constraint_list; 4038 4039 cpuc->excl_thread_id = 0; 4040 } 4041 4042 return 0; 4043 4044 err_constraint_list: 4045 kfree(cpuc->constraint_list); 4046 cpuc->constraint_list = NULL; 4047 4048 err_shared_regs: 4049 kfree(cpuc->shared_regs); 4050 cpuc->shared_regs = NULL; 4051 4052 err: 4053 return -ENOMEM; 4054 } 4055 4056 static int intel_pmu_cpu_prepare(int cpu) 4057 { 4058 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 4059 } 4060 4061 static void flip_smm_bit(void *data) 4062 { 4063 unsigned long set = *(unsigned long *)data; 4064 4065 if (set > 0) { 4066 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 4067 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4068 } else { 4069 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 4070 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 4071 } 4072 } 4073 4074 static void intel_pmu_cpu_starting(int cpu) 4075 { 4076 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 4077 int core_id = topology_core_id(cpu); 4078 int i; 4079 4080 init_debug_store_on_cpu(cpu); 4081 /* 4082 * Deal with CPUs that don't clear their LBRs on power-up. 4083 */ 4084 intel_pmu_lbr_reset(); 4085 4086 cpuc->lbr_sel = NULL; 4087 4088 if (x86_pmu.flags & PMU_FL_TFA) { 4089 WARN_ON_ONCE(cpuc->tfa_shadow); 4090 cpuc->tfa_shadow = ~0ULL; 4091 intel_set_tfa(cpuc, false); 4092 } 4093 4094 if (x86_pmu.version > 1) 4095 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 4096 4097 if (x86_pmu.counter_freezing) 4098 enable_counter_freeze(); 4099 4100 /* Disable perf metrics if any added CPU doesn't support it. */ 4101 if (x86_pmu.intel_cap.perf_metrics) { 4102 union perf_capabilities perf_cap; 4103 4104 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 4105 if (!perf_cap.perf_metrics) { 4106 x86_pmu.intel_cap.perf_metrics = 0; 4107 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 4108 } 4109 } 4110 4111 if (!cpuc->shared_regs) 4112 return; 4113 4114 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 4115 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4116 struct intel_shared_regs *pc; 4117 4118 pc = per_cpu(cpu_hw_events, i).shared_regs; 4119 if (pc && pc->core_id == core_id) { 4120 cpuc->kfree_on_online[0] = cpuc->shared_regs; 4121 cpuc->shared_regs = pc; 4122 break; 4123 } 4124 } 4125 cpuc->shared_regs->core_id = core_id; 4126 cpuc->shared_regs->refcnt++; 4127 } 4128 4129 if (x86_pmu.lbr_sel_map) 4130 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 4131 4132 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 4133 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 4134 struct cpu_hw_events *sibling; 4135 struct intel_excl_cntrs *c; 4136 4137 sibling = &per_cpu(cpu_hw_events, i); 4138 c = sibling->excl_cntrs; 4139 if (c && c->core_id == core_id) { 4140 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 4141 cpuc->excl_cntrs = c; 4142 if (!sibling->excl_thread_id) 4143 cpuc->excl_thread_id = 1; 4144 break; 4145 } 4146 } 4147 cpuc->excl_cntrs->core_id = core_id; 4148 cpuc->excl_cntrs->refcnt++; 4149 } 4150 } 4151 4152 static void free_excl_cntrs(struct cpu_hw_events *cpuc) 4153 { 4154 struct intel_excl_cntrs *c; 4155 4156 c = cpuc->excl_cntrs; 4157 if (c) { 4158 if (c->core_id == -1 || --c->refcnt == 0) 4159 kfree(c); 4160 cpuc->excl_cntrs = NULL; 4161 } 4162 4163 kfree(cpuc->constraint_list); 4164 cpuc->constraint_list = NULL; 4165 } 4166 4167 static void intel_pmu_cpu_dying(int cpu) 4168 { 4169 fini_debug_store_on_cpu(cpu); 4170 4171 if (x86_pmu.counter_freezing) 4172 disable_counter_freeze(); 4173 } 4174 4175 void intel_cpuc_finish(struct cpu_hw_events *cpuc) 4176 { 4177 struct intel_shared_regs *pc; 4178 4179 pc = cpuc->shared_regs; 4180 if (pc) { 4181 if (pc->core_id == -1 || --pc->refcnt == 0) 4182 kfree(pc); 4183 cpuc->shared_regs = NULL; 4184 } 4185 4186 free_excl_cntrs(cpuc); 4187 } 4188 4189 static void intel_pmu_cpu_dead(int cpu) 4190 { 4191 intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu)); 4192 } 4193 4194 static void intel_pmu_sched_task(struct perf_event_context *ctx, 4195 bool sched_in) 4196 { 4197 intel_pmu_pebs_sched_task(ctx, sched_in); 4198 intel_pmu_lbr_sched_task(ctx, sched_in); 4199 } 4200 4201 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev, 4202 struct perf_event_context *next) 4203 { 4204 intel_pmu_lbr_swap_task_ctx(prev, next); 4205 } 4206 4207 static int intel_pmu_check_period(struct perf_event *event, u64 value) 4208 { 4209 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 4210 } 4211 4212 static int intel_pmu_aux_output_match(struct perf_event *event) 4213 { 4214 if (!x86_pmu.intel_cap.pebs_output_pt_available) 4215 return 0; 4216 4217 return is_intel_pt_event(event); 4218 } 4219 4220 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 4221 4222 PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 4223 4224 PMU_FORMAT_ATTR(frontend, "config1:0-23"); 4225 4226 static struct attribute *intel_arch3_formats_attr[] = { 4227 &format_attr_event.attr, 4228 &format_attr_umask.attr, 4229 &format_attr_edge.attr, 4230 &format_attr_pc.attr, 4231 &format_attr_any.attr, 4232 &format_attr_inv.attr, 4233 &format_attr_cmask.attr, 4234 NULL, 4235 }; 4236 4237 static struct attribute *hsw_format_attr[] = { 4238 &format_attr_in_tx.attr, 4239 &format_attr_in_tx_cp.attr, 4240 &format_attr_offcore_rsp.attr, 4241 &format_attr_ldlat.attr, 4242 NULL 4243 }; 4244 4245 static struct attribute *nhm_format_attr[] = { 4246 &format_attr_offcore_rsp.attr, 4247 &format_attr_ldlat.attr, 4248 NULL 4249 }; 4250 4251 static struct attribute *slm_format_attr[] = { 4252 &format_attr_offcore_rsp.attr, 4253 NULL 4254 }; 4255 4256 static struct attribute *skl_format_attr[] = { 4257 &format_attr_frontend.attr, 4258 NULL, 4259 }; 4260 4261 static __initconst const struct x86_pmu core_pmu = { 4262 .name = "core", 4263 .handle_irq = x86_pmu_handle_irq, 4264 .disable_all = x86_pmu_disable_all, 4265 .enable_all = core_pmu_enable_all, 4266 .enable = core_pmu_enable_event, 4267 .disable = x86_pmu_disable_event, 4268 .hw_config = core_pmu_hw_config, 4269 .schedule_events = x86_schedule_events, 4270 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4271 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4272 .event_map = intel_pmu_event_map, 4273 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4274 .apic = 1, 4275 .large_pebs_flags = LARGE_PEBS_FLAGS, 4276 4277 /* 4278 * Intel PMCs cannot be accessed sanely above 32-bit width, 4279 * so we install an artificial 1<<31 period regardless of 4280 * the generic event period: 4281 */ 4282 .max_period = (1ULL<<31) - 1, 4283 .get_event_constraints = intel_get_event_constraints, 4284 .put_event_constraints = intel_put_event_constraints, 4285 .event_constraints = intel_core_event_constraints, 4286 .guest_get_msrs = core_guest_get_msrs, 4287 .format_attrs = intel_arch_formats_attr, 4288 .events_sysfs_show = intel_event_sysfs_show, 4289 4290 /* 4291 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 4292 * together with PMU version 1 and thus be using core_pmu with 4293 * shared_regs. We need following callbacks here to allocate 4294 * it properly. 4295 */ 4296 .cpu_prepare = intel_pmu_cpu_prepare, 4297 .cpu_starting = intel_pmu_cpu_starting, 4298 .cpu_dying = intel_pmu_cpu_dying, 4299 .cpu_dead = intel_pmu_cpu_dead, 4300 4301 .check_period = intel_pmu_check_period, 4302 4303 .lbr_reset = intel_pmu_lbr_reset_64, 4304 .lbr_read = intel_pmu_lbr_read_64, 4305 .lbr_save = intel_pmu_lbr_save, 4306 .lbr_restore = intel_pmu_lbr_restore, 4307 }; 4308 4309 static __initconst const struct x86_pmu intel_pmu = { 4310 .name = "Intel", 4311 .handle_irq = intel_pmu_handle_irq, 4312 .disable_all = intel_pmu_disable_all, 4313 .enable_all = intel_pmu_enable_all, 4314 .enable = intel_pmu_enable_event, 4315 .disable = intel_pmu_disable_event, 4316 .add = intel_pmu_add_event, 4317 .del = intel_pmu_del_event, 4318 .read = intel_pmu_read_event, 4319 .hw_config = intel_pmu_hw_config, 4320 .schedule_events = x86_schedule_events, 4321 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 4322 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 4323 .event_map = intel_pmu_event_map, 4324 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 4325 .apic = 1, 4326 .large_pebs_flags = LARGE_PEBS_FLAGS, 4327 /* 4328 * Intel PMCs cannot be accessed sanely above 32 bit width, 4329 * so we install an artificial 1<<31 period regardless of 4330 * the generic event period: 4331 */ 4332 .max_period = (1ULL << 31) - 1, 4333 .get_event_constraints = intel_get_event_constraints, 4334 .put_event_constraints = intel_put_event_constraints, 4335 .pebs_aliases = intel_pebs_aliases_core2, 4336 4337 .format_attrs = intel_arch3_formats_attr, 4338 .events_sysfs_show = intel_event_sysfs_show, 4339 4340 .cpu_prepare = intel_pmu_cpu_prepare, 4341 .cpu_starting = intel_pmu_cpu_starting, 4342 .cpu_dying = intel_pmu_cpu_dying, 4343 .cpu_dead = intel_pmu_cpu_dead, 4344 4345 .guest_get_msrs = intel_guest_get_msrs, 4346 .sched_task = intel_pmu_sched_task, 4347 .swap_task_ctx = intel_pmu_swap_task_ctx, 4348 4349 .check_period = intel_pmu_check_period, 4350 4351 .aux_output_match = intel_pmu_aux_output_match, 4352 4353 .lbr_reset = intel_pmu_lbr_reset_64, 4354 .lbr_read = intel_pmu_lbr_read_64, 4355 .lbr_save = intel_pmu_lbr_save, 4356 .lbr_restore = intel_pmu_lbr_restore, 4357 }; 4358 4359 static __init void intel_clovertown_quirk(void) 4360 { 4361 /* 4362 * PEBS is unreliable due to: 4363 * 4364 * AJ67 - PEBS may experience CPL leaks 4365 * AJ68 - PEBS PMI may be delayed by one event 4366 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 4367 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 4368 * 4369 * AJ67 could be worked around by restricting the OS/USR flags. 4370 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 4371 * 4372 * AJ106 could possibly be worked around by not allowing LBR 4373 * usage from PEBS, including the fixup. 4374 * AJ68 could possibly be worked around by always programming 4375 * a pebs_event_reset[0] value and coping with the lost events. 4376 * 4377 * But taken together it might just make sense to not enable PEBS on 4378 * these chips. 4379 */ 4380 pr_warn("PEBS disabled due to CPU errata\n"); 4381 x86_pmu.pebs = 0; 4382 x86_pmu.pebs_constraints = NULL; 4383 } 4384 4385 static const struct x86_cpu_desc isolation_ucodes[] = { 4386 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f), 4387 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e), 4388 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015), 4389 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037), 4390 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a), 4391 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023), 4392 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014), 4393 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010), 4394 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009), 4395 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009), 4396 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002), 4397 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014), 4398 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021), 4399 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000), 4400 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c), 4401 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c), 4402 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e), 4403 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e), 4404 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e), 4405 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e), 4406 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e), 4407 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e), 4408 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e), 4409 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e), 4410 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e), 4411 {} 4412 }; 4413 4414 static void intel_check_pebs_isolation(void) 4415 { 4416 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes); 4417 } 4418 4419 static __init void intel_pebs_isolation_quirk(void) 4420 { 4421 WARN_ON_ONCE(x86_pmu.check_microcode); 4422 x86_pmu.check_microcode = intel_check_pebs_isolation; 4423 intel_check_pebs_isolation(); 4424 } 4425 4426 static const struct x86_cpu_desc pebs_ucodes[] = { 4427 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028), 4428 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618), 4429 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c), 4430 {} 4431 }; 4432 4433 static bool intel_snb_pebs_broken(void) 4434 { 4435 return !x86_cpu_has_min_microcode_rev(pebs_ucodes); 4436 } 4437 4438 static void intel_snb_check_microcode(void) 4439 { 4440 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 4441 return; 4442 4443 /* 4444 * Serialized by the microcode lock.. 4445 */ 4446 if (x86_pmu.pebs_broken) { 4447 pr_info("PEBS enabled due to microcode update\n"); 4448 x86_pmu.pebs_broken = 0; 4449 } else { 4450 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 4451 x86_pmu.pebs_broken = 1; 4452 } 4453 } 4454 4455 static bool is_lbr_from(unsigned long msr) 4456 { 4457 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 4458 4459 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 4460 } 4461 4462 /* 4463 * Under certain circumstances, access certain MSR may cause #GP. 4464 * The function tests if the input MSR can be safely accessed. 4465 */ 4466 static bool check_msr(unsigned long msr, u64 mask) 4467 { 4468 u64 val_old, val_new, val_tmp; 4469 4470 /* 4471 * Disable the check for real HW, so we don't 4472 * mess with potentionaly enabled registers: 4473 */ 4474 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 4475 return true; 4476 4477 /* 4478 * Read the current value, change it and read it back to see if it 4479 * matches, this is needed to detect certain hardware emulators 4480 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 4481 */ 4482 if (rdmsrl_safe(msr, &val_old)) 4483 return false; 4484 4485 /* 4486 * Only change the bits which can be updated by wrmsrl. 4487 */ 4488 val_tmp = val_old ^ mask; 4489 4490 if (is_lbr_from(msr)) 4491 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 4492 4493 if (wrmsrl_safe(msr, val_tmp) || 4494 rdmsrl_safe(msr, &val_new)) 4495 return false; 4496 4497 /* 4498 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 4499 * should equal rdmsrl()'s even with the quirk. 4500 */ 4501 if (val_new != val_tmp) 4502 return false; 4503 4504 if (is_lbr_from(msr)) 4505 val_old = lbr_from_signext_quirk_wr(val_old); 4506 4507 /* Here it's sure that the MSR can be safely accessed. 4508 * Restore the old value and return. 4509 */ 4510 wrmsrl(msr, val_old); 4511 4512 return true; 4513 } 4514 4515 static __init void intel_sandybridge_quirk(void) 4516 { 4517 x86_pmu.check_microcode = intel_snb_check_microcode; 4518 cpus_read_lock(); 4519 intel_snb_check_microcode(); 4520 cpus_read_unlock(); 4521 } 4522 4523 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 4524 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 4525 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 4526 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 4527 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 4528 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 4529 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 4530 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 4531 }; 4532 4533 static __init void intel_arch_events_quirk(void) 4534 { 4535 int bit; 4536 4537 /* disable event that reported as not presend by cpuid */ 4538 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 4539 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 4540 pr_warn("CPUID marked event: \'%s\' unavailable\n", 4541 intel_arch_events_map[bit].name); 4542 } 4543 } 4544 4545 static __init void intel_nehalem_quirk(void) 4546 { 4547 union cpuid10_ebx ebx; 4548 4549 ebx.full = x86_pmu.events_maskl; 4550 if (ebx.split.no_branch_misses_retired) { 4551 /* 4552 * Erratum AAJ80 detected, we work it around by using 4553 * the BR_MISP_EXEC.ANY event. This will over-count 4554 * branch-misses, but it's still much better than the 4555 * architectural event which is often completely bogus: 4556 */ 4557 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 4558 ebx.split.no_branch_misses_retired = 0; 4559 x86_pmu.events_maskl = ebx.full; 4560 pr_info("CPU erratum AAJ80 worked around\n"); 4561 } 4562 } 4563 4564 static const struct x86_cpu_desc counter_freezing_ucodes[] = { 4565 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e), 4566 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e), 4567 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008), 4568 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028), 4569 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028), 4570 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006), 4571 {} 4572 }; 4573 4574 static bool intel_counter_freezing_broken(void) 4575 { 4576 return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes); 4577 } 4578 4579 static __init void intel_counter_freezing_quirk(void) 4580 { 4581 /* Check if it's already disabled */ 4582 if (disable_counter_freezing) 4583 return; 4584 4585 /* 4586 * If the system starts with the wrong ucode, leave the 4587 * counter-freezing feature permanently disabled. 4588 */ 4589 if (intel_counter_freezing_broken()) { 4590 pr_info("PMU counter freezing disabled due to CPU errata," 4591 "please upgrade microcode\n"); 4592 x86_pmu.counter_freezing = false; 4593 x86_pmu.handle_irq = intel_pmu_handle_irq; 4594 } 4595 } 4596 4597 /* 4598 * enable software workaround for errata: 4599 * SNB: BJ122 4600 * IVB: BV98 4601 * HSW: HSD29 4602 * 4603 * Only needed when HT is enabled. However detecting 4604 * if HT is enabled is difficult (model specific). So instead, 4605 * we enable the workaround in the early boot, and verify if 4606 * it is needed in a later initcall phase once we have valid 4607 * topology information to check if HT is actually enabled 4608 */ 4609 static __init void intel_ht_bug(void) 4610 { 4611 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 4612 4613 x86_pmu.start_scheduling = intel_start_scheduling; 4614 x86_pmu.commit_scheduling = intel_commit_scheduling; 4615 x86_pmu.stop_scheduling = intel_stop_scheduling; 4616 } 4617 4618 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 4619 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 4620 4621 /* Haswell special events */ 4622 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 4623 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 4624 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 4625 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 4626 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 4627 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 4628 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 4629 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 4630 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 4631 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 4632 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 4633 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 4634 4635 static struct attribute *hsw_events_attrs[] = { 4636 EVENT_PTR(td_slots_issued), 4637 EVENT_PTR(td_slots_retired), 4638 EVENT_PTR(td_fetch_bubbles), 4639 EVENT_PTR(td_total_slots), 4640 EVENT_PTR(td_total_slots_scale), 4641 EVENT_PTR(td_recovery_bubbles), 4642 EVENT_PTR(td_recovery_bubbles_scale), 4643 NULL 4644 }; 4645 4646 static struct attribute *hsw_mem_events_attrs[] = { 4647 EVENT_PTR(mem_ld_hsw), 4648 EVENT_PTR(mem_st_hsw), 4649 NULL, 4650 }; 4651 4652 static struct attribute *hsw_tsx_events_attrs[] = { 4653 EVENT_PTR(tx_start), 4654 EVENT_PTR(tx_commit), 4655 EVENT_PTR(tx_abort), 4656 EVENT_PTR(tx_capacity), 4657 EVENT_PTR(tx_conflict), 4658 EVENT_PTR(el_start), 4659 EVENT_PTR(el_commit), 4660 EVENT_PTR(el_abort), 4661 EVENT_PTR(el_capacity), 4662 EVENT_PTR(el_conflict), 4663 EVENT_PTR(cycles_t), 4664 EVENT_PTR(cycles_ct), 4665 NULL 4666 }; 4667 4668 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 4669 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 4670 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 4671 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 4672 4673 static struct attribute *icl_events_attrs[] = { 4674 EVENT_PTR(mem_ld_hsw), 4675 EVENT_PTR(mem_st_hsw), 4676 NULL, 4677 }; 4678 4679 static struct attribute *icl_td_events_attrs[] = { 4680 EVENT_PTR(slots), 4681 EVENT_PTR(td_retiring), 4682 EVENT_PTR(td_bad_spec), 4683 EVENT_PTR(td_fe_bound), 4684 EVENT_PTR(td_be_bound), 4685 NULL, 4686 }; 4687 4688 static struct attribute *icl_tsx_events_attrs[] = { 4689 EVENT_PTR(tx_start), 4690 EVENT_PTR(tx_abort), 4691 EVENT_PTR(tx_commit), 4692 EVENT_PTR(tx_capacity_read), 4693 EVENT_PTR(tx_capacity_write), 4694 EVENT_PTR(tx_conflict), 4695 EVENT_PTR(el_start), 4696 EVENT_PTR(el_abort), 4697 EVENT_PTR(el_commit), 4698 EVENT_PTR(el_capacity_read), 4699 EVENT_PTR(el_capacity_write), 4700 EVENT_PTR(el_conflict), 4701 EVENT_PTR(cycles_t), 4702 EVENT_PTR(cycles_ct), 4703 NULL, 4704 }; 4705 4706 static ssize_t freeze_on_smi_show(struct device *cdev, 4707 struct device_attribute *attr, 4708 char *buf) 4709 { 4710 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 4711 } 4712 4713 static DEFINE_MUTEX(freeze_on_smi_mutex); 4714 4715 static ssize_t freeze_on_smi_store(struct device *cdev, 4716 struct device_attribute *attr, 4717 const char *buf, size_t count) 4718 { 4719 unsigned long val; 4720 ssize_t ret; 4721 4722 ret = kstrtoul(buf, 0, &val); 4723 if (ret) 4724 return ret; 4725 4726 if (val > 1) 4727 return -EINVAL; 4728 4729 mutex_lock(&freeze_on_smi_mutex); 4730 4731 if (x86_pmu.attr_freeze_on_smi == val) 4732 goto done; 4733 4734 x86_pmu.attr_freeze_on_smi = val; 4735 4736 get_online_cpus(); 4737 on_each_cpu(flip_smm_bit, &val, 1); 4738 put_online_cpus(); 4739 done: 4740 mutex_unlock(&freeze_on_smi_mutex); 4741 4742 return count; 4743 } 4744 4745 static void update_tfa_sched(void *ignored) 4746 { 4747 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4748 4749 /* 4750 * check if PMC3 is used 4751 * and if so force schedule out for all event types all contexts 4752 */ 4753 if (test_bit(3, cpuc->active_mask)) 4754 perf_pmu_resched(x86_get_pmu()); 4755 } 4756 4757 static ssize_t show_sysctl_tfa(struct device *cdev, 4758 struct device_attribute *attr, 4759 char *buf) 4760 { 4761 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 4762 } 4763 4764 static ssize_t set_sysctl_tfa(struct device *cdev, 4765 struct device_attribute *attr, 4766 const char *buf, size_t count) 4767 { 4768 bool val; 4769 ssize_t ret; 4770 4771 ret = kstrtobool(buf, &val); 4772 if (ret) 4773 return ret; 4774 4775 /* no change */ 4776 if (val == allow_tsx_force_abort) 4777 return count; 4778 4779 allow_tsx_force_abort = val; 4780 4781 get_online_cpus(); 4782 on_each_cpu(update_tfa_sched, NULL, 1); 4783 put_online_cpus(); 4784 4785 return count; 4786 } 4787 4788 4789 static DEVICE_ATTR_RW(freeze_on_smi); 4790 4791 static ssize_t branches_show(struct device *cdev, 4792 struct device_attribute *attr, 4793 char *buf) 4794 { 4795 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 4796 } 4797 4798 static DEVICE_ATTR_RO(branches); 4799 4800 static struct attribute *lbr_attrs[] = { 4801 &dev_attr_branches.attr, 4802 NULL 4803 }; 4804 4805 static char pmu_name_str[30]; 4806 4807 static ssize_t pmu_name_show(struct device *cdev, 4808 struct device_attribute *attr, 4809 char *buf) 4810 { 4811 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str); 4812 } 4813 4814 static DEVICE_ATTR_RO(pmu_name); 4815 4816 static struct attribute *intel_pmu_caps_attrs[] = { 4817 &dev_attr_pmu_name.attr, 4818 NULL 4819 }; 4820 4821 static DEVICE_ATTR(allow_tsx_force_abort, 0644, 4822 show_sysctl_tfa, 4823 set_sysctl_tfa); 4824 4825 static struct attribute *intel_pmu_attrs[] = { 4826 &dev_attr_freeze_on_smi.attr, 4827 &dev_attr_allow_tsx_force_abort.attr, 4828 NULL, 4829 }; 4830 4831 static umode_t 4832 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4833 { 4834 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 4835 } 4836 4837 static umode_t 4838 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4839 { 4840 return x86_pmu.pebs ? attr->mode : 0; 4841 } 4842 4843 static umode_t 4844 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4845 { 4846 return x86_pmu.lbr_nr ? attr->mode : 0; 4847 } 4848 4849 static umode_t 4850 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4851 { 4852 return x86_pmu.version >= 2 ? attr->mode : 0; 4853 } 4854 4855 static umode_t 4856 default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 4857 { 4858 if (attr == &dev_attr_allow_tsx_force_abort.attr) 4859 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 4860 4861 return attr->mode; 4862 } 4863 4864 static struct attribute_group group_events_td = { 4865 .name = "events", 4866 }; 4867 4868 static struct attribute_group group_events_mem = { 4869 .name = "events", 4870 .is_visible = pebs_is_visible, 4871 }; 4872 4873 static struct attribute_group group_events_tsx = { 4874 .name = "events", 4875 .is_visible = tsx_is_visible, 4876 }; 4877 4878 static struct attribute_group group_caps_gen = { 4879 .name = "caps", 4880 .attrs = intel_pmu_caps_attrs, 4881 }; 4882 4883 static struct attribute_group group_caps_lbr = { 4884 .name = "caps", 4885 .attrs = lbr_attrs, 4886 .is_visible = lbr_is_visible, 4887 }; 4888 4889 static struct attribute_group group_format_extra = { 4890 .name = "format", 4891 .is_visible = exra_is_visible, 4892 }; 4893 4894 static struct attribute_group group_format_extra_skl = { 4895 .name = "format", 4896 .is_visible = exra_is_visible, 4897 }; 4898 4899 static struct attribute_group group_default = { 4900 .attrs = intel_pmu_attrs, 4901 .is_visible = default_is_visible, 4902 }; 4903 4904 static const struct attribute_group *attr_update[] = { 4905 &group_events_td, 4906 &group_events_mem, 4907 &group_events_tsx, 4908 &group_caps_gen, 4909 &group_caps_lbr, 4910 &group_format_extra, 4911 &group_format_extra_skl, 4912 &group_default, 4913 NULL, 4914 }; 4915 4916 static struct attribute *empty_attrs; 4917 4918 __init int intel_pmu_init(void) 4919 { 4920 struct attribute **extra_skl_attr = &empty_attrs; 4921 struct attribute **extra_attr = &empty_attrs; 4922 struct attribute **td_attr = &empty_attrs; 4923 struct attribute **mem_attr = &empty_attrs; 4924 struct attribute **tsx_attr = &empty_attrs; 4925 union cpuid10_edx edx; 4926 union cpuid10_eax eax; 4927 union cpuid10_ebx ebx; 4928 struct event_constraint *c; 4929 unsigned int unused; 4930 struct extra_reg *er; 4931 bool pmem = false; 4932 int version, i; 4933 char *name; 4934 4935 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 4936 switch (boot_cpu_data.x86) { 4937 case 0x6: 4938 return p6_pmu_init(); 4939 case 0xb: 4940 return knc_pmu_init(); 4941 case 0xf: 4942 return p4_pmu_init(); 4943 } 4944 return -ENODEV; 4945 } 4946 4947 /* 4948 * Check whether the Architectural PerfMon supports 4949 * Branch Misses Retired hw_event or not. 4950 */ 4951 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); 4952 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 4953 return -ENODEV; 4954 4955 version = eax.split.version_id; 4956 if (version < 2) 4957 x86_pmu = core_pmu; 4958 else 4959 x86_pmu = intel_pmu; 4960 4961 x86_pmu.version = version; 4962 x86_pmu.num_counters = eax.split.num_counters; 4963 x86_pmu.cntval_bits = eax.split.bit_width; 4964 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 4965 4966 x86_pmu.events_maskl = ebx.full; 4967 x86_pmu.events_mask_len = eax.split.mask_length; 4968 4969 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); 4970 4971 /* 4972 * Quirk: v2 perfmon does not report fixed-purpose events, so 4973 * assume at least 3 events, when not running in a hypervisor: 4974 */ 4975 if (version > 1) { 4976 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 4977 4978 x86_pmu.num_counters_fixed = 4979 max((int)edx.split.num_counters_fixed, assume); 4980 } 4981 4982 if (version >= 4) 4983 x86_pmu.counter_freezing = !disable_counter_freezing; 4984 4985 if (boot_cpu_has(X86_FEATURE_PDCM)) { 4986 u64 capabilities; 4987 4988 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 4989 x86_pmu.intel_cap.capabilities = capabilities; 4990 } 4991 4992 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 4993 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 4994 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 4995 } 4996 4997 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 4998 intel_pmu_arch_lbr_init(); 4999 5000 intel_ds_init(); 5001 5002 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 5003 5004 if (version >= 5) { 5005 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 5006 if (x86_pmu.intel_cap.anythread_deprecated) 5007 pr_cont(" AnyThread deprecated, "); 5008 } 5009 5010 /* 5011 * Install the hw-cache-events table: 5012 */ 5013 switch (boot_cpu_data.x86_model) { 5014 case INTEL_FAM6_CORE_YONAH: 5015 pr_cont("Core events, "); 5016 name = "core"; 5017 break; 5018 5019 case INTEL_FAM6_CORE2_MEROM: 5020 x86_add_quirk(intel_clovertown_quirk); 5021 fallthrough; 5022 5023 case INTEL_FAM6_CORE2_MEROM_L: 5024 case INTEL_FAM6_CORE2_PENRYN: 5025 case INTEL_FAM6_CORE2_DUNNINGTON: 5026 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 5027 sizeof(hw_cache_event_ids)); 5028 5029 intel_pmu_lbr_init_core(); 5030 5031 x86_pmu.event_constraints = intel_core2_event_constraints; 5032 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 5033 pr_cont("Core2 events, "); 5034 name = "core2"; 5035 break; 5036 5037 case INTEL_FAM6_NEHALEM: 5038 case INTEL_FAM6_NEHALEM_EP: 5039 case INTEL_FAM6_NEHALEM_EX: 5040 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 5041 sizeof(hw_cache_event_ids)); 5042 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5043 sizeof(hw_cache_extra_regs)); 5044 5045 intel_pmu_lbr_init_nhm(); 5046 5047 x86_pmu.event_constraints = intel_nehalem_event_constraints; 5048 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 5049 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5050 x86_pmu.extra_regs = intel_nehalem_extra_regs; 5051 x86_pmu.limit_period = nhm_limit_period; 5052 5053 mem_attr = nhm_mem_events_attrs; 5054 5055 /* UOPS_ISSUED.STALLED_CYCLES */ 5056 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5057 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5058 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5059 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5060 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5061 5062 intel_pmu_pebs_data_source_nhm(); 5063 x86_add_quirk(intel_nehalem_quirk); 5064 x86_pmu.pebs_no_tlb = 1; 5065 extra_attr = nhm_format_attr; 5066 5067 pr_cont("Nehalem events, "); 5068 name = "nehalem"; 5069 break; 5070 5071 case INTEL_FAM6_ATOM_BONNELL: 5072 case INTEL_FAM6_ATOM_BONNELL_MID: 5073 case INTEL_FAM6_ATOM_SALTWELL: 5074 case INTEL_FAM6_ATOM_SALTWELL_MID: 5075 case INTEL_FAM6_ATOM_SALTWELL_TABLET: 5076 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 5077 sizeof(hw_cache_event_ids)); 5078 5079 intel_pmu_lbr_init_atom(); 5080 5081 x86_pmu.event_constraints = intel_gen_event_constraints; 5082 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 5083 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 5084 pr_cont("Atom events, "); 5085 name = "bonnell"; 5086 break; 5087 5088 case INTEL_FAM6_ATOM_SILVERMONT: 5089 case INTEL_FAM6_ATOM_SILVERMONT_D: 5090 case INTEL_FAM6_ATOM_SILVERMONT_MID: 5091 case INTEL_FAM6_ATOM_AIRMONT: 5092 case INTEL_FAM6_ATOM_AIRMONT_MID: 5093 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 5094 sizeof(hw_cache_event_ids)); 5095 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 5096 sizeof(hw_cache_extra_regs)); 5097 5098 intel_pmu_lbr_init_slm(); 5099 5100 x86_pmu.event_constraints = intel_slm_event_constraints; 5101 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5102 x86_pmu.extra_regs = intel_slm_extra_regs; 5103 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5104 td_attr = slm_events_attrs; 5105 extra_attr = slm_format_attr; 5106 pr_cont("Silvermont events, "); 5107 name = "silvermont"; 5108 break; 5109 5110 case INTEL_FAM6_ATOM_GOLDMONT: 5111 case INTEL_FAM6_ATOM_GOLDMONT_D: 5112 x86_add_quirk(intel_counter_freezing_quirk); 5113 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 5114 sizeof(hw_cache_event_ids)); 5115 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 5116 sizeof(hw_cache_extra_regs)); 5117 5118 intel_pmu_lbr_init_skl(); 5119 5120 x86_pmu.event_constraints = intel_slm_event_constraints; 5121 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 5122 x86_pmu.extra_regs = intel_glm_extra_regs; 5123 /* 5124 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5125 * for precise cycles. 5126 * :pp is identical to :ppp 5127 */ 5128 x86_pmu.pebs_aliases = NULL; 5129 x86_pmu.pebs_prec_dist = true; 5130 x86_pmu.lbr_pt_coexist = true; 5131 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5132 td_attr = glm_events_attrs; 5133 extra_attr = slm_format_attr; 5134 pr_cont("Goldmont events, "); 5135 name = "goldmont"; 5136 break; 5137 5138 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5139 x86_add_quirk(intel_counter_freezing_quirk); 5140 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5141 sizeof(hw_cache_event_ids)); 5142 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 5143 sizeof(hw_cache_extra_regs)); 5144 5145 intel_pmu_lbr_init_skl(); 5146 5147 x86_pmu.event_constraints = intel_slm_event_constraints; 5148 x86_pmu.extra_regs = intel_glm_extra_regs; 5149 /* 5150 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5151 * for precise cycles. 5152 */ 5153 x86_pmu.pebs_aliases = NULL; 5154 x86_pmu.pebs_prec_dist = true; 5155 x86_pmu.lbr_pt_coexist = true; 5156 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5157 x86_pmu.flags |= PMU_FL_PEBS_ALL; 5158 x86_pmu.get_event_constraints = glp_get_event_constraints; 5159 td_attr = glm_events_attrs; 5160 /* Goldmont Plus has 4-wide pipeline */ 5161 event_attr_td_total_slots_scale_glm.event_str = "4"; 5162 extra_attr = slm_format_attr; 5163 pr_cont("Goldmont plus events, "); 5164 name = "goldmont_plus"; 5165 break; 5166 5167 case INTEL_FAM6_ATOM_TREMONT_D: 5168 case INTEL_FAM6_ATOM_TREMONT: 5169 case INTEL_FAM6_ATOM_TREMONT_L: 5170 x86_pmu.late_ack = true; 5171 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 5172 sizeof(hw_cache_event_ids)); 5173 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 5174 sizeof(hw_cache_extra_regs)); 5175 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5176 5177 intel_pmu_lbr_init_skl(); 5178 5179 x86_pmu.event_constraints = intel_slm_event_constraints; 5180 x86_pmu.extra_regs = intel_tnt_extra_regs; 5181 /* 5182 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 5183 * for precise cycles. 5184 */ 5185 x86_pmu.pebs_aliases = NULL; 5186 x86_pmu.pebs_prec_dist = true; 5187 x86_pmu.lbr_pt_coexist = true; 5188 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5189 x86_pmu.get_event_constraints = tnt_get_event_constraints; 5190 td_attr = tnt_events_attrs; 5191 extra_attr = slm_format_attr; 5192 pr_cont("Tremont events, "); 5193 name = "Tremont"; 5194 break; 5195 5196 case INTEL_FAM6_WESTMERE: 5197 case INTEL_FAM6_WESTMERE_EP: 5198 case INTEL_FAM6_WESTMERE_EX: 5199 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 5200 sizeof(hw_cache_event_ids)); 5201 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 5202 sizeof(hw_cache_extra_regs)); 5203 5204 intel_pmu_lbr_init_nhm(); 5205 5206 x86_pmu.event_constraints = intel_westmere_event_constraints; 5207 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 5208 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 5209 x86_pmu.extra_regs = intel_westmere_extra_regs; 5210 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5211 5212 mem_attr = nhm_mem_events_attrs; 5213 5214 /* UOPS_ISSUED.STALLED_CYCLES */ 5215 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5216 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5217 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 5218 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5219 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 5220 5221 intel_pmu_pebs_data_source_nhm(); 5222 extra_attr = nhm_format_attr; 5223 pr_cont("Westmere events, "); 5224 name = "westmere"; 5225 break; 5226 5227 case INTEL_FAM6_SANDYBRIDGE: 5228 case INTEL_FAM6_SANDYBRIDGE_X: 5229 x86_add_quirk(intel_sandybridge_quirk); 5230 x86_add_quirk(intel_ht_bug); 5231 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5232 sizeof(hw_cache_event_ids)); 5233 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5234 sizeof(hw_cache_extra_regs)); 5235 5236 intel_pmu_lbr_init_snb(); 5237 5238 x86_pmu.event_constraints = intel_snb_event_constraints; 5239 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 5240 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 5241 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X) 5242 x86_pmu.extra_regs = intel_snbep_extra_regs; 5243 else 5244 x86_pmu.extra_regs = intel_snb_extra_regs; 5245 5246 5247 /* all extra regs are per-cpu when HT is on */ 5248 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5249 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5250 5251 td_attr = snb_events_attrs; 5252 mem_attr = snb_mem_events_attrs; 5253 5254 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5255 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5256 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5257 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 5258 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 5259 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 5260 5261 extra_attr = nhm_format_attr; 5262 5263 pr_cont("SandyBridge events, "); 5264 name = "sandybridge"; 5265 break; 5266 5267 case INTEL_FAM6_IVYBRIDGE: 5268 case INTEL_FAM6_IVYBRIDGE_X: 5269 x86_add_quirk(intel_ht_bug); 5270 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 5271 sizeof(hw_cache_event_ids)); 5272 /* dTLB-load-misses on IVB is different than SNB */ 5273 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 5274 5275 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 5276 sizeof(hw_cache_extra_regs)); 5277 5278 intel_pmu_lbr_init_snb(); 5279 5280 x86_pmu.event_constraints = intel_ivb_event_constraints; 5281 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 5282 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5283 x86_pmu.pebs_prec_dist = true; 5284 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X) 5285 x86_pmu.extra_regs = intel_snbep_extra_regs; 5286 else 5287 x86_pmu.extra_regs = intel_snb_extra_regs; 5288 /* all extra regs are per-cpu when HT is on */ 5289 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5290 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5291 5292 td_attr = snb_events_attrs; 5293 mem_attr = snb_mem_events_attrs; 5294 5295 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 5296 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 5297 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 5298 5299 extra_attr = nhm_format_attr; 5300 5301 pr_cont("IvyBridge events, "); 5302 name = "ivybridge"; 5303 break; 5304 5305 5306 case INTEL_FAM6_HASWELL: 5307 case INTEL_FAM6_HASWELL_X: 5308 case INTEL_FAM6_HASWELL_L: 5309 case INTEL_FAM6_HASWELL_G: 5310 x86_add_quirk(intel_ht_bug); 5311 x86_add_quirk(intel_pebs_isolation_quirk); 5312 x86_pmu.late_ack = true; 5313 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5314 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5315 5316 intel_pmu_lbr_init_hsw(); 5317 5318 x86_pmu.event_constraints = intel_hsw_event_constraints; 5319 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 5320 x86_pmu.extra_regs = intel_snbep_extra_regs; 5321 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5322 x86_pmu.pebs_prec_dist = true; 5323 /* all extra regs are per-cpu when HT is on */ 5324 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5325 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5326 5327 x86_pmu.hw_config = hsw_hw_config; 5328 x86_pmu.get_event_constraints = hsw_get_event_constraints; 5329 x86_pmu.lbr_double_abort = true; 5330 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5331 hsw_format_attr : nhm_format_attr; 5332 td_attr = hsw_events_attrs; 5333 mem_attr = hsw_mem_events_attrs; 5334 tsx_attr = hsw_tsx_events_attrs; 5335 pr_cont("Haswell events, "); 5336 name = "haswell"; 5337 break; 5338 5339 case INTEL_FAM6_BROADWELL: 5340 case INTEL_FAM6_BROADWELL_D: 5341 case INTEL_FAM6_BROADWELL_G: 5342 case INTEL_FAM6_BROADWELL_X: 5343 x86_add_quirk(intel_pebs_isolation_quirk); 5344 x86_pmu.late_ack = true; 5345 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5346 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5347 5348 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 5349 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 5350 BDW_L3_MISS|HSW_SNOOP_DRAM; 5351 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 5352 HSW_SNOOP_DRAM; 5353 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 5354 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5355 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 5356 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 5357 5358 intel_pmu_lbr_init_hsw(); 5359 5360 x86_pmu.event_constraints = intel_bdw_event_constraints; 5361 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 5362 x86_pmu.extra_regs = intel_snbep_extra_regs; 5363 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 5364 x86_pmu.pebs_prec_dist = true; 5365 /* all extra regs are per-cpu when HT is on */ 5366 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5367 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5368 5369 x86_pmu.hw_config = hsw_hw_config; 5370 x86_pmu.get_event_constraints = hsw_get_event_constraints; 5371 x86_pmu.limit_period = bdw_limit_period; 5372 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5373 hsw_format_attr : nhm_format_attr; 5374 td_attr = hsw_events_attrs; 5375 mem_attr = hsw_mem_events_attrs; 5376 tsx_attr = hsw_tsx_events_attrs; 5377 pr_cont("Broadwell events, "); 5378 name = "broadwell"; 5379 break; 5380 5381 case INTEL_FAM6_XEON_PHI_KNL: 5382 case INTEL_FAM6_XEON_PHI_KNM: 5383 memcpy(hw_cache_event_ids, 5384 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5385 memcpy(hw_cache_extra_regs, 5386 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5387 intel_pmu_lbr_init_knl(); 5388 5389 x86_pmu.event_constraints = intel_slm_event_constraints; 5390 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 5391 x86_pmu.extra_regs = intel_knl_extra_regs; 5392 5393 /* all extra regs are per-cpu when HT is on */ 5394 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5395 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5396 extra_attr = slm_format_attr; 5397 pr_cont("Knights Landing/Mill events, "); 5398 name = "knights-landing"; 5399 break; 5400 5401 case INTEL_FAM6_SKYLAKE_X: 5402 pmem = true; 5403 fallthrough; 5404 case INTEL_FAM6_SKYLAKE_L: 5405 case INTEL_FAM6_SKYLAKE: 5406 case INTEL_FAM6_KABYLAKE_L: 5407 case INTEL_FAM6_KABYLAKE: 5408 case INTEL_FAM6_COMETLAKE_L: 5409 case INTEL_FAM6_COMETLAKE: 5410 x86_add_quirk(intel_pebs_isolation_quirk); 5411 x86_pmu.late_ack = true; 5412 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5413 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5414 intel_pmu_lbr_init_skl(); 5415 5416 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 5417 event_attr_td_recovery_bubbles.event_str_noht = 5418 "event=0xd,umask=0x1,cmask=1"; 5419 event_attr_td_recovery_bubbles.event_str_ht = 5420 "event=0xd,umask=0x1,cmask=1,any=1"; 5421 5422 x86_pmu.event_constraints = intel_skl_event_constraints; 5423 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 5424 x86_pmu.extra_regs = intel_skl_extra_regs; 5425 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 5426 x86_pmu.pebs_prec_dist = true; 5427 /* all extra regs are per-cpu when HT is on */ 5428 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5429 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5430 5431 x86_pmu.hw_config = hsw_hw_config; 5432 x86_pmu.get_event_constraints = hsw_get_event_constraints; 5433 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5434 hsw_format_attr : nhm_format_attr; 5435 extra_skl_attr = skl_format_attr; 5436 td_attr = hsw_events_attrs; 5437 mem_attr = hsw_mem_events_attrs; 5438 tsx_attr = hsw_tsx_events_attrs; 5439 intel_pmu_pebs_data_source_skl(pmem); 5440 5441 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) { 5442 x86_pmu.flags |= PMU_FL_TFA; 5443 x86_pmu.get_event_constraints = tfa_get_event_constraints; 5444 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 5445 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 5446 } 5447 5448 pr_cont("Skylake events, "); 5449 name = "skylake"; 5450 break; 5451 5452 case INTEL_FAM6_ICELAKE_X: 5453 case INTEL_FAM6_ICELAKE_D: 5454 pmem = true; 5455 fallthrough; 5456 case INTEL_FAM6_ICELAKE_L: 5457 case INTEL_FAM6_ICELAKE: 5458 case INTEL_FAM6_TIGERLAKE_L: 5459 case INTEL_FAM6_TIGERLAKE: 5460 case INTEL_FAM6_ROCKETLAKE: 5461 x86_pmu.late_ack = true; 5462 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 5463 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 5464 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 5465 intel_pmu_lbr_init_skl(); 5466 5467 x86_pmu.event_constraints = intel_icl_event_constraints; 5468 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 5469 x86_pmu.extra_regs = intel_icl_extra_regs; 5470 x86_pmu.pebs_aliases = NULL; 5471 x86_pmu.pebs_prec_dist = true; 5472 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 5473 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 5474 5475 x86_pmu.hw_config = hsw_hw_config; 5476 x86_pmu.get_event_constraints = icl_get_event_constraints; 5477 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 5478 hsw_format_attr : nhm_format_attr; 5479 extra_skl_attr = skl_format_attr; 5480 mem_attr = icl_events_attrs; 5481 td_attr = icl_td_events_attrs; 5482 tsx_attr = icl_tsx_events_attrs; 5483 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 5484 x86_pmu.lbr_pt_coexist = true; 5485 intel_pmu_pebs_data_source_skl(pmem); 5486 x86_pmu.update_topdown_event = icl_update_topdown_event; 5487 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period; 5488 pr_cont("Icelake events, "); 5489 name = "icelake"; 5490 break; 5491 5492 default: 5493 switch (x86_pmu.version) { 5494 case 1: 5495 x86_pmu.event_constraints = intel_v1_event_constraints; 5496 pr_cont("generic architected perfmon v1, "); 5497 name = "generic_arch_v1"; 5498 break; 5499 default: 5500 /* 5501 * default constraints for v2 and up 5502 */ 5503 x86_pmu.event_constraints = intel_gen_event_constraints; 5504 pr_cont("generic architected perfmon, "); 5505 name = "generic_arch_v2+"; 5506 break; 5507 } 5508 } 5509 5510 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 5511 5512 5513 group_events_td.attrs = td_attr; 5514 group_events_mem.attrs = mem_attr; 5515 group_events_tsx.attrs = tsx_attr; 5516 group_format_extra.attrs = extra_attr; 5517 group_format_extra_skl.attrs = extra_skl_attr; 5518 5519 x86_pmu.attr_update = attr_update; 5520 5521 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { 5522 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5523 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); 5524 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; 5525 } 5526 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1; 5527 5528 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { 5529 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5530 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); 5531 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; 5532 } 5533 5534 x86_pmu.intel_ctrl |= 5535 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; 5536 5537 /* AnyThread may be deprecated on arch perfmon v5 or later */ 5538 if (x86_pmu.intel_cap.anythread_deprecated) 5539 x86_pmu.format_attrs = intel_arch_formats_attr; 5540 5541 if (x86_pmu.event_constraints) { 5542 /* 5543 * event on fixed counter2 (REF_CYCLES) only works on this 5544 * counter, so do not extend mask to generic counters 5545 */ 5546 for_each_event_constraint(c, x86_pmu.event_constraints) { 5547 /* 5548 * Don't extend the topdown slots and metrics 5549 * events to the generic counters. 5550 */ 5551 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 5552 c->weight = hweight64(c->idxmsk64); 5553 continue; 5554 } 5555 5556 if (c->cmask == FIXED_EVENT_FLAGS 5557 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { 5558 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; 5559 } 5560 c->idxmsk64 &= 5561 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); 5562 c->weight = hweight64(c->idxmsk64); 5563 } 5564 } 5565 5566 /* 5567 * Access LBR MSR may cause #GP under certain circumstances. 5568 * E.g. KVM doesn't support LBR MSR 5569 * Check all LBT MSR here. 5570 * Disable LBR access if any LBR MSRs can not be accessed. 5571 */ 5572 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 5573 x86_pmu.lbr_nr = 0; 5574 for (i = 0; i < x86_pmu.lbr_nr; i++) { 5575 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 5576 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 5577 x86_pmu.lbr_nr = 0; 5578 } 5579 5580 if (x86_pmu.lbr_nr) 5581 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 5582 5583 /* 5584 * Access extra MSR may cause #GP under certain circumstances. 5585 * E.g. KVM doesn't support offcore event 5586 * Check all extra_regs here. 5587 */ 5588 if (x86_pmu.extra_regs) { 5589 for (er = x86_pmu.extra_regs; er->msr; er++) { 5590 er->extra_msr_access = check_msr(er->msr, 0x11UL); 5591 /* Disable LBR select mapping */ 5592 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 5593 x86_pmu.lbr_sel_map = NULL; 5594 } 5595 } 5596 5597 /* Support full width counters using alternative MSR range */ 5598 if (x86_pmu.intel_cap.full_width_write) { 5599 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 5600 x86_pmu.perfctr = MSR_IA32_PMC0; 5601 pr_cont("full-width counters, "); 5602 } 5603 5604 /* 5605 * For arch perfmon 4 use counter freezing to avoid 5606 * several MSR accesses in the PMI. 5607 */ 5608 if (x86_pmu.counter_freezing) 5609 x86_pmu.handle_irq = intel_pmu_handle_irq_v4; 5610 5611 if (x86_pmu.intel_cap.perf_metrics) 5612 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5613 5614 return 0; 5615 } 5616 5617 /* 5618 * HT bug: phase 2 init 5619 * Called once we have valid topology information to check 5620 * whether or not HT is enabled 5621 * If HT is off, then we disable the workaround 5622 */ 5623 static __init int fixup_ht_bug(void) 5624 { 5625 int c; 5626 /* 5627 * problem not present on this CPU model, nothing to do 5628 */ 5629 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 5630 return 0; 5631 5632 if (topology_max_smt_threads() > 1) { 5633 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 5634 return 0; 5635 } 5636 5637 cpus_read_lock(); 5638 5639 hardlockup_detector_perf_stop(); 5640 5641 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 5642 5643 x86_pmu.start_scheduling = NULL; 5644 x86_pmu.commit_scheduling = NULL; 5645 x86_pmu.stop_scheduling = NULL; 5646 5647 hardlockup_detector_perf_restart(); 5648 5649 for_each_online_cpu(c) 5650 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 5651 5652 cpus_read_unlock(); 5653 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 5654 return 0; 5655 } 5656 subsys_initcall(fixup_ht_bug) 5657