1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 static const struct flash_info spansion_parts[] = { 12 /* Spansion/Cypress -- single (large) sector size only, at least 13 * for the chips listed here (without boot sectors). 14 */ 15 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 16 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 17 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 18 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 19 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, 20 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 21 USE_CLSR) }, 22 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, 23 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 24 USE_CLSR) }, 25 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, 26 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 27 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 28 USE_CLSR) }, 29 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256, 30 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 31 SPI_NOR_HAS_LOCK | USE_CLSR) }, 32 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, 33 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 34 USE_CLSR) }, 35 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, 36 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 37 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 38 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 39 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 40 USE_CLSR) }, 41 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 42 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 43 USE_CLSR) }, 44 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, 45 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, 46 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, 47 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 48 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 49 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, 50 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 51 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, 52 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 53 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, 54 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 55 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 56 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, 57 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 58 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, 59 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, 60 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, 61 SECT_4K | SPI_NOR_DUAL_READ) }, 62 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, 63 SECT_4K | SPI_NOR_DUAL_READ) }, 64 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, 65 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 66 SPI_NOR_4B_OPCODES) }, 67 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, 68 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 69 SPI_NOR_4B_OPCODES) }, 70 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, 71 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 72 SPI_NOR_4B_OPCODES) }, 73 }; 74 75 static void spansion_post_sfdp_fixups(struct spi_nor *nor) 76 { 77 if (nor->params->size <= SZ_16M) 78 return; 79 80 nor->flags |= SNOR_F_4B_OPCODES; 81 /* No small sector erase for 4-byte command set */ 82 nor->erase_opcode = SPINOR_OP_SE; 83 nor->mtd.erasesize = nor->info->sector_size; 84 } 85 86 static const struct spi_nor_fixups spansion_fixups = { 87 .post_sfdp = spansion_post_sfdp_fixups, 88 }; 89 90 const struct spi_nor_manufacturer spi_nor_spansion = { 91 .name = "spansion", 92 .parts = spansion_parts, 93 .nparts = ARRAY_SIZE(spansion_parts), 94 .fixups = &spansion_fixups, 95 }; 96