1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_CPU_PORT 6 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 #define MTK_HDR_LEN 4 15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17 enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 }; 22 23 #define NUM_TRGMII_CTRL 5 24 25 #define TRGMII_BASE(x) (0x10000 + (x)) 26 27 /* Registers to ethsys access */ 28 #define ETHSYS_CLKCFG0 0x2c 29 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 30 31 #define SYSC_REG_RSTCTRL 0x34 32 #define RESET_MCM BIT(2) 33 34 /* Registers to mac forward control for unknown frames */ 35 #define MT7530_MFC 0x10 36 #define BC_FFP(x) (((x) & 0xff) << 24) 37 #define UNM_FFP(x) (((x) & 0xff) << 16) 38 #define UNM_FFP_MASK UNM_FFP(~0) 39 #define UNU_FFP(x) (((x) & 0xff) << 8) 40 #define UNU_FFP_MASK UNU_FFP(~0) 41 #define CPU_EN BIT(7) 42 #define CPU_PORT(x) ((x) << 4) 43 #define CPU_MASK (0xf << 4) 44 #define MIRROR_EN BIT(3) 45 #define MIRROR_PORT(x) ((x) & 0x7) 46 #define MIRROR_MASK 0x7 47 48 /* Registers for CPU forward control */ 49 #define MT7531_CFC 0x4 50 #define MT7531_MIRROR_EN BIT(19) 51 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16) 52 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) 53 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) 54 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 55 56 #define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \ 57 MT7531_CFC : MT7530_MFC) 58 #define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \ 59 MT7531_MIRROR_EN : MIRROR_EN) 60 #define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \ 61 MT7531_MIRROR_MASK : MIRROR_MASK) 62 63 /* Registers for BPDU and PAE frame control*/ 64 #define MT753X_BPC 0x24 65 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) 66 67 enum mt753x_bpdu_port_fw { 68 MT753X_BPDU_FOLLOW_MFC, 69 MT753X_BPDU_CPU_EXCLUDE = 4, 70 MT753X_BPDU_CPU_INCLUDE = 5, 71 MT753X_BPDU_CPU_ONLY = 6, 72 MT753X_BPDU_DROP = 7, 73 }; 74 75 /* Registers for address table access */ 76 #define MT7530_ATA1 0x74 77 #define STATIC_EMP 0 78 #define STATIC_ENT 3 79 #define MT7530_ATA2 0x78 80 81 /* Register for address table write data */ 82 #define MT7530_ATWD 0x7c 83 84 /* Register for address table control */ 85 #define MT7530_ATC 0x80 86 #define ATC_HASH (((x) & 0xfff) << 16) 87 #define ATC_BUSY BIT(15) 88 #define ATC_SRCH_END BIT(14) 89 #define ATC_SRCH_HIT BIT(13) 90 #define ATC_INVALID BIT(12) 91 #define ATC_MAT(x) (((x) & 0xf) << 8) 92 #define ATC_MAT_MACTAB ATC_MAT(0) 93 94 enum mt7530_fdb_cmd { 95 MT7530_FDB_READ = 0, 96 MT7530_FDB_WRITE = 1, 97 MT7530_FDB_FLUSH = 2, 98 MT7530_FDB_START = 4, 99 MT7530_FDB_NEXT = 5, 100 }; 101 102 /* Registers for table search read address */ 103 #define MT7530_TSRA1 0x84 104 #define MAC_BYTE_0 24 105 #define MAC_BYTE_1 16 106 #define MAC_BYTE_2 8 107 #define MAC_BYTE_3 0 108 #define MAC_BYTE_MASK 0xff 109 110 #define MT7530_TSRA2 0x88 111 #define MAC_BYTE_4 24 112 #define MAC_BYTE_5 16 113 #define CVID 0 114 #define CVID_MASK 0xfff 115 116 #define MT7530_ATRD 0x8C 117 #define AGE_TIMER 24 118 #define AGE_TIMER_MASK 0xff 119 #define PORT_MAP 4 120 #define PORT_MAP_MASK 0xff 121 #define ENT_STATUS 2 122 #define ENT_STATUS_MASK 0x3 123 124 /* Register for vlan table control */ 125 #define MT7530_VTCR 0x90 126 #define VTCR_BUSY BIT(31) 127 #define VTCR_INVALID BIT(16) 128 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 129 #define VTCR_VID ((x) & 0xfff) 130 131 enum mt7530_vlan_cmd { 132 /* Read/Write the specified VID entry from VAWD register based 133 * on VID. 134 */ 135 MT7530_VTCR_RD_VID = 0, 136 MT7530_VTCR_WR_VID = 1, 137 }; 138 139 /* Register for setup vlan and acl write data */ 140 #define MT7530_VAWD1 0x94 141 #define PORT_STAG BIT(31) 142 /* Independent VLAN Learning */ 143 #define IVL_MAC BIT(30) 144 /* Per VLAN Egress Tag Control */ 145 #define VTAG_EN BIT(28) 146 /* VLAN Member Control */ 147 #define PORT_MEM(x) (((x) & 0xff) << 16) 148 /* VLAN Entry Valid */ 149 #define VLAN_VALID BIT(0) 150 #define PORT_MEM_SHFT 16 151 #define PORT_MEM_MASK 0xff 152 153 #define MT7530_VAWD2 0x98 154 /* Egress Tag Control */ 155 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 156 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 157 158 enum mt7530_vlan_egress_attr { 159 MT7530_VLAN_EGRESS_UNTAG = 0, 160 MT7530_VLAN_EGRESS_TAG = 2, 161 MT7530_VLAN_EGRESS_STACK = 3, 162 }; 163 164 /* Register for address age control */ 165 #define MT7530_AAC 0xa0 166 /* Disable ageing */ 167 #define AGE_DIS BIT(20) 168 /* Age count */ 169 #define AGE_CNT_MASK GENMASK(19, 12) 170 #define AGE_CNT_MAX 0xff 171 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 172 /* Age unit */ 173 #define AGE_UNIT_MASK GENMASK(11, 0) 174 #define AGE_UNIT_MAX 0xfff 175 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 176 177 /* Register for port STP state control */ 178 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 179 #define FID_PST(x) ((x) & 0x3) 180 #define FID_PST_MASK FID_PST(0x3) 181 182 enum mt7530_stp_state { 183 MT7530_STP_DISABLED = 0, 184 MT7530_STP_BLOCKING = 1, 185 MT7530_STP_LISTENING = 1, 186 MT7530_STP_LEARNING = 2, 187 MT7530_STP_FORWARDING = 3 188 }; 189 190 /* Register for port control */ 191 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 192 #define PORT_TX_MIR BIT(9) 193 #define PORT_RX_MIR BIT(8) 194 #define PORT_VLAN(x) ((x) & 0x3) 195 196 enum mt7530_port_mode { 197 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 198 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 199 200 /* Fallback Mode: Forward received frames with ingress ports that do 201 * not belong to the VLAN member. Frames whose VID is not listed on 202 * the VLAN table are forwarded by the PCR_MATRIX members. 203 */ 204 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 205 206 /* Security Mode: Discard any frame due to ingress membership 207 * violation or VID missed on the VLAN table. 208 */ 209 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 210 }; 211 212 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 213 #define PORT_PRI(x) (((x) & 0x7) << 24) 214 #define EG_TAG(x) (((x) & 0x3) << 28) 215 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 216 #define PCR_MATRIX_CLR PCR_MATRIX(0) 217 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 218 219 /* Register for port security control */ 220 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 221 #define SA_DIS BIT(4) 222 223 /* Register for port vlan control */ 224 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 225 #define PORT_SPEC_TAG BIT(5) 226 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 227 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 228 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 229 #define VLAN_ATTR_MASK VLAN_ATTR(3) 230 231 enum mt7530_vlan_port_eg_tag { 232 MT7530_VLAN_EG_DISABLED = 0, 233 MT7530_VLAN_EG_CONSISTENT = 1, 234 }; 235 236 enum mt7530_vlan_port_attr { 237 MT7530_VLAN_USER = 0, 238 MT7530_VLAN_TRANSPARENT = 3, 239 }; 240 241 #define STAG_VPID (((x) & 0xffff) << 16) 242 243 /* Register for port port-and-protocol based vlan 1 control */ 244 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 245 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 246 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 247 #define G0_PORT_VID_DEF G0_PORT_VID(1) 248 249 /* Register for port MAC control register */ 250 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 251 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 252 #define PMCR_EXT_PHY BIT(17) 253 #define PMCR_MAC_MODE BIT(16) 254 #define PMCR_FORCE_MODE BIT(15) 255 #define PMCR_TX_EN BIT(14) 256 #define PMCR_RX_EN BIT(13) 257 #define PMCR_BACKOFF_EN BIT(9) 258 #define PMCR_BACKPR_EN BIT(8) 259 #define PMCR_TX_FC_EN BIT(5) 260 #define PMCR_RX_FC_EN BIT(4) 261 #define PMCR_FORCE_SPEED_1000 BIT(3) 262 #define PMCR_FORCE_SPEED_100 BIT(2) 263 #define PMCR_FORCE_FDX BIT(1) 264 #define PMCR_FORCE_LNK BIT(0) 265 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 266 PMCR_FORCE_SPEED_1000) 267 #define MT7531_FORCE_LNK BIT(31) 268 #define MT7531_FORCE_SPD BIT(30) 269 #define MT7531_FORCE_DPX BIT(29) 270 #define MT7531_FORCE_RX_FC BIT(28) 271 #define MT7531_FORCE_TX_FC BIT(27) 272 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ 273 MT7531_FORCE_SPD | \ 274 MT7531_FORCE_DPX | \ 275 MT7531_FORCE_RX_FC | \ 276 MT7531_FORCE_TX_FC) 277 #define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \ 278 MT7531_FORCE_MODE : \ 279 PMCR_FORCE_MODE) 280 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ 281 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ 282 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 283 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 284 #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \ 285 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ 286 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ 287 PMCR_TX_EN | PMCR_RX_EN | \ 288 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 289 PMCR_FORCE_SPEED_1000 | \ 290 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 291 292 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 293 #define PMSR_EEE1G BIT(7) 294 #define PMSR_EEE100M BIT(6) 295 #define PMSR_RX_FC BIT(5) 296 #define PMSR_TX_FC BIT(4) 297 #define PMSR_SPEED_1000 BIT(3) 298 #define PMSR_SPEED_100 BIT(2) 299 #define PMSR_SPEED_10 0x00 300 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 301 #define PMSR_DPX BIT(1) 302 #define PMSR_LINK BIT(0) 303 304 /* Register for port debug count */ 305 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 306 #define MT7531_DIS_CLR BIT(31) 307 308 #define MT7530_GMACCR 0x30e0 309 #define MAX_RX_JUMBO(x) ((x) << 2) 310 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 311 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 312 #define MAX_RX_PKT_LEN_1522 0x0 313 #define MAX_RX_PKT_LEN_1536 0x1 314 #define MAX_RX_PKT_LEN_1552 0x2 315 #define MAX_RX_PKT_LEN_JUMBO 0x3 316 317 /* Register for MIB */ 318 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 319 #define MT7530_MIB_CCR 0x4fe0 320 #define CCR_MIB_ENABLE BIT(31) 321 #define CCR_RX_OCT_CNT_GOOD BIT(7) 322 #define CCR_RX_OCT_CNT_BAD BIT(6) 323 #define CCR_TX_OCT_CNT_GOOD BIT(5) 324 #define CCR_TX_OCT_CNT_BAD BIT(4) 325 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 326 CCR_RX_OCT_CNT_BAD | \ 327 CCR_TX_OCT_CNT_GOOD | \ 328 CCR_TX_OCT_CNT_BAD) 329 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 330 CCR_RX_OCT_CNT_GOOD | \ 331 CCR_RX_OCT_CNT_BAD | \ 332 CCR_TX_OCT_CNT_GOOD | \ 333 CCR_TX_OCT_CNT_BAD) 334 335 /* MT7531 SGMII register group */ 336 #define MT7531_SGMII_REG_BASE 0x5000 337 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ 338 ((p) - 5) * 0x1000 + (r)) 339 340 /* Register forSGMII PCS_CONTROL_1 */ 341 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00) 342 #define MT7531_SGMII_LINK_STATUS BIT(18) 343 #define MT7531_SGMII_AN_ENABLE BIT(12) 344 #define MT7531_SGMII_AN_RESTART BIT(9) 345 346 /* Register for SGMII PCS_SPPED_ABILITY */ 347 #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08) 348 #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0) 349 #define MT7531_SGMII_TX_CONFIG BIT(0) 350 351 /* Register for SGMII_MODE */ 352 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20) 353 #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8) 354 #define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1) 355 #define MT7531_SGMII_FORCE_DUPLEX BIT(4) 356 #define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2) 357 #define MT7531_SGMII_FORCE_SPEED_1000 BIT(3) 358 #define MT7531_SGMII_FORCE_SPEED_100 BIT(2) 359 #define MT7531_SGMII_FORCE_SPEED_10 0 360 #define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1) 361 362 enum mt7531_sgmii_force_duplex { 363 MT7531_SGMII_FORCE_FULL_DUPLEX = 0, 364 MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10, 365 }; 366 367 /* Fields of QPHY_PWR_STATE_CTRL */ 368 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8) 369 #define MT7531_SGMII_PHYA_PWD BIT(4) 370 371 /* Values of SGMII SPEED */ 372 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128) 373 #define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3)) 374 #define MT7531_RG_TPHY_SPEED_1_25G 0x0 375 #define MT7531_RG_TPHY_SPEED_3_125G BIT(2) 376 377 /* Register for system reset */ 378 #define MT7530_SYS_CTRL 0x7000 379 #define SYS_CTRL_PHY_RST BIT(2) 380 #define SYS_CTRL_SW_RST BIT(1) 381 #define SYS_CTRL_REG_RST BIT(0) 382 383 /* Register for PHY Indirect Access Control */ 384 #define MT7531_PHY_IAC 0x701C 385 #define MT7531_PHY_ACS_ST BIT(31) 386 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 387 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 388 #define MT7531_MDIO_CMD_MASK (0x3 << 18) 389 #define MT7531_MDIO_ST_MASK (0x3 << 16) 390 #define MT7531_MDIO_RW_DATA_MASK (0xffff) 391 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 392 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 393 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 394 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 395 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 396 397 enum mt7531_phy_iac_cmd { 398 MT7531_MDIO_ADDR = 0, 399 MT7531_MDIO_WRITE = 1, 400 MT7531_MDIO_READ = 2, 401 MT7531_MDIO_READ_CL45 = 3, 402 }; 403 404 /* MDIO_ST: MDIO start field */ 405 enum mt7531_mdio_st { 406 MT7531_MDIO_ST_CL45 = 0, 407 MT7531_MDIO_ST_CL22 = 1, 408 }; 409 410 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 411 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 412 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 413 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 414 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 415 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 416 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 417 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 418 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 419 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 420 421 /* Register for RGMII clock phase */ 422 #define MT7531_CLKGEN_CTRL 0x7500 423 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 424 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 425 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 426 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 427 #define RXCLK_NO_DELAY BIT(5) 428 #define TXCLK_NO_REVERSE BIT(4) 429 #define GP_MODE(x) (((x) & 0x3) << 1) 430 #define GP_MODE_MASK GENMASK(2, 1) 431 #define GP_CLK_EN BIT(0) 432 433 enum mt7531_gp_mode { 434 MT7531_GP_MODE_RGMII = 0, 435 MT7531_GP_MODE_MII = 1, 436 MT7531_GP_MODE_REV_MII = 2 437 }; 438 439 enum mt7531_clk_skew { 440 MT7531_CLK_SKEW_NO_CHG = 0, 441 MT7531_CLK_SKEW_DLY_100PPS = 1, 442 MT7531_CLK_SKEW_DLY_200PPS = 2, 443 MT7531_CLK_SKEW_REVERSE = 3, 444 }; 445 446 /* Register for hw trap status */ 447 #define MT7530_HWTRAP 0x7800 448 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 449 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 450 #define HWTRAP_XTAL_40MHZ (BIT(10)) 451 #define HWTRAP_XTAL_20MHZ (BIT(9)) 452 453 #define MT7531_HWTRAP 0x7800 454 #define HWTRAP_XTAL_FSEL_MASK BIT(7) 455 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7) 456 #define HWTRAP_XTAL_FSEL_40MHZ 0 457 /* Unique fields of (M)HWSTRAP for MT7531 */ 458 #define XTAL_FSEL_S 7 459 #define XTAL_FSEL_M BIT(7) 460 #define PHY_EN BIT(6) 461 #define CHG_STRAP BIT(8) 462 463 /* Register for hw trap modification */ 464 #define MT7530_MHWTRAP 0x7804 465 #define MHWTRAP_PHY0_SEL BIT(20) 466 #define MHWTRAP_MANUAL BIT(16) 467 #define MHWTRAP_P5_MAC_SEL BIT(13) 468 #define MHWTRAP_P6_DIS BIT(8) 469 #define MHWTRAP_P5_RGMII_MODE BIT(7) 470 #define MHWTRAP_P5_DIS BIT(6) 471 #define MHWTRAP_PHY_ACCESS BIT(5) 472 473 /* Register for TOP signal control */ 474 #define MT7530_TOP_SIG_CTRL 0x7808 475 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 476 477 #define MT7531_TOP_SIG_SR 0x780c 478 #define PAD_DUAL_SGMII_EN BIT(1) 479 #define PAD_MCM_SMI_EN BIT(0) 480 481 #define MT7530_IO_DRV_CR 0x7810 482 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 483 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 484 485 #define MT7531_CHIP_REV 0x781C 486 487 #define MT7531_PLLGP_EN 0x7820 488 #define EN_COREPLL BIT(2) 489 #define SW_CLKSW BIT(1) 490 #define SW_PLLGP BIT(0) 491 492 #define MT7530_P6ECR 0x7830 493 #define P6_INTF_MODE_MASK 0x3 494 #define P6_INTF_MODE(x) ((x) & 0x3) 495 496 #define MT7531_PLLGP_CR0 0x78a8 497 #define RG_COREPLL_EN BIT(22) 498 #define RG_COREPLL_POSDIV_S 23 499 #define RG_COREPLL_POSDIV_M 0x3800000 500 #define RG_COREPLL_SDM_PCW_S 1 501 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 502 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 503 504 /* Registers for RGMII and SGMII PLL clock */ 505 #define MT7531_ANA_PLLGP_CR2 0x78b0 506 #define MT7531_ANA_PLLGP_CR5 0x78bc 507 508 /* Registers for TRGMII on the both side */ 509 #define MT7530_TRGMII_RCK_CTRL 0x7a00 510 #define RX_RST BIT(31) 511 #define RXC_DQSISEL BIT(30) 512 #define DQSI1_TAP_MASK (0x7f << 8) 513 #define DQSI0_TAP_MASK 0x7f 514 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 515 #define DQSI0_TAP(x) ((x) & 0x7f) 516 517 #define MT7530_TRGMII_RCK_RTT 0x7a04 518 #define DQS1_GATE BIT(31) 519 #define DQS0_GATE BIT(30) 520 521 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 522 #define BSLIP_EN BIT(31) 523 #define EDGE_CHK BIT(30) 524 #define RD_TAP_MASK 0x7f 525 #define RD_TAP(x) ((x) & 0x7f) 526 527 #define MT7530_TRGMII_TXCTRL 0x7a40 528 #define TRAIN_TXEN BIT(31) 529 #define TXC_INV BIT(30) 530 #define TX_RST BIT(28) 531 532 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 533 #define TD_DM_DRVP(x) ((x) & 0xf) 534 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 535 536 #define MT7530_TRGMII_TCK_CTRL 0x7a78 537 #define TCK_TAP(x) (((x) & 0xf) << 8) 538 539 #define MT7530_P5RGMIIRXCR 0x7b00 540 #define CSR_RGMII_EDGE_ALIGN BIT(8) 541 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 542 543 #define MT7530_P5RGMIITXCR 0x7b04 544 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 545 546 /* Registers for GPIO mode */ 547 #define MT7531_GPIO_MODE0 0x7c0c 548 #define MT7531_GPIO0_MASK GENMASK(3, 0) 549 #define MT7531_GPIO0_INTERRUPT 1 550 551 #define MT7531_GPIO_MODE1 0x7c10 552 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 553 #define MT7531_EXT_P_MDC_11 (2 << 12) 554 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 555 #define MT7531_EXT_P_MDIO_12 (2 << 16) 556 557 #define MT7530_CREV 0x7ffc 558 #define CHIP_NAME_SHIFT 16 559 #define MT7530_ID 0x7530 560 561 #define MT7531_CREV 0x781C 562 #define CHIP_REV_M 0x0f 563 #define MT7531_ID 0x7531 564 565 /* Registers for core PLL access through mmd indirect */ 566 #define CORE_PLL_GROUP2 0x401 567 #define RG_SYSPLL_EN_NORMAL BIT(15) 568 #define RG_SYSPLL_VODEN BIT(14) 569 #define RG_SYSPLL_LF BIT(13) 570 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 571 #define RG_SYSPLL_LVROD_EN BIT(10) 572 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 573 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 574 #define RG_SYSPLL_FBKSEL BIT(4) 575 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 576 577 #define CORE_PLL_GROUP4 0x403 578 #define RG_SYSPLL_DDSFBK_EN BIT(12) 579 #define RG_SYSPLL_BIAS_EN BIT(11) 580 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 581 #define MT7531_PHY_PLL_OFF BIT(5) 582 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 583 584 #define MT753X_CTRL_PHY_ADDR 0 585 586 #define CORE_PLL_GROUP5 0x404 587 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 588 589 #define CORE_PLL_GROUP6 0x405 590 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 591 592 #define CORE_PLL_GROUP7 0x406 593 #define RG_LCDDS_PWDB BIT(15) 594 #define RG_LCDDS_ISO_EN BIT(13) 595 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 596 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 597 598 #define CORE_PLL_GROUP10 0x409 599 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 600 601 #define CORE_PLL_GROUP11 0x40a 602 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 603 604 #define CORE_GSWPLL_GRP1 0x40d 605 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 606 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 607 #define RG_GSWPLL_EN_PRE BIT(11) 608 #define RG_GSWPLL_FBKSEL BIT(10) 609 #define RG_GSWPLL_BP BIT(9) 610 #define RG_GSWPLL_BR BIT(8) 611 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 612 613 #define CORE_GSWPLL_GRP2 0x40e 614 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 615 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 616 617 #define CORE_TRGMII_GSW_CLK_CG 0x410 618 #define REG_GSWCK_EN BIT(0) 619 #define REG_TRGMIICK_EN BIT(1) 620 621 #define MIB_DESC(_s, _o, _n) \ 622 { \ 623 .size = (_s), \ 624 .offset = (_o), \ 625 .name = (_n), \ 626 } 627 628 struct mt7530_mib_desc { 629 unsigned int size; 630 unsigned int offset; 631 const char *name; 632 }; 633 634 struct mt7530_fdb { 635 u16 vid; 636 u8 port_mask; 637 u8 aging; 638 u8 mac[6]; 639 bool noarp; 640 }; 641 642 /* struct mt7530_port - This is the main data structure for holding the state 643 * of the port. 644 * @enable: The status used for show port is enabled or not. 645 * @pm: The matrix used to show all connections with the port. 646 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 647 * untagged frames will be assigned to the related VLAN. 648 * @vlan_filtering: The flags indicating whether the port that can recognize 649 * VLAN-tagged frames. 650 */ 651 struct mt7530_port { 652 bool enable; 653 u32 pm; 654 u16 pvid; 655 }; 656 657 /* Port 5 interface select definitions */ 658 enum p5_interface_select { 659 P5_DISABLED = 0, 660 P5_INTF_SEL_PHY_P0, 661 P5_INTF_SEL_PHY_P4, 662 P5_INTF_SEL_GMAC5, 663 P5_INTF_SEL_GMAC5_SGMII, 664 }; 665 666 static const char *p5_intf_modes(unsigned int p5_interface) 667 { 668 switch (p5_interface) { 669 case P5_DISABLED: 670 return "DISABLED"; 671 case P5_INTF_SEL_PHY_P0: 672 return "PHY P0"; 673 case P5_INTF_SEL_PHY_P4: 674 return "PHY P4"; 675 case P5_INTF_SEL_GMAC5: 676 return "GMAC5"; 677 case P5_INTF_SEL_GMAC5_SGMII: 678 return "GMAC5_SGMII"; 679 default: 680 return "unknown"; 681 } 682 } 683 684 /* struct mt753x_info - This is the main data structure for holding the specific 685 * part for each supported device 686 * @sw_setup: Holding the handler to a device initialization 687 * @phy_read: Holding the way reading PHY port 688 * @phy_write: Holding the way writing PHY port 689 * @pad_setup: Holding the way setting up the bus pad for a certain 690 * MAC port 691 * @phy_mode_supported: Check if the PHY type is being supported on a certain 692 * port 693 * @mac_port_validate: Holding the way to set addition validate type for a 694 * certan MAC port 695 * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain 696 * MAC port 697 * @mac_port_config: Holding the way setting up the PHY attribute to a 698 * certain MAC port 699 * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a 700 * certain MAC port 701 * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs 702 * of the certain MAC port 703 */ 704 struct mt753x_info { 705 enum mt753x_id id; 706 707 int (*sw_setup)(struct dsa_switch *ds); 708 int (*phy_read)(struct dsa_switch *ds, int port, int regnum); 709 int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val); 710 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); 711 int (*cpu_port_config)(struct dsa_switch *ds, int port); 712 bool (*phy_mode_supported)(struct dsa_switch *ds, int port, 713 const struct phylink_link_state *state); 714 void (*mac_port_validate)(struct dsa_switch *ds, int port, 715 unsigned long *supported); 716 int (*mac_port_get_state)(struct dsa_switch *ds, int port, 717 struct phylink_link_state *state); 718 int (*mac_port_config)(struct dsa_switch *ds, int port, 719 unsigned int mode, 720 phy_interface_t interface); 721 void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port); 722 void (*mac_pcs_link_up)(struct dsa_switch *ds, int port, 723 unsigned int mode, phy_interface_t interface, 724 int speed, int duplex); 725 }; 726 727 /* struct mt7530_priv - This is the main data structure for holding the state 728 * of the driver 729 * @dev: The device pointer 730 * @ds: The pointer to the dsa core structure 731 * @bus: The bus used for the device and built-in PHY 732 * @rstc: The pointer to reset control used by MCM 733 * @core_pwr: The power supplied into the core 734 * @io_pwr: The power supplied into the I/O 735 * @reset: The descriptor for GPIO line tied to its reset pin 736 * @mcm: Flag for distinguishing if standalone IC or module 737 * coupling 738 * @ports: Holding the state among ports 739 * @reg_mutex: The lock for protecting among process accessing 740 * registers 741 * @p6_interface Holding the current port 6 interface 742 * @p5_intf_sel: Holding the current port 5 interface select 743 */ 744 struct mt7530_priv { 745 struct device *dev; 746 struct dsa_switch *ds; 747 struct mii_bus *bus; 748 struct reset_control *rstc; 749 struct regulator *core_pwr; 750 struct regulator *io_pwr; 751 struct gpio_desc *reset; 752 const struct mt753x_info *info; 753 unsigned int id; 754 bool mcm; 755 phy_interface_t p6_interface; 756 phy_interface_t p5_interface; 757 unsigned int p5_intf_sel; 758 u8 mirror_rx; 759 u8 mirror_tx; 760 761 struct mt7530_port ports[MT7530_NUM_PORTS]; 762 /* protect among processes for registers access*/ 763 struct mutex reg_mutex; 764 }; 765 766 struct mt7530_hw_vlan_entry { 767 int port; 768 u8 old_members; 769 bool untagged; 770 }; 771 772 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 773 int port, bool untagged) 774 { 775 e->port = port; 776 e->untagged = untagged; 777 } 778 779 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 780 struct mt7530_hw_vlan_entry *); 781 782 struct mt7530_hw_stats { 783 const char *string; 784 u16 reg; 785 u8 sizeof_stat; 786 }; 787 788 struct mt7530_dummy_poll { 789 struct mt7530_priv *priv; 790 u32 reg; 791 }; 792 793 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 794 struct mt7530_priv *priv, u32 reg) 795 { 796 p->priv = priv; 797 p->reg = reg; 798 } 799 800 #endif /* __MT7530_H */ 801