1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>; /* GICR */ 39 /* 40 * vcpumntirq: 41 * virtual CPU interface maintenance interrupt 42 */ 43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 44 45 gic_its: gic-its@1820000 { 46 compatible = "arm,gic-v3-its"; 47 reg = <0x00 0x01820000 0x00 0x10000>; 48 socionext,synquacer-pre-its = <0x1000000 0x400000>; 49 msi-controller; 50 #msi-cells = <1>; 51 }; 52 }; 53 54 serdes0: serdes@900000 { 55 compatible = "ti,phy-am654-serdes"; 56 reg = <0x0 0x900000 0x0 0x2000>; 57 reg-names = "serdes"; 58 #phy-cells = <2>; 59 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 60 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 61 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 62 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 63 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 64 ti,serdes-clk = <&serdes0_clk>; 65 #clock-cells = <1>; 66 mux-controls = <&serdes_mux 0>; 67 }; 68 69 serdes1: serdes@910000 { 70 compatible = "ti,phy-am654-serdes"; 71 reg = <0x0 0x910000 0x0 0x2000>; 72 reg-names = "serdes"; 73 #phy-cells = <2>; 74 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 75 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 76 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 77 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 78 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 79 ti,serdes-clk = <&serdes1_clk>; 80 #clock-cells = <1>; 81 mux-controls = <&serdes_mux 1>; 82 }; 83 84 main_uart0: serial@2800000 { 85 compatible = "ti,am654-uart"; 86 reg = <0x00 0x02800000 0x00 0x100>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 90 clock-frequency = <48000000>; 91 current-speed = <115200>; 92 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 93 }; 94 95 main_uart1: serial@2810000 { 96 compatible = "ti,am654-uart"; 97 reg = <0x00 0x02810000 0x00 0x100>; 98 reg-shift = <2>; 99 reg-io-width = <4>; 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 clock-frequency = <48000000>; 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 103 }; 104 105 main_uart2: serial@2820000 { 106 compatible = "ti,am654-uart"; 107 reg = <0x00 0x02820000 0x00 0x100>; 108 reg-shift = <2>; 109 reg-io-width = <4>; 110 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 111 clock-frequency = <48000000>; 112 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 113 }; 114 115 main_pmx0: pinmux@11c000 { 116 compatible = "pinctrl-single"; 117 reg = <0x0 0x11c000 0x0 0x2e4>; 118 #pinctrl-cells = <1>; 119 pinctrl-single,register-width = <32>; 120 pinctrl-single,function-mask = <0xffffffff>; 121 }; 122 123 main_pmx1: pinmux@11c2e8 { 124 compatible = "pinctrl-single"; 125 reg = <0x0 0x11c2e8 0x0 0x24>; 126 #pinctrl-cells = <1>; 127 pinctrl-single,register-width = <32>; 128 pinctrl-single,function-mask = <0xffffffff>; 129 }; 130 131 main_i2c0: i2c@2000000 { 132 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 133 reg = <0x0 0x2000000 0x0 0x100>; 134 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 clock-names = "fck"; 138 clocks = <&k3_clks 110 1>; 139 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 140 }; 141 142 main_i2c1: i2c@2010000 { 143 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 144 reg = <0x0 0x2010000 0x0 0x100>; 145 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clock-names = "fck"; 149 clocks = <&k3_clks 111 1>; 150 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 151 }; 152 153 main_i2c2: i2c@2020000 { 154 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 155 reg = <0x0 0x2020000 0x0 0x100>; 156 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 clock-names = "fck"; 160 clocks = <&k3_clks 112 1>; 161 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 162 }; 163 164 main_i2c3: i2c@2030000 { 165 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 166 reg = <0x0 0x2030000 0x0 0x100>; 167 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clock-names = "fck"; 171 clocks = <&k3_clks 113 1>; 172 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 173 }; 174 175 ecap0: pwm@3100000 { 176 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 177 #pwm-cells = <3>; 178 reg = <0x0 0x03100000 0x0 0x60>; 179 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 180 clocks = <&k3_clks 39 0>; 181 clock-names = "fck"; 182 }; 183 184 main_spi0: spi@2100000 { 185 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 186 reg = <0x0 0x2100000 0x0 0x400>; 187 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&k3_clks 137 1>; 189 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 193 dma-names = "tx0", "rx0"; 194 }; 195 196 main_spi1: spi@2110000 { 197 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 198 reg = <0x0 0x2110000 0x0 0x400>; 199 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&k3_clks 138 1>; 201 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 assigned-clocks = <&k3_clks 137 1>; 205 assigned-clock-rates = <48000000>; 206 }; 207 208 main_spi2: spi@2120000 { 209 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 210 reg = <0x0 0x2120000 0x0 0x400>; 211 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&k3_clks 139 1>; 213 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 }; 217 218 main_spi3: spi@2130000 { 219 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 220 reg = <0x0 0x2130000 0x0 0x400>; 221 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&k3_clks 140 1>; 223 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 }; 227 228 main_spi4: spi@2140000 { 229 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 230 reg = <0x0 0x2140000 0x0 0x400>; 231 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&k3_clks 141 1>; 233 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 }; 237 238 sdhci0: sdhci@4f80000 { 239 compatible = "ti,am654-sdhci-5.1"; 240 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 241 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 242 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 243 clock-names = "clk_ahb", "clk_xin"; 244 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 245 mmc-ddr-1_8v; 246 mmc-hs200-1_8v; 247 ti,otap-del-sel = <0x2>; 248 ti,trm-icp = <0x8>; 249 dma-coherent; 250 }; 251 252 scm_conf: scm_conf@100000 { 253 compatible = "syscon", "simple-mfd"; 254 reg = <0 0x00100000 0 0x1c000>; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 ranges = <0x0 0x0 0x00100000 0x1c000>; 258 259 pcie0_mode: pcie-mode@4060 { 260 compatible = "syscon"; 261 reg = <0x00004060 0x4>; 262 }; 263 264 pcie1_mode: pcie-mode@4070 { 265 compatible = "syscon"; 266 reg = <0x00004070 0x4>; 267 }; 268 269 pcie_devid: pcie-devid@210 { 270 compatible = "syscon"; 271 reg = <0x00000210 0x4>; 272 }; 273 274 serdes0_clk: serdes_clk@4080 { 275 compatible = "syscon"; 276 reg = <0x00004080 0x4>; 277 }; 278 279 serdes1_clk: serdes_clk@4090 { 280 compatible = "syscon"; 281 reg = <0x00004090 0x4>; 282 }; 283 284 serdes_mux: mux-controller { 285 compatible = "mmio-mux"; 286 #mux-control-cells = <1>; 287 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 288 <0x4090 0x3>; /* SERDES1 lane select */ 289 }; 290 }; 291 292 dwc3_0: dwc3@4000000 { 293 compatible = "ti,am654-dwc3"; 294 reg = <0x0 0x4000000 0x0 0x4000>; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 ranges = <0x0 0x0 0x4000000 0x20000>; 298 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 299 dma-coherent; 300 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 301 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 302 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 303 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 304 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 305 306 usb0: usb@10000 { 307 compatible = "snps,dwc3"; 308 reg = <0x10000 0x10000>; 309 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 312 interrupt-names = "peripheral", 313 "host", 314 "otg"; 315 maximum-speed = "high-speed"; 316 dr_mode = "otg"; 317 phys = <&usb0_phy>; 318 phy-names = "usb2-phy"; 319 snps,dis_u3_susphy_quirk; 320 }; 321 }; 322 323 usb0_phy: phy@4100000 { 324 compatible = "ti,am654-usb2", "ti,omap-usb2"; 325 reg = <0x0 0x4100000 0x0 0x54>; 326 syscon-phy-power = <&scm_conf 0x4000>; 327 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 328 clock-names = "wkupclk", "refclk"; 329 #phy-cells = <0>; 330 }; 331 332 dwc3_1: dwc3@4020000 { 333 compatible = "ti,am654-dwc3"; 334 reg = <0x0 0x4020000 0x0 0x4000>; 335 #address-cells = <1>; 336 #size-cells = <1>; 337 ranges = <0x0 0x0 0x4020000 0x20000>; 338 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 339 dma-coherent; 340 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 341 clocks = <&k3_clks 152 2>; 342 assigned-clocks = <&k3_clks 152 2>; 343 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 344 345 usb1: usb@10000 { 346 compatible = "snps,dwc3"; 347 reg = <0x10000 0x10000>; 348 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 351 interrupt-names = "peripheral", 352 "host", 353 "otg"; 354 maximum-speed = "high-speed"; 355 dr_mode = "otg"; 356 phys = <&usb1_phy>; 357 phy-names = "usb2-phy"; 358 }; 359 }; 360 361 usb1_phy: phy@4110000 { 362 compatible = "ti,am654-usb2", "ti,omap-usb2"; 363 reg = <0x0 0x4110000 0x0 0x54>; 364 syscon-phy-power = <&scm_conf 0x4020>; 365 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 366 clock-names = "wkupclk", "refclk"; 367 #phy-cells = <0>; 368 }; 369 370 intr_main_gpio: interrupt-controller0 { 371 compatible = "ti,sci-intr"; 372 ti,intr-trigger-type = <1>; 373 interrupt-controller; 374 interrupt-parent = <&gic500>; 375 #interrupt-cells = <2>; 376 ti,sci = <&dmsc>; 377 ti,sci-dst-id = <56>; 378 ti,sci-rm-range-girq = <0x1>; 379 }; 380 381 main_navss { 382 compatible = "simple-mfd"; 383 #address-cells = <2>; 384 #size-cells = <2>; 385 ranges; 386 dma-coherent; 387 dma-ranges; 388 389 ti,sci-dev-id = <118>; 390 391 intr_main_navss: interrupt-controller1 { 392 compatible = "ti,sci-intr"; 393 ti,intr-trigger-type = <4>; 394 interrupt-controller; 395 interrupt-parent = <&gic500>; 396 #interrupt-cells = <2>; 397 ti,sci = <&dmsc>; 398 ti,sci-dst-id = <56>; 399 ti,sci-rm-range-girq = <0x0>, <0x2>; 400 }; 401 402 inta_main_udmass: interrupt-controller@33d00000 { 403 compatible = "ti,sci-inta"; 404 reg = <0x0 0x33d00000 0x0 0x100000>; 405 interrupt-controller; 406 interrupt-parent = <&intr_main_navss>; 407 msi-controller; 408 ti,sci = <&dmsc>; 409 ti,sci-dev-id = <179>; 410 ti,sci-rm-range-vint = <0x0>; 411 ti,sci-rm-range-global-event = <0x1>; 412 }; 413 414 secure_proxy_main: mailbox@32c00000 { 415 compatible = "ti,am654-secure-proxy"; 416 #mbox-cells = <1>; 417 reg-names = "target_data", "rt", "scfg"; 418 reg = <0x00 0x32c00000 0x00 0x100000>, 419 <0x00 0x32400000 0x00 0x100000>, 420 <0x00 0x32800000 0x00 0x100000>; 421 interrupt-names = "rx_011"; 422 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 423 }; 424 425 hwspinlock: spinlock@30e00000 { 426 compatible = "ti,am654-hwspinlock"; 427 reg = <0x00 0x30e00000 0x00 0x1000>; 428 #hwlock-cells = <1>; 429 }; 430 431 mailbox0_cluster0: mailbox@31f80000 { 432 compatible = "ti,am654-mailbox"; 433 reg = <0x00 0x31f80000 0x00 0x200>; 434 #mbox-cells = <1>; 435 ti,mbox-num-users = <4>; 436 ti,mbox-num-fifos = <16>; 437 interrupt-parent = <&intr_main_navss>; 438 }; 439 440 mailbox0_cluster1: mailbox@31f81000 { 441 compatible = "ti,am654-mailbox"; 442 reg = <0x00 0x31f81000 0x00 0x200>; 443 #mbox-cells = <1>; 444 ti,mbox-num-users = <4>; 445 ti,mbox-num-fifos = <16>; 446 interrupt-parent = <&intr_main_navss>; 447 }; 448 449 mailbox0_cluster2: mailbox@31f82000 { 450 compatible = "ti,am654-mailbox"; 451 reg = <0x00 0x31f82000 0x00 0x200>; 452 #mbox-cells = <1>; 453 ti,mbox-num-users = <4>; 454 ti,mbox-num-fifos = <16>; 455 interrupt-parent = <&intr_main_navss>; 456 }; 457 458 mailbox0_cluster3: mailbox@31f83000 { 459 compatible = "ti,am654-mailbox"; 460 reg = <0x00 0x31f83000 0x00 0x200>; 461 #mbox-cells = <1>; 462 ti,mbox-num-users = <4>; 463 ti,mbox-num-fifos = <16>; 464 interrupt-parent = <&intr_main_navss>; 465 }; 466 467 mailbox0_cluster4: mailbox@31f84000 { 468 compatible = "ti,am654-mailbox"; 469 reg = <0x00 0x31f84000 0x00 0x200>; 470 #mbox-cells = <1>; 471 ti,mbox-num-users = <4>; 472 ti,mbox-num-fifos = <16>; 473 interrupt-parent = <&intr_main_navss>; 474 }; 475 476 mailbox0_cluster5: mailbox@31f85000 { 477 compatible = "ti,am654-mailbox"; 478 reg = <0x00 0x31f85000 0x00 0x200>; 479 #mbox-cells = <1>; 480 ti,mbox-num-users = <4>; 481 ti,mbox-num-fifos = <16>; 482 interrupt-parent = <&intr_main_navss>; 483 }; 484 485 mailbox0_cluster6: mailbox@31f86000 { 486 compatible = "ti,am654-mailbox"; 487 reg = <0x00 0x31f86000 0x00 0x200>; 488 #mbox-cells = <1>; 489 ti,mbox-num-users = <4>; 490 ti,mbox-num-fifos = <16>; 491 interrupt-parent = <&intr_main_navss>; 492 }; 493 494 mailbox0_cluster7: mailbox@31f87000 { 495 compatible = "ti,am654-mailbox"; 496 reg = <0x00 0x31f87000 0x00 0x200>; 497 #mbox-cells = <1>; 498 ti,mbox-num-users = <4>; 499 ti,mbox-num-fifos = <16>; 500 interrupt-parent = <&intr_main_navss>; 501 }; 502 503 mailbox0_cluster8: mailbox@31f88000 { 504 compatible = "ti,am654-mailbox"; 505 reg = <0x00 0x31f88000 0x00 0x200>; 506 #mbox-cells = <1>; 507 ti,mbox-num-users = <4>; 508 ti,mbox-num-fifos = <16>; 509 interrupt-parent = <&intr_main_navss>; 510 }; 511 512 mailbox0_cluster9: mailbox@31f89000 { 513 compatible = "ti,am654-mailbox"; 514 reg = <0x00 0x31f89000 0x00 0x200>; 515 #mbox-cells = <1>; 516 ti,mbox-num-users = <4>; 517 ti,mbox-num-fifos = <16>; 518 interrupt-parent = <&intr_main_navss>; 519 }; 520 521 mailbox0_cluster10: mailbox@31f8a000 { 522 compatible = "ti,am654-mailbox"; 523 reg = <0x00 0x31f8a000 0x00 0x200>; 524 #mbox-cells = <1>; 525 ti,mbox-num-users = <4>; 526 ti,mbox-num-fifos = <16>; 527 interrupt-parent = <&intr_main_navss>; 528 }; 529 530 mailbox0_cluster11: mailbox@31f8b000 { 531 compatible = "ti,am654-mailbox"; 532 reg = <0x00 0x31f8b000 0x00 0x200>; 533 #mbox-cells = <1>; 534 ti,mbox-num-users = <4>; 535 ti,mbox-num-fifos = <16>; 536 interrupt-parent = <&intr_main_navss>; 537 }; 538 539 ringacc: ringacc@3c000000 { 540 compatible = "ti,am654-navss-ringacc"; 541 reg = <0x0 0x3c000000 0x0 0x400000>, 542 <0x0 0x38000000 0x0 0x400000>, 543 <0x0 0x31120000 0x0 0x100>, 544 <0x0 0x33000000 0x0 0x40000>; 545 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 546 ti,num-rings = <818>; 547 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ 548 ti,dma-ring-reset-quirk; 549 ti,sci = <&dmsc>; 550 ti,sci-dev-id = <187>; 551 msi-parent = <&inta_main_udmass>; 552 }; 553 554 main_udmap: dma-controller@31150000 { 555 compatible = "ti,am654-navss-main-udmap"; 556 reg = <0x0 0x31150000 0x0 0x100>, 557 <0x0 0x34000000 0x0 0x100000>, 558 <0x0 0x35000000 0x0 0x100000>; 559 reg-names = "gcfg", "rchanrt", "tchanrt"; 560 msi-parent = <&inta_main_udmass>; 561 #dma-cells = <1>; 562 563 ti,sci = <&dmsc>; 564 ti,sci-dev-id = <188>; 565 ti,ringacc = <&ringacc>; 566 567 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ 568 <0x2>; /* TX_CHAN */ 569 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */ 570 <0x5>; /* RX_CHAN */ 571 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */ 572 }; 573 }; 574 575 main_gpio0: main_gpio0@600000 { 576 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 577 reg = <0x0 0x600000 0x0 0x100>; 578 gpio-controller; 579 #gpio-cells = <2>; 580 interrupt-parent = <&intr_main_gpio>; 581 interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>, 582 <57 261>; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 ti,ngpio = <96>; 586 ti,davinci-gpio-unbanked = <0>; 587 clocks = <&k3_clks 57 0>; 588 clock-names = "gpio"; 589 }; 590 591 main_gpio1: main_gpio1@601000 { 592 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 593 reg = <0x0 0x601000 0x0 0x100>; 594 gpio-controller; 595 #gpio-cells = <2>; 596 interrupt-parent = <&intr_main_gpio>; 597 interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>, 598 <58 261>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 ti,ngpio = <90>; 602 ti,davinci-gpio-unbanked = <0>; 603 clocks = <&k3_clks 58 0>; 604 clock-names = "gpio"; 605 }; 606 607 pcie0_rc: pcie@5500000 { 608 compatible = "ti,am654-pcie-rc"; 609 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 610 reg-names = "app", "dbics", "config", "atu"; 611 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 612 #address-cells = <3>; 613 #size-cells = <2>; 614 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 615 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 616 ti,syscon-pcie-id = <&pcie_devid>; 617 ti,syscon-pcie-mode = <&pcie0_mode>; 618 bus-range = <0x0 0xff>; 619 num-viewport = <16>; 620 max-link-speed = <3>; 621 dma-coherent; 622 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 623 msi-map = <0x0 &gic_its 0x0 0x10000>; 624 }; 625 626 pcie0_ep: pcie-ep@5500000 { 627 compatible = "ti,am654-pcie-ep"; 628 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 629 reg-names = "app", "dbics", "addr_space", "atu"; 630 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 631 ti,syscon-pcie-mode = <&pcie0_mode>; 632 num-ib-windows = <16>; 633 num-ob-windows = <16>; 634 max-link-speed = <3>; 635 dma-coherent; 636 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 637 }; 638 639 pcie1_rc: pcie@5600000 { 640 compatible = "ti,am654-pcie-rc"; 641 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 642 reg-names = "app", "dbics", "config", "atu"; 643 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 644 #address-cells = <3>; 645 #size-cells = <2>; 646 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 647 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 648 ti,syscon-pcie-id = <&pcie_devid>; 649 ti,syscon-pcie-mode = <&pcie1_mode>; 650 bus-range = <0x0 0xff>; 651 num-viewport = <16>; 652 max-link-speed = <3>; 653 dma-coherent; 654 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 655 msi-map = <0x0 &gic_its 0x10000 0x10000>; 656 }; 657 658 pcie1_ep: pcie-ep@5600000 { 659 compatible = "ti,am654-pcie-ep"; 660 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 661 reg-names = "app", "dbics", "addr_space", "atu"; 662 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 663 ti,syscon-pcie-mode = <&pcie1_mode>; 664 num-ib-windows = <16>; 665 num-ob-windows = <16>; 666 max-link-speed = <3>; 667 dma-coherent; 668 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 669 }; 670 671 mcasp0: mcasp@2b00000 { 672 compatible = "ti,am33xx-mcasp-audio"; 673 reg = <0x0 0x02b00000 0x0 0x2000>, 674 <0x0 0x02b08000 0x0 0x1000>; 675 reg-names = "mpu","dat"; 676 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 678 interrupt-names = "tx", "rx"; 679 680 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 681 dma-names = "tx", "rx"; 682 683 clocks = <&k3_clks 104 0>; 684 clock-names = "fck"; 685 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 686 687 status = "disabled"; 688 }; 689 690 mcasp1: mcasp@2b10000 { 691 compatible = "ti,am33xx-mcasp-audio"; 692 reg = <0x0 0x02b10000 0x0 0x2000>, 693 <0x0 0x02b18000 0x0 0x1000>; 694 reg-names = "mpu","dat"; 695 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 697 interrupt-names = "tx", "rx"; 698 699 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 700 dma-names = "tx", "rx"; 701 702 clocks = <&k3_clks 105 0>; 703 clock-names = "fck"; 704 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 705 706 status = "disabled"; 707 }; 708 709 mcasp2: mcasp@2b20000 { 710 compatible = "ti,am33xx-mcasp-audio"; 711 reg = <0x0 0x02b20000 0x0 0x2000>, 712 <0x0 0x02b28000 0x0 0x1000>; 713 reg-names = "mpu","dat"; 714 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 716 interrupt-names = "tx", "rx"; 717 718 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 719 dma-names = "tx", "rx"; 720 721 clocks = <&k3_clks 106 0>; 722 clock-names = "fck"; 723 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 724 725 status = "disabled"; 726 }; 727 728 cal: cal@6f03000 { 729 compatible = "ti,am654-cal"; 730 reg = <0x0 0x06f03000 0x0 0x400>, 731 <0x0 0x06f03800 0x0 0x40>; 732 reg-names = "cal_top", 733 "cal_rx_core0"; 734 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 735 ti,camerrx-control = <&scm_conf 0x40c0>; 736 clock-names = "fck"; 737 clocks = <&k3_clks 2 0>; 738 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 739 740 ports { 741 #address-cells = <1>; 742 #size-cells = <0>; 743 744 csi2_0: port@0 { 745 reg = <0>; 746 }; 747 }; 748 }; 749}; 750