xref: /linux/arch/riscv/include/asm/csr.h (revision 22d55f02b8922a097cd4be1e2f131dfa7ef65901)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2015 Regents of the University of California
4  */
5 
6 #ifndef _ASM_RISCV_CSR_H
7 #define _ASM_RISCV_CSR_H
8 
9 #include <asm/asm.h>
10 #include <linux/const.h>
11 
12 /* Status register flags */
13 #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
15 #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
16 #define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
17 
18 #define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
19 #define SR_FS_OFF	_AC(0x00000000, UL)
20 #define SR_FS_INITIAL	_AC(0x00002000, UL)
21 #define SR_FS_CLEAN	_AC(0x00004000, UL)
22 #define SR_FS_DIRTY	_AC(0x00006000, UL)
23 
24 #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
25 #define SR_XS_OFF	_AC(0x00000000, UL)
26 #define SR_XS_INITIAL	_AC(0x00008000, UL)
27 #define SR_XS_CLEAN	_AC(0x00010000, UL)
28 #define SR_XS_DIRTY	_AC(0x00018000, UL)
29 
30 #ifndef CONFIG_64BIT
31 #define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
32 #else
33 #define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
34 #endif
35 
36 /* SATP flags */
37 #ifndef CONFIG_64BIT
38 #define SATP_PPN	_AC(0x003FFFFF, UL)
39 #define SATP_MODE_32	_AC(0x80000000, UL)
40 #define SATP_MODE	SATP_MODE_32
41 #else
42 #define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
43 #define SATP_MODE_39	_AC(0x8000000000000000, UL)
44 #define SATP_MODE	SATP_MODE_39
45 #endif
46 
47 /* SCAUSE */
48 #define SCAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
49 
50 #define IRQ_U_SOFT		0
51 #define IRQ_S_SOFT		1
52 #define IRQ_M_SOFT		3
53 #define IRQ_U_TIMER		4
54 #define IRQ_S_TIMER		5
55 #define IRQ_M_TIMER		7
56 #define IRQ_U_EXT		8
57 #define IRQ_S_EXT		9
58 #define IRQ_M_EXT		11
59 
60 #define EXC_INST_MISALIGNED	0
61 #define EXC_INST_ACCESS		1
62 #define EXC_BREAKPOINT		3
63 #define EXC_LOAD_ACCESS		5
64 #define EXC_STORE_ACCESS	7
65 #define EXC_SYSCALL		8
66 #define EXC_INST_PAGE_FAULT	12
67 #define EXC_LOAD_PAGE_FAULT	13
68 #define EXC_STORE_PAGE_FAULT	15
69 
70 /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
71 #define SIE_SSIE		(_AC(0x1, UL) << IRQ_S_SOFT)
72 #define SIE_STIE		(_AC(0x1, UL) << IRQ_S_TIMER)
73 #define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
74 
75 #define CSR_CYCLE		0xc00
76 #define CSR_TIME		0xc01
77 #define CSR_INSTRET		0xc02
78 #define CSR_SSTATUS		0x100
79 #define CSR_SIE			0x104
80 #define CSR_STVEC		0x105
81 #define CSR_SCOUNTEREN		0x106
82 #define CSR_SSCRATCH		0x140
83 #define CSR_SEPC		0x141
84 #define CSR_SCAUSE		0x142
85 #define CSR_STVAL		0x143
86 #define CSR_SIP			0x144
87 #define CSR_SATP		0x180
88 #define CSR_CYCLEH		0xc80
89 #define CSR_TIMEH		0xc81
90 #define CSR_INSTRETH		0xc82
91 
92 #ifndef __ASSEMBLY__
93 
94 #define csr_swap(csr, val)					\
95 ({								\
96 	unsigned long __v = (unsigned long)(val);		\
97 	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
98 			      : "=r" (__v) : "rK" (__v)		\
99 			      : "memory");			\
100 	__v;							\
101 })
102 
103 #define csr_read(csr)						\
104 ({								\
105 	register unsigned long __v;				\
106 	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
107 			      : "=r" (__v) :			\
108 			      : "memory");			\
109 	__v;							\
110 })
111 
112 #define csr_write(csr, val)					\
113 ({								\
114 	unsigned long __v = (unsigned long)(val);		\
115 	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
116 			      : : "rK" (__v)			\
117 			      : "memory");			\
118 })
119 
120 #define csr_read_set(csr, val)					\
121 ({								\
122 	unsigned long __v = (unsigned long)(val);		\
123 	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
124 			      : "=r" (__v) : "rK" (__v)		\
125 			      : "memory");			\
126 	__v;							\
127 })
128 
129 #define csr_set(csr, val)					\
130 ({								\
131 	unsigned long __v = (unsigned long)(val);		\
132 	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
133 			      : : "rK" (__v)			\
134 			      : "memory");			\
135 })
136 
137 #define csr_read_clear(csr, val)				\
138 ({								\
139 	unsigned long __v = (unsigned long)(val);		\
140 	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
141 			      : "=r" (__v) : "rK" (__v)		\
142 			      : "memory");			\
143 	__v;							\
144 })
145 
146 #define csr_clear(csr, val)					\
147 ({								\
148 	unsigned long __v = (unsigned long)(val);		\
149 	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
150 			      : : "rK" (__v)			\
151 			      : "memory");			\
152 })
153 
154 #endif /* __ASSEMBLY__ */
155 
156 #endif /* _ASM_RISCV_CSR_H */
157