1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2012 Regents of the University of California 4 * Copyright (C) 2017 SiFive 5 */ 6 7#include <linux/init.h> 8#include <linux/linkage.h> 9 10#include <asm/asm.h> 11#include <asm/csr.h> 12#include <asm/scs.h> 13#include <asm/unistd.h> 14#include <asm/page.h> 15#include <asm/thread_info.h> 16#include <asm/asm-offsets.h> 17#include <asm/errata_list.h> 18#include <linux/sizes.h> 19 20 .section .irqentry.text, "ax" 21 22SYM_CODE_START(handle_exception) 23 /* 24 * If coming from userspace, preserve the user thread pointer and load 25 * the kernel thread pointer. If we came from the kernel, the scratch 26 * register will contain 0, and we should continue on the current TP. 27 */ 28 csrrw tp, CSR_SCRATCH, tp 29 bnez tp, .Lsave_context 30 31.Lrestore_kernel_tpsp: 32 csrr tp, CSR_SCRATCH 33 REG_S sp, TASK_TI_KERNEL_SP(tp) 34 35#ifdef CONFIG_VMAP_STACK 36 addi sp, sp, -(PT_SIZE_ON_STACK) 37 srli sp, sp, THREAD_SHIFT 38 andi sp, sp, 0x1 39 bnez sp, handle_kernel_stack_overflow 40 REG_L sp, TASK_TI_KERNEL_SP(tp) 41#endif 42 43.Lsave_context: 44 REG_S sp, TASK_TI_USER_SP(tp) 45 REG_L sp, TASK_TI_KERNEL_SP(tp) 46 addi sp, sp, -(PT_SIZE_ON_STACK) 47 REG_S x1, PT_RA(sp) 48 REG_S x3, PT_GP(sp) 49 REG_S x5, PT_T0(sp) 50 save_from_x6_to_x31 51 52 /* 53 * Disable user-mode memory access as it should only be set in the 54 * actual user copy routines. 55 * 56 * Disable the FPU/Vector to detect illegal usage of floating point 57 * or vector in kernel space. 58 */ 59 li t0, SR_SUM | SR_FS_VS 60 61 REG_L s0, TASK_TI_USER_SP(tp) 62 csrrc s1, CSR_STATUS, t0 63 csrr s2, CSR_EPC 64 csrr s3, CSR_TVAL 65 csrr s4, CSR_CAUSE 66 csrr s5, CSR_SCRATCH 67 REG_S s0, PT_SP(sp) 68 REG_S s1, PT_STATUS(sp) 69 REG_S s2, PT_EPC(sp) 70 REG_S s3, PT_BADADDR(sp) 71 REG_S s4, PT_CAUSE(sp) 72 REG_S s5, PT_TP(sp) 73 74 /* 75 * Set the scratch register to 0, so that if a recursive exception 76 * occurs, the exception vector knows it came from the kernel 77 */ 78 csrw CSR_SCRATCH, x0 79 80 /* Load the global pointer */ 81 load_global_pointer 82 83 /* Load the kernel shadow call stack pointer if coming from userspace */ 84 scs_load_current_if_task_changed s5 85 86 move a0, sp /* pt_regs */ 87 la ra, ret_from_exception 88 89 /* 90 * MSB of cause differentiates between 91 * interrupts and exceptions 92 */ 93 bge s4, zero, 1f 94 95 /* Handle interrupts */ 96 tail do_irq 971: 98 /* Handle other exceptions */ 99 slli t0, s4, RISCV_LGPTR 100 la t1, excp_vect_table 101 la t2, excp_vect_table_end 102 add t0, t1, t0 103 /* Check if exception code lies within bounds */ 104 bgeu t0, t2, 1f 105 REG_L t0, 0(t0) 106 jr t0 1071: 108 tail do_trap_unknown 109SYM_CODE_END(handle_exception) 110 111/* 112 * The ret_from_exception must be called with interrupt disabled. Here is the 113 * caller list: 114 * - handle_exception 115 * - ret_from_fork 116 */ 117SYM_CODE_START_NOALIGN(ret_from_exception) 118 REG_L s0, PT_STATUS(sp) 119#ifdef CONFIG_RISCV_M_MODE 120 /* the MPP value is too large to be used as an immediate arg for addi */ 121 li t0, SR_MPP 122 and s0, s0, t0 123#else 124 andi s0, s0, SR_SPP 125#endif 126 bnez s0, 1f 127 128 /* Save unwound kernel stack pointer in thread_info */ 129 addi s0, sp, PT_SIZE_ON_STACK 130 REG_S s0, TASK_TI_KERNEL_SP(tp) 131 132 /* Save the kernel shadow call stack pointer */ 133 scs_save_current 134 135 /* 136 * Save TP into the scratch register , so we can find the kernel data 137 * structures again. 138 */ 139 csrw CSR_SCRATCH, tp 1401: 141 REG_L a0, PT_STATUS(sp) 142 /* 143 * The current load reservation is effectively part of the processor's 144 * state, in the sense that load reservations cannot be shared between 145 * different hart contexts. We can't actually save and restore a load 146 * reservation, so instead here we clear any existing reservation -- 147 * it's always legal for implementations to clear load reservations at 148 * any point (as long as the forward progress guarantee is kept, but 149 * we'll ignore that here). 150 * 151 * Dangling load reservations can be the result of taking a trap in the 152 * middle of an LR/SC sequence, but can also be the result of a taken 153 * forward branch around an SC -- which is how we implement CAS. As a 154 * result we need to clear reservations between the last CAS and the 155 * jump back to the new context. While it is unlikely the store 156 * completes, implementations are allowed to expand reservations to be 157 * arbitrarily large. 158 */ 159 REG_L a2, PT_EPC(sp) 160 REG_SC x0, a2, PT_EPC(sp) 161 162 csrw CSR_STATUS, a0 163 csrw CSR_EPC, a2 164 165 REG_L x1, PT_RA(sp) 166 REG_L x3, PT_GP(sp) 167 REG_L x4, PT_TP(sp) 168 REG_L x5, PT_T0(sp) 169 restore_from_x6_to_x31 170 171 REG_L x2, PT_SP(sp) 172 173#ifdef CONFIG_RISCV_M_MODE 174 mret 175#else 176 sret 177#endif 178SYM_CODE_END(ret_from_exception) 179 180#ifdef CONFIG_VMAP_STACK 181SYM_CODE_START_LOCAL(handle_kernel_stack_overflow) 182 /* we reach here from kernel context, sscratch must be 0 */ 183 csrrw x31, CSR_SCRATCH, x31 184 asm_per_cpu sp, overflow_stack, x31 185 li x31, OVERFLOW_STACK_SIZE 186 add sp, sp, x31 187 /* zero out x31 again and restore x31 */ 188 xor x31, x31, x31 189 csrrw x31, CSR_SCRATCH, x31 190 191 addi sp, sp, -(PT_SIZE_ON_STACK) 192 193 //save context to overflow stack 194 REG_S x1, PT_RA(sp) 195 REG_S x3, PT_GP(sp) 196 REG_S x5, PT_T0(sp) 197 save_from_x6_to_x31 198 199 REG_L s0, TASK_TI_KERNEL_SP(tp) 200 csrr s1, CSR_STATUS 201 csrr s2, CSR_EPC 202 csrr s3, CSR_TVAL 203 csrr s4, CSR_CAUSE 204 csrr s5, CSR_SCRATCH 205 REG_S s0, PT_SP(sp) 206 REG_S s1, PT_STATUS(sp) 207 REG_S s2, PT_EPC(sp) 208 REG_S s3, PT_BADADDR(sp) 209 REG_S s4, PT_CAUSE(sp) 210 REG_S s5, PT_TP(sp) 211 move a0, sp 212 tail handle_bad_stack 213SYM_CODE_END(handle_kernel_stack_overflow) 214#endif 215 216SYM_CODE_START(ret_from_fork) 217 call schedule_tail 218 beqz s0, 1f /* not from kernel thread */ 219 /* Call fn(arg) */ 220 move a0, s1 221 jalr s0 2221: 223 move a0, sp /* pt_regs */ 224 la ra, ret_from_exception 225 tail syscall_exit_to_user_mode 226SYM_CODE_END(ret_from_fork) 227 228#ifdef CONFIG_IRQ_STACKS 229/* 230 * void call_on_irq_stack(struct pt_regs *regs, 231 * void (*func)(struct pt_regs *)); 232 * 233 * Calls func(regs) using the per-CPU IRQ stack. 234 */ 235SYM_FUNC_START(call_on_irq_stack) 236 /* Create a frame record to save ra and s0 (fp) */ 237 addi sp, sp, -STACKFRAME_SIZE_ON_STACK 238 REG_S ra, STACKFRAME_RA(sp) 239 REG_S s0, STACKFRAME_FP(sp) 240 addi s0, sp, STACKFRAME_SIZE_ON_STACK 241 242 /* Switch to the per-CPU shadow call stack */ 243 scs_save_current 244 scs_load_irq_stack t0 245 246 /* Switch to the per-CPU IRQ stack and call the handler */ 247 load_per_cpu t0, irq_stack_ptr, t1 248 li t1, IRQ_STACK_SIZE 249 add sp, t0, t1 250 jalr a1 251 252 /* Switch back to the thread shadow call stack */ 253 scs_load_current 254 255 /* Switch back to the thread stack and restore ra and s0 */ 256 addi sp, s0, -STACKFRAME_SIZE_ON_STACK 257 REG_L ra, STACKFRAME_RA(sp) 258 REG_L s0, STACKFRAME_FP(sp) 259 addi sp, sp, STACKFRAME_SIZE_ON_STACK 260 261 ret 262SYM_FUNC_END(call_on_irq_stack) 263#endif /* CONFIG_IRQ_STACKS */ 264 265/* 266 * Integer register context switch 267 * The callee-saved registers must be saved and restored. 268 * 269 * a0: previous task_struct (must be preserved across the switch) 270 * a1: next task_struct 271 * 272 * The value of a0 and a1 must be preserved by this function, as that's how 273 * arguments are passed to schedule_tail. 274 */ 275SYM_FUNC_START(__switch_to) 276 /* Save context into prev->thread */ 277 li a4, TASK_THREAD_RA 278 add a3, a0, a4 279 add a4, a1, a4 280 REG_S ra, TASK_THREAD_RA_RA(a3) 281 REG_S sp, TASK_THREAD_SP_RA(a3) 282 REG_S s0, TASK_THREAD_S0_RA(a3) 283 REG_S s1, TASK_THREAD_S1_RA(a3) 284 REG_S s2, TASK_THREAD_S2_RA(a3) 285 REG_S s3, TASK_THREAD_S3_RA(a3) 286 REG_S s4, TASK_THREAD_S4_RA(a3) 287 REG_S s5, TASK_THREAD_S5_RA(a3) 288 REG_S s6, TASK_THREAD_S6_RA(a3) 289 REG_S s7, TASK_THREAD_S7_RA(a3) 290 REG_S s8, TASK_THREAD_S8_RA(a3) 291 REG_S s9, TASK_THREAD_S9_RA(a3) 292 REG_S s10, TASK_THREAD_S10_RA(a3) 293 REG_S s11, TASK_THREAD_S11_RA(a3) 294 /* Save the kernel shadow call stack pointer */ 295 scs_save_current 296 /* Restore context from next->thread */ 297 REG_L ra, TASK_THREAD_RA_RA(a4) 298 REG_L sp, TASK_THREAD_SP_RA(a4) 299 REG_L s0, TASK_THREAD_S0_RA(a4) 300 REG_L s1, TASK_THREAD_S1_RA(a4) 301 REG_L s2, TASK_THREAD_S2_RA(a4) 302 REG_L s3, TASK_THREAD_S3_RA(a4) 303 REG_L s4, TASK_THREAD_S4_RA(a4) 304 REG_L s5, TASK_THREAD_S5_RA(a4) 305 REG_L s6, TASK_THREAD_S6_RA(a4) 306 REG_L s7, TASK_THREAD_S7_RA(a4) 307 REG_L s8, TASK_THREAD_S8_RA(a4) 308 REG_L s9, TASK_THREAD_S9_RA(a4) 309 REG_L s10, TASK_THREAD_S10_RA(a4) 310 REG_L s11, TASK_THREAD_S11_RA(a4) 311 /* The offset of thread_info in task_struct is zero. */ 312 move tp, a1 313 /* Switch to the next shadow call stack */ 314 scs_load_current 315 ret 316SYM_FUNC_END(__switch_to) 317 318#ifndef CONFIG_MMU 319#define do_page_fault do_trap_unknown 320#endif 321 322 .section ".rodata" 323 .align LGREG 324 /* Exception vector table */ 325SYM_DATA_START_LOCAL(excp_vect_table) 326 RISCV_PTR do_trap_insn_misaligned 327 ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault) 328 RISCV_PTR do_trap_insn_illegal 329 RISCV_PTR do_trap_break 330 RISCV_PTR do_trap_load_misaligned 331 RISCV_PTR do_trap_load_fault 332 RISCV_PTR do_trap_store_misaligned 333 RISCV_PTR do_trap_store_fault 334 RISCV_PTR do_trap_ecall_u /* system call */ 335 RISCV_PTR do_trap_ecall_s 336 RISCV_PTR do_trap_unknown 337 RISCV_PTR do_trap_ecall_m 338 /* instruciton page fault */ 339 ALT_PAGE_FAULT(RISCV_PTR do_page_fault) 340 RISCV_PTR do_page_fault /* load page fault */ 341 RISCV_PTR do_trap_unknown 342 RISCV_PTR do_page_fault /* store page fault */ 343SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) 344 345#ifndef CONFIG_MMU 346SYM_DATA_START(__user_rt_sigreturn) 347 li a7, __NR_rt_sigreturn 348 ecall 349SYM_DATA_END(__user_rt_sigreturn) 350#endif 351