1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 #include <linux/gpio/driver.h> 6 #include <linux/interrupt.h> 7 #include <linux/irq.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/slab.h> 12 13 #define PCH_EDGE_FALLING 0 14 #define PCH_EDGE_RISING BIT(0) 15 #define PCH_LEVEL_L BIT(1) 16 #define PCH_LEVEL_H (BIT(0) | BIT(1)) 17 #define PCH_EDGE_BOTH BIT(2) 18 #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) 19 20 #define PCH_IRQ_BASE 24 21 22 struct pch_regs { 23 u32 ien; 24 u32 istatus; 25 u32 idisp; 26 u32 iclr; 27 u32 imask; 28 u32 imaskclr; 29 u32 po; 30 u32 pi; 31 u32 pm; 32 u32 im0; 33 u32 im1; 34 u32 reserved[3]; 35 u32 gpio_use_sel; 36 u32 reset; 37 }; 38 39 enum pch_type_t { 40 INTEL_EG20T_PCH, 41 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */ 42 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */ 43 }; 44 45 /* Specifies number of GPIO PINS */ 46 static int gpio_pins[] = { 47 [INTEL_EG20T_PCH] = 12, 48 [OKISEMI_ML7223m_IOH] = 8, 49 [OKISEMI_ML7223n_IOH] = 8, 50 }; 51 52 /** 53 * struct pch_gpio_reg_data - The register store data. 54 * @ien_reg: To store contents of IEN register. 55 * @imask_reg: To store contents of IMASK register. 56 * @po_reg: To store contents of PO register. 57 * @pm_reg: To store contents of PM register. 58 * @im0_reg: To store contents of IM0 register. 59 * @im1_reg: To store contents of IM1 register. 60 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register. 61 * (Only ML7223 Bus-n) 62 */ 63 struct pch_gpio_reg_data { 64 u32 ien_reg; 65 u32 imask_reg; 66 u32 po_reg; 67 u32 pm_reg; 68 u32 im0_reg; 69 u32 im1_reg; 70 u32 gpio_use_sel_reg; 71 }; 72 73 /** 74 * struct pch_gpio - GPIO private data structure. 75 * @base: PCI base address of Memory mapped I/O register. 76 * @reg: Memory mapped PCH GPIO register list. 77 * @dev: Pointer to device structure. 78 * @gpio: Data for GPIO infrastructure. 79 * @pch_gpio_reg: Memory mapped Register data is saved here 80 * when suspend. 81 * @lock: Used for register access protection 82 * @irq_base: Save base of IRQ number for interrupt 83 * @ioh: IOH ID 84 * @spinlock: Used for register access protection 85 */ 86 struct pch_gpio { 87 void __iomem *base; 88 struct pch_regs __iomem *reg; 89 struct device *dev; 90 struct gpio_chip gpio; 91 struct pch_gpio_reg_data pch_gpio_reg; 92 int irq_base; 93 enum pch_type_t ioh; 94 spinlock_t spinlock; 95 }; 96 97 static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) 98 { 99 u32 reg_val; 100 struct pch_gpio *chip = gpiochip_get_data(gpio); 101 unsigned long flags; 102 103 spin_lock_irqsave(&chip->spinlock, flags); 104 reg_val = ioread32(&chip->reg->po); 105 if (val) 106 reg_val |= (1 << nr); 107 else 108 reg_val &= ~(1 << nr); 109 110 iowrite32(reg_val, &chip->reg->po); 111 spin_unlock_irqrestore(&chip->spinlock, flags); 112 } 113 114 static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr) 115 { 116 struct pch_gpio *chip = gpiochip_get_data(gpio); 117 118 return (ioread32(&chip->reg->pi) >> nr) & 1; 119 } 120 121 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 122 int val) 123 { 124 struct pch_gpio *chip = gpiochip_get_data(gpio); 125 u32 pm; 126 u32 reg_val; 127 unsigned long flags; 128 129 spin_lock_irqsave(&chip->spinlock, flags); 130 131 reg_val = ioread32(&chip->reg->po); 132 if (val) 133 reg_val |= (1 << nr); 134 else 135 reg_val &= ~(1 << nr); 136 iowrite32(reg_val, &chip->reg->po); 137 138 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); 139 pm |= (1 << nr); 140 iowrite32(pm, &chip->reg->pm); 141 142 spin_unlock_irqrestore(&chip->spinlock, flags); 143 144 return 0; 145 } 146 147 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 148 { 149 struct pch_gpio *chip = gpiochip_get_data(gpio); 150 u32 pm; 151 unsigned long flags; 152 153 spin_lock_irqsave(&chip->spinlock, flags); 154 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); 155 pm &= ~(1 << nr); 156 iowrite32(pm, &chip->reg->pm); 157 spin_unlock_irqrestore(&chip->spinlock, flags); 158 159 return 0; 160 } 161 162 /* 163 * Save register configuration and disable interrupts. 164 */ 165 static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip) 166 { 167 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); 168 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); 169 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); 170 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); 171 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); 172 if (chip->ioh == INTEL_EG20T_PCH) 173 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); 174 if (chip->ioh == OKISEMI_ML7223n_IOH) 175 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel); 176 } 177 178 /* 179 * This function restores the register configuration of the GPIO device. 180 */ 181 static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip) 182 { 183 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); 184 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); 185 /* to store contents of PO register */ 186 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); 187 /* to store contents of PM register */ 188 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); 189 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); 190 if (chip->ioh == INTEL_EG20T_PCH) 191 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); 192 if (chip->ioh == OKISEMI_ML7223n_IOH) 193 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel); 194 } 195 196 static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset) 197 { 198 struct pch_gpio *chip = gpiochip_get_data(gpio); 199 return chip->irq_base + offset; 200 } 201 202 static void pch_gpio_setup(struct pch_gpio *chip) 203 { 204 struct gpio_chip *gpio = &chip->gpio; 205 206 gpio->label = dev_name(chip->dev); 207 gpio->parent = chip->dev; 208 gpio->owner = THIS_MODULE; 209 gpio->direction_input = pch_gpio_direction_input; 210 gpio->get = pch_gpio_get; 211 gpio->direction_output = pch_gpio_direction_output; 212 gpio->set = pch_gpio_set; 213 gpio->base = -1; 214 gpio->ngpio = gpio_pins[chip->ioh]; 215 gpio->can_sleep = false; 216 gpio->to_irq = pch_gpio_to_irq; 217 } 218 219 static int pch_irq_type(struct irq_data *d, unsigned int type) 220 { 221 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 222 struct pch_gpio *chip = gc->private; 223 u32 im, im_pos, val; 224 u32 __iomem *im_reg; 225 unsigned long flags; 226 int ch, irq = d->irq; 227 228 ch = irq - chip->irq_base; 229 if (irq <= chip->irq_base + 7) { 230 im_reg = &chip->reg->im0; 231 im_pos = ch; 232 } else { 233 im_reg = &chip->reg->im1; 234 im_pos = ch - 8; 235 } 236 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos); 237 238 spin_lock_irqsave(&chip->spinlock, flags); 239 240 switch (type) { 241 case IRQ_TYPE_EDGE_RISING: 242 val = PCH_EDGE_RISING; 243 break; 244 case IRQ_TYPE_EDGE_FALLING: 245 val = PCH_EDGE_FALLING; 246 break; 247 case IRQ_TYPE_EDGE_BOTH: 248 val = PCH_EDGE_BOTH; 249 break; 250 case IRQ_TYPE_LEVEL_HIGH: 251 val = PCH_LEVEL_H; 252 break; 253 case IRQ_TYPE_LEVEL_LOW: 254 val = PCH_LEVEL_L; 255 break; 256 default: 257 goto unlock; 258 } 259 260 /* Set interrupt mode */ 261 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4)); 262 iowrite32(im | (val << (im_pos * 4)), im_reg); 263 264 /* And the handler */ 265 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 266 irq_set_handler_locked(d, handle_level_irq); 267 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 268 irq_set_handler_locked(d, handle_edge_irq); 269 270 unlock: 271 spin_unlock_irqrestore(&chip->spinlock, flags); 272 return 0; 273 } 274 275 static void pch_irq_unmask(struct irq_data *d) 276 { 277 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 278 struct pch_gpio *chip = gc->private; 279 280 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr); 281 } 282 283 static void pch_irq_mask(struct irq_data *d) 284 { 285 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 286 struct pch_gpio *chip = gc->private; 287 288 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask); 289 } 290 291 static void pch_irq_ack(struct irq_data *d) 292 { 293 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 294 struct pch_gpio *chip = gc->private; 295 296 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr); 297 } 298 299 static irqreturn_t pch_gpio_handler(int irq, void *dev_id) 300 { 301 struct pch_gpio *chip = dev_id; 302 unsigned long reg_val = ioread32(&chip->reg->istatus); 303 int i, ret = IRQ_NONE; 304 305 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) { 306 dev_dbg(chip->dev, "[%d]:irq=%d status=0x%lx\n", i, irq, reg_val); 307 generic_handle_irq(chip->irq_base + i); 308 ret = IRQ_HANDLED; 309 } 310 return ret; 311 } 312 313 static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip, 314 unsigned int irq_start, 315 unsigned int num) 316 { 317 struct irq_chip_generic *gc; 318 struct irq_chip_type *ct; 319 int rv; 320 321 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start, 322 chip->base, handle_simple_irq); 323 if (!gc) 324 return -ENOMEM; 325 326 gc->private = chip; 327 ct = gc->chip_types; 328 329 ct->chip.irq_ack = pch_irq_ack; 330 ct->chip.irq_mask = pch_irq_mask; 331 ct->chip.irq_unmask = pch_irq_unmask; 332 ct->chip.irq_set_type = pch_irq_type; 333 334 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), 335 IRQ_GC_INIT_MASK_CACHE, 336 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 337 338 return rv; 339 } 340 341 static int pch_gpio_probe(struct pci_dev *pdev, 342 const struct pci_device_id *id) 343 { 344 s32 ret; 345 struct pch_gpio *chip; 346 int irq_base; 347 u32 msk; 348 349 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 350 if (chip == NULL) 351 return -ENOMEM; 352 353 chip->dev = &pdev->dev; 354 ret = pcim_enable_device(pdev); 355 if (ret) { 356 dev_err(&pdev->dev, "pci_enable_device FAILED"); 357 return ret; 358 } 359 360 ret = pcim_iomap_regions(pdev, 1 << 1, KBUILD_MODNAME); 361 if (ret) { 362 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret); 363 return ret; 364 } 365 366 chip->base = pcim_iomap_table(pdev)[1]; 367 368 if (pdev->device == 0x8803) 369 chip->ioh = INTEL_EG20T_PCH; 370 else if (pdev->device == 0x8014) 371 chip->ioh = OKISEMI_ML7223m_IOH; 372 else if (pdev->device == 0x8043) 373 chip->ioh = OKISEMI_ML7223n_IOH; 374 375 chip->reg = chip->base; 376 pci_set_drvdata(pdev, chip); 377 spin_lock_init(&chip->spinlock); 378 pch_gpio_setup(chip); 379 380 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip); 381 if (ret) { 382 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n"); 383 return ret; 384 } 385 386 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 387 gpio_pins[chip->ioh], NUMA_NO_NODE); 388 if (irq_base < 0) { 389 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n"); 390 chip->irq_base = -1; 391 return 0; 392 } 393 chip->irq_base = irq_base; 394 395 /* Mask all interrupts, but enable them */ 396 msk = (1 << gpio_pins[chip->ioh]) - 1; 397 iowrite32(msk, &chip->reg->imask); 398 iowrite32(msk, &chip->reg->ien); 399 400 ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler, 401 IRQF_SHARED, KBUILD_MODNAME, chip); 402 if (ret) { 403 dev_err(&pdev->dev, "request_irq failed\n"); 404 return ret; 405 } 406 407 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]); 408 } 409 410 static int __maybe_unused pch_gpio_suspend(struct device *dev) 411 { 412 struct pch_gpio *chip = dev_get_drvdata(dev); 413 unsigned long flags; 414 415 spin_lock_irqsave(&chip->spinlock, flags); 416 pch_gpio_save_reg_conf(chip); 417 spin_unlock_irqrestore(&chip->spinlock, flags); 418 419 return 0; 420 } 421 422 static int __maybe_unused pch_gpio_resume(struct device *dev) 423 { 424 struct pch_gpio *chip = dev_get_drvdata(dev); 425 unsigned long flags; 426 427 spin_lock_irqsave(&chip->spinlock, flags); 428 iowrite32(0x01, &chip->reg->reset); 429 iowrite32(0x00, &chip->reg->reset); 430 pch_gpio_restore_reg_conf(chip); 431 spin_unlock_irqrestore(&chip->spinlock, flags); 432 433 return 0; 434 } 435 436 static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume); 437 438 static const struct pci_device_id pch_gpio_pcidev_id[] = { 439 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) }, 440 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) }, 441 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) }, 442 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) }, 443 { 0, } 444 }; 445 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id); 446 447 static struct pci_driver pch_gpio_driver = { 448 .name = "pch_gpio", 449 .id_table = pch_gpio_pcidev_id, 450 .probe = pch_gpio_probe, 451 .driver = { 452 .pm = &pch_gpio_pm_ops, 453 }, 454 }; 455 456 module_pci_driver(pch_gpio_driver); 457 458 MODULE_DESCRIPTION("PCH GPIO PCI Driver"); 459 MODULE_LICENSE("GPL v2"); 460