1 /* 2 * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) 3 * 4 * This file is licensed under the terms of the GNU General Public 5 * License version 2. This program is licensed "as is" without any 6 * warranty of any kind, whether express or implied. 7 */ 8 9 #ifndef __DESIGNWARE_LOCAL_H 10 #define __DESIGNWARE_LOCAL_H 11 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/types.h> 15 #include <sound/dmaengine_pcm.h> 16 #include <sound/pcm.h> 17 #include <sound/designware_i2s.h> 18 19 /* common register for all channel */ 20 #define IER 0x000 21 #define IRER 0x004 22 #define ITER 0x008 23 #define CER 0x00C 24 #define CCR 0x010 25 #define RXFFR 0x014 26 #define TXFFR 0x018 27 28 /* Interrupt status register fields */ 29 #define ISR_TXFO BIT(5) 30 #define ISR_TXFE BIT(4) 31 #define ISR_RXFO BIT(1) 32 #define ISR_RXDA BIT(0) 33 34 /* I2STxRxRegisters for all channels */ 35 #define LRBR_LTHR(x) (0x40 * x + 0x020) 36 #define RRBR_RTHR(x) (0x40 * x + 0x024) 37 #define RER(x) (0x40 * x + 0x028) 38 #define TER(x) (0x40 * x + 0x02C) 39 #define RCR(x) (0x40 * x + 0x030) 40 #define TCR(x) (0x40 * x + 0x034) 41 #define ISR(x) (0x40 * x + 0x038) 42 #define IMR(x) (0x40 * x + 0x03C) 43 #define ROR(x) (0x40 * x + 0x040) 44 #define TOR(x) (0x40 * x + 0x044) 45 #define RFCR(x) (0x40 * x + 0x048) 46 #define TFCR(x) (0x40 * x + 0x04C) 47 #define RFF(x) (0x40 * x + 0x050) 48 #define TFF(x) (0x40 * x + 0x054) 49 50 /* I2SCOMPRegisters */ 51 #define I2S_COMP_PARAM_2 0x01F0 52 #define I2S_COMP_PARAM_1 0x01F4 53 #define I2S_COMP_VERSION 0x01F8 54 #define I2S_COMP_TYPE 0x01FC 55 56 #define I2S_RRXDMA 0x01C4 57 #define I2S_RTXDMA 0x01CC 58 #define I2S_DMACR 0x0200 59 #define I2S_DMAEN_RXBLOCK (1 << 16) 60 #define I2S_DMAEN_TXBLOCK (1 << 17) 61 62 /* 63 * Component parameter register fields - define the I2S block's 64 * configuration. 65 */ 66 #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25) 67 #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22) 68 #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19) 69 #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16) 70 #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9) 71 #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7) 72 #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6) 73 #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5) 74 #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4) 75 #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2) 76 #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0) 77 78 #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10) 79 #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7) 80 #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3) 81 #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0) 82 83 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */ 84 #define COMP_MAX_WORDSIZE (1 << 3) 85 #define COMP_MAX_DATA_WIDTH (1 << 2) 86 87 #define MAX_CHANNEL_NUM 8 88 #define MIN_CHANNEL_NUM 2 89 90 union dw_i2s_snd_dma_data { 91 struct i2s_dma_data pd; 92 struct snd_dmaengine_dai_dma_data dt; 93 }; 94 95 struct dw_i2s_dev { 96 void __iomem *i2s_base; 97 struct clk *clk; 98 struct reset_control *reset; 99 int active; 100 unsigned int capability; 101 unsigned int quirks; 102 unsigned int i2s_reg_comp1; 103 unsigned int i2s_reg_comp2; 104 struct device *dev; 105 u32 ccr; 106 u32 xfer_resolution; 107 u32 fifo_th; 108 109 /* data related to DMA transfers b/w i2s and DMAC */ 110 union dw_i2s_snd_dma_data play_dma_data; 111 union dw_i2s_snd_dma_data capture_dma_data; 112 struct i2s_clk_config_data config; 113 int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); 114 115 /* data related to PIO transfers */ 116 bool use_pio; 117 struct snd_pcm_substream __rcu *tx_substream; 118 struct snd_pcm_substream __rcu *rx_substream; 119 unsigned int (*tx_fn)(struct dw_i2s_dev *dev, 120 struct snd_pcm_runtime *runtime, unsigned int tx_ptr, 121 bool *period_elapsed); 122 unsigned int (*rx_fn)(struct dw_i2s_dev *dev, 123 struct snd_pcm_runtime *runtime, unsigned int rx_ptr, 124 bool *period_elapsed); 125 unsigned int tx_ptr; 126 unsigned int rx_ptr; 127 }; 128 129 #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM) 130 void dw_pcm_push_tx(struct dw_i2s_dev *dev); 131 void dw_pcm_pop_rx(struct dw_i2s_dev *dev); 132 int dw_pcm_register(struct platform_device *pdev); 133 #else 134 static inline void dw_pcm_push_tx(struct dw_i2s_dev *dev) { } 135 static inline void dw_pcm_pop_rx(struct dw_i2s_dev *dev) { } 136 static inline int dw_pcm_register(struct platform_device *pdev) 137 { 138 return -EINVAL; 139 } 140 #endif 141 142 #endif 143