xref: /linux/drivers/crypto/qce/common.h (revision f8e17c17b81070f38062dce79ca7f4541851dadd)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _COMMON_H_
7 #define _COMMON_H_
8 
9 #include <linux/crypto.h>
10 #include <linux/types.h>
11 #include <crypto/aes.h>
12 #include <crypto/hash.h>
13 #include <crypto/internal/skcipher.h>
14 
15 /* key size in bytes */
16 #define QCE_SHA_HMAC_KEY_SIZE		64
17 #define QCE_MAX_CIPHER_KEY_SIZE		AES_KEYSIZE_256
18 
19 /* IV length in bytes */
20 #define QCE_AES_IV_LENGTH		AES_BLOCK_SIZE
21 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
22 #define QCE_MAX_IV_SIZE			AES_BLOCK_SIZE
23 
24 /* maximum nonce bytes  */
25 #define QCE_MAX_NONCE			16
26 #define QCE_MAX_NONCE_WORDS		(QCE_MAX_NONCE / sizeof(u32))
27 
28 /* burst size alignment requirement */
29 #define QCE_MAX_ALIGN_SIZE		64
30 
31 /* cipher algorithms */
32 #define QCE_ALG_DES			BIT(0)
33 #define QCE_ALG_3DES			BIT(1)
34 #define QCE_ALG_AES			BIT(2)
35 
36 /* hash and hmac algorithms */
37 #define QCE_HASH_SHA1			BIT(3)
38 #define QCE_HASH_SHA256			BIT(4)
39 #define QCE_HASH_SHA1_HMAC		BIT(5)
40 #define QCE_HASH_SHA256_HMAC		BIT(6)
41 #define QCE_HASH_AES_CMAC		BIT(7)
42 
43 /* cipher modes */
44 #define QCE_MODE_CBC			BIT(8)
45 #define QCE_MODE_ECB			BIT(9)
46 #define QCE_MODE_CTR			BIT(10)
47 #define QCE_MODE_XTS			BIT(11)
48 #define QCE_MODE_CCM			BIT(12)
49 #define QCE_MODE_MASK			GENMASK(12, 8)
50 
51 /* cipher encryption/decryption operations */
52 #define QCE_ENCRYPT			BIT(13)
53 #define QCE_DECRYPT			BIT(14)
54 
55 #define IS_DES(flags)			(flags & QCE_ALG_DES)
56 #define IS_3DES(flags)			(flags & QCE_ALG_3DES)
57 #define IS_AES(flags)			(flags & QCE_ALG_AES)
58 
59 #define IS_SHA1(flags)			(flags & QCE_HASH_SHA1)
60 #define IS_SHA256(flags)		(flags & QCE_HASH_SHA256)
61 #define IS_SHA1_HMAC(flags)		(flags & QCE_HASH_SHA1_HMAC)
62 #define IS_SHA256_HMAC(flags)		(flags & QCE_HASH_SHA256_HMAC)
63 #define IS_CMAC(flags)			(flags & QCE_HASH_AES_CMAC)
64 #define IS_SHA(flags)			(IS_SHA1(flags) || IS_SHA256(flags))
65 #define IS_SHA_HMAC(flags)		\
66 		(IS_SHA1_HMAC(flags) || IS_SHA256_HMAC(flags))
67 
68 #define IS_CBC(mode)			(mode & QCE_MODE_CBC)
69 #define IS_ECB(mode)			(mode & QCE_MODE_ECB)
70 #define IS_CTR(mode)			(mode & QCE_MODE_CTR)
71 #define IS_XTS(mode)			(mode & QCE_MODE_XTS)
72 #define IS_CCM(mode)			(mode & QCE_MODE_CCM)
73 
74 #define IS_ENCRYPT(dir)			(dir & QCE_ENCRYPT)
75 #define IS_DECRYPT(dir)			(dir & QCE_DECRYPT)
76 
77 struct qce_alg_template {
78 	struct list_head entry;
79 	u32 crypto_alg_type;
80 	unsigned long alg_flags;
81 	const u32 *std_iv;
82 	union {
83 		struct skcipher_alg skcipher;
84 		struct ahash_alg ahash;
85 	} alg;
86 	struct qce_device *qce;
87 };
88 
89 void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len);
90 int qce_check_status(struct qce_device *qce, u32 *status);
91 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step);
92 int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
93 	      u32 offset);
94 
95 #endif /* _COMMON_H_ */
96