drm/amd/display: Refactor DCN4x and related code[why & how]Refactor existing code related to DCN4x for better code sharing withother modules.Reviewed-by: Charlene Liu <charlene.liu@amd.com>Sig
drm/amd/display: Refactor DCN4x and related code[why & how]Refactor existing code related to DCN4x for better code sharing withother modules.Reviewed-by: Charlene Liu <charlene.liu@amd.com>Signed-off-by: Swapnil Patel <Swapnil.Patel@amd.com>Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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drm/amd/display: Allow reuse of of DCN4x codeRemove the static qualifier to make it available for code sharingwith other components.Reviewed-by: Charlene Liu <charlene.liu@amd.com>Signed-off-by
drm/amd/display: Allow reuse of of DCN4x codeRemove the static qualifier to make it available for code sharingwith other components.Reviewed-by: Charlene Liu <charlene.liu@amd.com>Signed-off-by: Dmytro <dmytro.laktyushkin@amd.com>Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>Signed-off-by: Alex Hung <alex.hung@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: log destination of vertical interrupt[Why]Knowing the destination of OTG's vertical interrupt 2 is useful fordebugging, but it is not currently included in the OTG state readback
drm/amd/display: log destination of vertical interrupt[Why]Knowing the destination of OTG's vertical interrupt 2 is useful fordebugging, but it is not currently included in the OTG state readbacklogic[How]Read the OTG interrupt destination register to get the vertical interrupt2 destination on ASICs that have this register when reading back the OTGstate from hardwareReviewed-by: Sung Lee <sung.lee@amd.com>Reviewed-by: Aric Cyr <aric.cyr@amd.com>Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>Signed-off-by: Wayne Lin <wayne.lin@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add support to configure CRC window on specific CRC instance[Why]Have the need to specify the CRC window on specific CRC engine.dc_stream_configure_crc() today calculates CRC on
drm/amd/display: Add support to configure CRC window on specific CRC instance[Why]Have the need to specify the CRC window on specific CRC engine.dc_stream_configure_crc() today calculates CRC on crc engine 0 only and alwaysresets CRC engine at first.[How]Add index parameter to dc_stream_configure_crc() for selecting the desired crcengine. Additionally, add another parameter to specify whether to skip thedefault reset of crc engine.Reviewed-by: HaoPing Liu <haoping.liu@amd.com>Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: DML2.1 Post-Si Cleanup[Why]There are a few cleanup and refactoring tasks that need to be donewith the DML2.1 wrapper and DC interface to remove dependencies onlegacy structures
drm/amd/display: DML2.1 Post-Si Cleanup[Why]There are a few cleanup and refactoring tasks that need to be donewith the DML2.1 wrapper and DC interface to remove dependencies onlegacy structures and N-1 prototypes.[How]Implemented pipe_ctx->global_sync.Implemented new functions to use pipe_ctx->hubp_regs andpipe_ctx->global_sync:- hubp_setup2- hubp_setup_interdependent2- Several other new functions for DCN 4.01 to support newer structuresRemoved dml21_update_pipe_ctx_dchub_regsRemoved dml21_extract_legacy_watermark_setRemoved dml21_populate_pipe_ctx_dlg_paramRemoved outdated dcn references in DML2.1 wrapper.Reviewed-by: Austin Zheng <austin.zheng@amd.com>Reviewed-by: Dillon Varone <dillon.varone@amd.com>Signed-off-by: Rafal Ostrowski <rostrows@amd.com>Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Extend dc_stream_get_crc to support 2nd crc engine[Why & How]Since now we can set multiple crc windows for secure display, add a new inputparameter for dc_stream_get_crc to indic
drm/amd/display: Extend dc_stream_get_crc to support 2nd crc engine[Why & How]Since now we can set multiple crc windows for secure display, add a new inputparameter for dc_stream_get_crc to indicate to fetch crc from which crcengine.Reviewed-by: HaoPing Liu <haoping.liu@amd.com>Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>Signed-off-by: Roman Li <roman.li@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Wait for all pending cleared before full update[Description]Before every full update we must wait for all pending updates to becleared - this is particularly important for minima
drm/amd/display: Wait for all pending cleared before full update[Description]Before every full update we must wait for all pending updates to becleared - this is particularly important for minimal transitionsbecause if we don't wait for pending cleared, it will be as ifthere was no minimal transition at all. In OTG we must read 3 differentstatus registers for pending cleared, one specifically for OTG updates,one specifically for OPTC updates, and the last for surface relatedupdates.Reviewed-by: Dillon Varone <dillon.varone@amd.com>Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add 'pstate_keepout' kdoc entry in 'optc1_program_timing'Fixes the below with gcc W=1:Function parameter or struct member 'pstate_keepout' not described in 'optc1_program_timing'
drm/amd/display: Add 'pstate_keepout' kdoc entry in 'optc1_program_timing'Fixes the below with gcc W=1:Function parameter or struct member 'pstate_keepout' not described in 'optc1_program_timing'Cc: Tom Chung <chiahsuan.chung@amd.com>Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Cc: Roman Li <roman.li@amd.com>Cc: Alex Hung <alex.hung@amd.com>Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>Cc: Harry Wentland <harry.wentland@amd.com>Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add P-State Keepout to dcn401 Global Sync[WHY&HOW]OTG has new functionality to allow P-State relative to VStartup. Keepout regionfor this should be configured based on DML output
drm/amd/display: Add P-State Keepout to dcn401 Global Sync[WHY&HOW]OTG has new functionality to allow P-State relative to VStartup. Keepout regionfor this should be configured based on DML outputs same as other global syncparams.Reviewed-by: Alvin Lee <alvin.lee2@amd.com>Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>Signed-off-by: Dillon Varone <dillon.varone@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: fix corruption with high refresh rates on DCN 3.0This reverts commit bc87d666c05a13e6d4ae1ddce41fc43d2567b9a2 and theregister changes from commit 6d4279cb99ac4f51d10409501d29969f6
drm/amd/display: fix corruption with high refresh rates on DCN 3.0This reverts commit bc87d666c05a13e6d4ae1ddce41fc43d2567b9a2 and theregister changes from commit 6d4279cb99ac4f51d10409501d29969f687ac8dc.Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3412Cc: mikhail.v.gavrilov@gmail.comCc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>Cc: stable@vger.kernel.org # 6.10.x
drm/amd/display: Wait for double buffer update on ODM changes[WHAT & HOW]We must wait for ODM double buffer updates to completebefore exiting the pipe update sequence or we may reduceDISPCLK and
drm/amd/display: Wait for double buffer update on ODM changes[WHAT & HOW]We must wait for ODM double buffer updates to completebefore exiting the pipe update sequence or we may reduceDISPCLK and hit some transient underflow (pixel rate isreduced before the pipes have ODM enabled).Reviewed-by: Samson Tam <samson.tam@amd.com>Cc: Mario Limonciello <mario.limonciello@amd.com>Cc: Alex Deucher <alexander.deucher@amd.com>Cc: stable@vger.kernel.orgSigned-off-by: Alex Hung <alex.hung@amd.com>Signed-off-by: Alvin Lee <alvin.lee2@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix swapped dimension calculations[Why]The values calculated in optc1_get_otg_active_size are assigned to thewrong output parameters, vertical blank is being used for horizontal
drm/amd/display: Fix swapped dimension calculations[Why]The values calculated in optc1_get_otg_active_size are assigned to thewrong output parameters, vertical blank is being used for horizontal sizeand vice versa. This results in DPG test pattern looking wrong duringhardware init, as the DPG dimensions get assigned from this output, andpotentially other issues.Reviewed-by: Aric Cyr <aric.cyr@amd.com>Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: use even ODM slice width for two pixels per container[why]When optc uses two pixel per container, each ODM slice width must be aneven number.[how]If ODM slice width is odd num
drm/amd/display: use even ODM slice width for two pixels per container[why]When optc uses two pixel per container, each ODM slice width must be aneven number.[how]If ODM slice width is odd number increase it by 1.Reviewed-by: Dillon Varone <dillon.varone@amd.com>Acked-by: Wayne Lin <wayne.lin@amd.com>Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add misc DC changes for DCN401Add miscellaneous changes to enable DCN401 initSigned-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Acked-by: Rodrigo Siqueira <rodrigo.siquei
drm/amd/display: Add misc DC changes for DCN401Add miscellaneous changes to enable DCN401 initSigned-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add some DCN401 reg name to macro definitionsUpdate macros to cover DCN 4.0.1.Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Acked-by: Rodrigo Siqueira <rodrigo.sique
drm/amd/display: Add some DCN401 reg name to macro definitionsUpdate macros to cover DCN 4.0.1.Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add fallback configuration for set DRR in DCN10Set OTG/OPTC parameters to 0 if something goes wrong on DCN10.Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>Signed-off-by: Rodrig
drm/amd/display: Add fallback configuration for set DRR in DCN10Set OTG/OPTC parameters to 0 if something goes wrong on DCN10.Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add V_TOTAL_REGS to dcn10DCN10 OPTC is used by other DCNs, and in some cases it might be usefulto have V_TOTAL_REGS available. This commit add V_TOTAL_REGS as part ofthe TG field
drm/amd/display: Add V_TOTAL_REGS to dcn10DCN10 OPTC is used by other DCNs, and in some cases it might be usefulto have V_TOTAL_REGS available. This commit add V_TOTAL_REGS as part ofthe TG field.Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add extra logging for HUBP and OTG[Description]Add extra logging for DCSURF_FLIP_CNTL, DCHUBP_CNTL,OTG_MASTER_EN, and OTG_DOUBLE_BUFFER_CONTROL for moredebuggability for a syste
drm/amd/display: Add extra logging for HUBP and OTG[Description]Add extra logging for DCSURF_FLIP_CNTL, DCHUBP_CNTL,OTG_MASTER_EN, and OTG_DOUBLE_BUFFER_CONTROL for moredebuggability for a system crash.Reviewed-by: Samson Tam <samson.tam@amd.com>Acked-by: Roman Li <roman.li@amd.com>Signed-off-by: Alvin Lee <alvin.lee2@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Support long vblank feature[WHY]We want to support low hz case, but the originalvtotal/vtotal_min/vtotal_max can't support morethan 0x7FFF.[HOW]We use the 2 HW reg to contorl
drm/amd/display: Support long vblank feature[WHY]We want to support low hz case, but the originalvtotal/vtotal_min/vtotal_max can't support morethan 0x7FFF.[HOW]We use the 2 HW reg to contorl long vblank case.1. OTG_V_COUNT_STOP_CONTROL -> vcount_stop2. OTG_V_COUNT_STOP_CONTROL2 -> vcount_stop_timervcount_stop define from which line we stop using vcountand start using vcount2.vcount_stop_timer define how long we use vcount2.Ex:Vtotal = 7OTG_V_COUNT_STOP_CONTROL = 4OTG_V_COUNT_STOP_CONTROL2 = 5time : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11vcount : 0, 1, 2, 3, - - - - - 4, 5, 6vcount2 : 0, 1, 2, 3, 4,Reviewed-by: Jun Lei <jun.lei@amd.com>Acked-by: Alex Hung <alex.hung@amd.com>Signed-off-by: ChunTao Tso <chuntao.tso@amd.com>Signed-off-by: Robin Chen<robin.chen@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Implement wait_for_odm_update_pending_complete[WHY]Odm update is doubled buffered. We need to wait for ODM update to becompleted before optimizing bandwidth or programming new ud
drm/amd/display: Implement wait_for_odm_update_pending_complete[WHY]Odm update is doubled buffered. We need to wait for ODM update to becompleted before optimizing bandwidth or programming new udpates.[HOW]implement wait_for_odm_update_pending_complete function to wait for:1. odm configuration update is no longer pending in timing generator.2. no pending dpg pattern update for each active OPP.Cc: Mario Limonciello <mario.limonciello@amd.com>Cc: Alex Deucher <alexander.deucher@amd.com>Cc: stable@vger.kernel.orgReviewed-by: Alvin Lee <alvin.lee2@amd.com>Acked-by: Alex Hung <alex.hung@amd.com>Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Refactor OPTC into component folder[why]Move all optc files to uniquefolder optc.[how]creating optc repo in dc, and moved the dcnxx_optc.c and .h files intocorresponding new
drm/amd/display: Refactor OPTC into component folder[why]Move all optc files to uniquefolder optc.[how]creating optc repo in dc, and moved the dcnxx_optc.c and .h files intocorresponding new folders inside the optc and cleared the linkageerrors by adding relative paths in the Makefile.template.Reviewed-by: Martin Leung <martin.leung@amd.com>Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>Signed-off-by: Parandhaman K <parandhaman.k@amd.com>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>