1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 4 * Authors: 5 * Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/seq_file.h> 20 #include <linux/slab.h> 21 #include <linux/string_helpers.h> 22 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinmux.h> 27 28 #include "core.h" 29 30 /* PIO Block registers */ 31 /* PIO output */ 32 #define REG_PIO_POUT 0x00 33 /* Set bits of POUT */ 34 #define REG_PIO_SET_POUT 0x04 35 /* Clear bits of POUT */ 36 #define REG_PIO_CLR_POUT 0x08 37 /* PIO input */ 38 #define REG_PIO_PIN 0x10 39 /* PIO configuration */ 40 #define REG_PIO_PC(n) (0x20 + (n) * 0x10) 41 /* Set bits of PC[2:0] */ 42 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) 43 /* Clear bits of PC[2:0] */ 44 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) 45 /* PIO input comparison */ 46 #define REG_PIO_PCOMP 0x50 47 /* Set bits of PCOMP */ 48 #define REG_PIO_SET_PCOMP 0x54 49 /* Clear bits of PCOMP */ 50 #define REG_PIO_CLR_PCOMP 0x58 51 /* PIO input comparison mask */ 52 #define REG_PIO_PMASK 0x60 53 /* Set bits of PMASK */ 54 #define REG_PIO_SET_PMASK 0x64 55 /* Clear bits of PMASK */ 56 #define REG_PIO_CLR_PMASK 0x68 57 58 #define ST_GPIO_DIRECTION_BIDIR 0x1 59 #define ST_GPIO_DIRECTION_OUT 0x2 60 #define ST_GPIO_DIRECTION_IN 0x4 61 62 /* 63 * Packed style retime configuration. 64 * There are two registers cfg0 and cfg1 in this style for each bank. 65 * Each field in this register is 8 bit corresponding to 8 pins in the bank. 66 */ 67 #define RT_P_CFGS_PER_BANK 2 68 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) 69 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) 70 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) 71 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) 72 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) 73 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) 74 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) 75 76 /* 77 * Dedicated style retime Configuration register 78 * each register is dedicated per pin. 79 */ 80 #define RT_D_CFGS_PER_BANK 8 81 #define RT_D_CFG_CLK_SHIFT 0 82 #define RT_D_CFG_CLK_MASK (0x3 << 0) 83 #define RT_D_CFG_CLKNOTDATA_SHIFT 2 84 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2) 85 #define RT_D_CFG_DELAY_SHIFT 3 86 #define RT_D_CFG_DELAY_MASK (0xf << 3) 87 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 88 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) 89 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 90 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) 91 #define RT_D_CFG_INVERTCLK_SHIFT 9 92 #define RT_D_CFG_INVERTCLK_MASK BIT(9) 93 #define RT_D_CFG_RETIME_SHIFT 10 94 #define RT_D_CFG_RETIME_MASK BIT(10) 95 96 /* 97 * Pinconf is represented in an opaque unsigned long variable. 98 * Below is the bit allocation details for each possible configuration. 99 * All the bit fields can be encapsulated into four variables 100 * (direction, retime-type, retime-clk, retime-delay) 101 * 102 * +----------------+ 103 *[31:28]| reserved-3 | 104 * +----------------+------------- 105 *[27] | oe | | 106 * +----------------+ v 107 *[26] | pu | [Direction ] 108 * +----------------+ ^ 109 *[25] | od | | 110 * +----------------+------------- 111 *[24] | reserved-2 | 112 * +----------------+------------- 113 *[23] | retime | | 114 * +----------------+ | 115 *[22] | retime-invclk | | 116 * +----------------+ v 117 *[21] |retime-clknotdat| [Retime-type ] 118 * +----------------+ ^ 119 *[20] | retime-de | | 120 * +----------------+------------- 121 *[19:18]| retime-clk |------>[Retime-Clk ] 122 * +----------------+ 123 *[17:16]| reserved-1 | 124 * +----------------+ 125 *[15..0]| retime-delay |------>[Retime Delay] 126 * +----------------+ 127 */ 128 129 #define ST_PINCONF_UNPACK(conf, param)\ 130 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ 131 & ST_PINCONF_ ##param ##_MASK) 132 133 #define ST_PINCONF_PACK(conf, val, param) (conf |=\ 134 ((val & ST_PINCONF_ ##param ##_MASK) << \ 135 ST_PINCONF_ ##param ##_SHIFT)) 136 137 /* Output enable */ 138 #define ST_PINCONF_OE_MASK 0x1 139 #define ST_PINCONF_OE_SHIFT 27 140 #define ST_PINCONF_OE BIT(27) 141 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 142 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) 143 144 /* Pull Up */ 145 #define ST_PINCONF_PU_MASK 0x1 146 #define ST_PINCONF_PU_SHIFT 26 147 #define ST_PINCONF_PU BIT(26) 148 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) 149 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) 150 151 /* Open Drain */ 152 #define ST_PINCONF_OD_MASK 0x1 153 #define ST_PINCONF_OD_SHIFT 25 154 #define ST_PINCONF_OD BIT(25) 155 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) 156 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) 157 158 #define ST_PINCONF_RT_MASK 0x1 159 #define ST_PINCONF_RT_SHIFT 23 160 #define ST_PINCONF_RT BIT(23) 161 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) 162 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) 163 164 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1 165 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22 166 #define ST_PINCONF_RT_INVERTCLK BIT(22) 167 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ 168 ST_PINCONF_UNPACK(conf, RT_INVERTCLK) 169 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ 170 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) 171 172 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 173 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 174 #define ST_PINCONF_RT_CLKNOTDATA BIT(21) 175 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ 176 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) 177 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ 178 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) 179 180 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 181 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 182 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) 183 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ 184 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) 185 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ 186 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) 187 188 #define ST_PINCONF_RT_CLK_MASK 0x3 189 #define ST_PINCONF_RT_CLK_SHIFT 18 190 #define ST_PINCONF_RT_CLK BIT(18) 191 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) 192 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) 193 194 /* RETIME_DELAY in Pico Secs */ 195 #define ST_PINCONF_RT_DELAY_MASK 0xffff 196 #define ST_PINCONF_RT_DELAY_SHIFT 0 197 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) 198 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \ 199 ST_PINCONF_PACK(conf, val, RT_DELAY) 200 201 #define ST_GPIO_PINS_PER_BANK (8) 202 #define OF_GPIO_ARGS_MIN (4) 203 #define OF_RT_ARGS_MIN (2) 204 205 #define gpio_range_to_bank(chip) \ 206 container_of(chip, struct st_gpio_bank, range) 207 208 #define pc_to_bank(pc) \ 209 container_of(pc, struct st_gpio_bank, pc) 210 211 enum st_retime_style { 212 st_retime_style_none, 213 st_retime_style_packed, 214 st_retime_style_dedicated, 215 }; 216 217 struct st_retime_dedicated { 218 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; 219 }; 220 221 struct st_retime_packed { 222 struct regmap_field *clk1notclk0; 223 struct regmap_field *delay_0; 224 struct regmap_field *delay_1; 225 struct regmap_field *invertclk; 226 struct regmap_field *retime; 227 struct regmap_field *clknotdata; 228 struct regmap_field *double_edge; 229 }; 230 231 struct st_pio_control { 232 u32 rt_pin_mask; 233 struct regmap_field *alt, *oe, *pu, *od; 234 /* retiming */ 235 union { 236 struct st_retime_packed rt_p; 237 struct st_retime_dedicated rt_d; 238 } rt; 239 }; 240 241 struct st_pctl_data { 242 const enum st_retime_style rt_style; 243 const unsigned int *input_delays; 244 const int ninput_delays; 245 const unsigned int *output_delays; 246 const int noutput_delays; 247 /* register offset information */ 248 const int alt, oe, pu, od, rt; 249 }; 250 251 struct st_pinconf { 252 int pin; 253 const char *name; 254 unsigned long config; 255 int altfunc; 256 }; 257 258 struct st_pmx_func { 259 const char *name; 260 const char **groups; 261 unsigned ngroups; 262 }; 263 264 struct st_pctl_group { 265 const char *name; 266 unsigned int *pins; 267 unsigned npins; 268 struct st_pinconf *pin_conf; 269 }; 270 271 /* 272 * Edge triggers are not supported at hardware level, it is supported by 273 * software by exploiting the level trigger support in hardware. 274 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration 275 * of each gpio pin in a GPIO bank. 276 * 277 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of 278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. 279 * 280 * bit allocation per pin is: 281 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] 282 * -------------------------------------------------------- 283 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | 284 * -------------------------------------------------------- 285 * 286 * A pin can have one of following the values in its edge configuration field. 287 * 288 * ------- ---------------------------- 289 * [0-3] - Description 290 * ------- ---------------------------- 291 * 0000 - No edge IRQ. 292 * 0001 - Falling edge IRQ. 293 * 0010 - Rising edge IRQ. 294 * 0011 - Rising and Falling edge IRQ. 295 * ------- ---------------------------- 296 */ 297 298 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 299 #define ST_IRQ_EDGE_MASK 0xf 300 #define ST_IRQ_EDGE_FALLING BIT(0) 301 #define ST_IRQ_EDGE_RISING BIT(1) 302 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) 303 304 #define ST_IRQ_RISING_EDGE_CONF(pin) \ 305 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 306 307 #define ST_IRQ_FALLING_EDGE_CONF(pin) \ 308 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 309 310 #define ST_IRQ_BOTH_EDGE_CONF(pin) \ 311 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 312 313 #define ST_IRQ_EDGE_CONF(conf, pin) \ 314 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) 315 316 struct st_gpio_bank { 317 struct gpio_chip gpio_chip; 318 struct pinctrl_gpio_range range; 319 void __iomem *base; 320 struct st_pio_control pc; 321 unsigned long irq_edge_conf; 322 spinlock_t lock; 323 }; 324 325 struct st_pinctrl { 326 struct device *dev; 327 struct pinctrl_dev *pctl; 328 struct st_gpio_bank *banks; 329 int nbanks; 330 struct st_pmx_func *functions; 331 int nfunctions; 332 struct st_pctl_group *groups; 333 int ngroups; 334 struct regmap *regmap; 335 const struct st_pctl_data *data; 336 void __iomem *irqmux_base; 337 }; 338 339 /* SOC specific data */ 340 341 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250, 342 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 343 344 static const struct st_pctl_data stih407_data = { 345 .rt_style = st_retime_style_dedicated, 346 .input_delays = stih407_delays, 347 .ninput_delays = ARRAY_SIZE(stih407_delays), 348 .output_delays = stih407_delays, 349 .noutput_delays = ARRAY_SIZE(stih407_delays), 350 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 351 }; 352 353 static const struct st_pctl_data stih407_flashdata = { 354 .rt_style = st_retime_style_none, 355 .input_delays = stih407_delays, 356 .ninput_delays = ARRAY_SIZE(stih407_delays), 357 .output_delays = stih407_delays, 358 .noutput_delays = ARRAY_SIZE(stih407_delays), 359 .alt = 0, 360 .oe = -1, /* Not Available */ 361 .pu = -1, /* Not Available */ 362 .od = 60, 363 .rt = 100, 364 }; 365 366 static struct st_pio_control *st_get_pio_control( 367 struct pinctrl_dev *pctldev, int pin) 368 { 369 struct pinctrl_gpio_range *range = 370 pinctrl_find_gpio_range_from_pin(pctldev, pin); 371 struct st_gpio_bank *bank = gpio_range_to_bank(range); 372 373 return &bank->pc; 374 } 375 376 /* Low level functions.. */ 377 static inline int st_gpio_bank(int gpio) 378 { 379 return gpio/ST_GPIO_PINS_PER_BANK; 380 } 381 382 static inline int st_gpio_pin(int gpio) 383 { 384 return gpio%ST_GPIO_PINS_PER_BANK; 385 } 386 387 static void st_pinconf_set_config(struct st_pio_control *pc, 388 int pin, unsigned long config) 389 { 390 struct regmap_field *output_enable = pc->oe; 391 struct regmap_field *pull_up = pc->pu; 392 struct regmap_field *open_drain = pc->od; 393 unsigned int oe_value, pu_value, od_value; 394 unsigned long mask = BIT(pin); 395 396 if (output_enable) { 397 regmap_field_read(output_enable, &oe_value); 398 oe_value &= ~mask; 399 if (config & ST_PINCONF_OE) 400 oe_value |= mask; 401 regmap_field_write(output_enable, oe_value); 402 } 403 404 if (pull_up) { 405 regmap_field_read(pull_up, &pu_value); 406 pu_value &= ~mask; 407 if (config & ST_PINCONF_PU) 408 pu_value |= mask; 409 regmap_field_write(pull_up, pu_value); 410 } 411 412 if (open_drain) { 413 regmap_field_read(open_drain, &od_value); 414 od_value &= ~mask; 415 if (config & ST_PINCONF_OD) 416 od_value |= mask; 417 regmap_field_write(open_drain, od_value); 418 } 419 } 420 421 static void st_pctl_set_function(struct st_pio_control *pc, 422 int pin_id, int function) 423 { 424 struct regmap_field *alt = pc->alt; 425 unsigned int val; 426 int pin = st_gpio_pin(pin_id); 427 int offset = pin * 4; 428 429 if (!alt) 430 return; 431 432 regmap_field_read(alt, &val); 433 val &= ~(0xf << offset); 434 val |= function << offset; 435 regmap_field_write(alt, val); 436 } 437 438 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) 439 { 440 struct regmap_field *alt = pc->alt; 441 unsigned int val; 442 int offset = pin * 4; 443 444 if (!alt) 445 return 0; 446 447 regmap_field_read(alt, &val); 448 449 return (val >> offset) & 0xf; 450 } 451 452 static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 453 const struct st_pctl_data *data, unsigned long config) 454 { 455 const unsigned int *delay_times; 456 int num_delay_times, i, closest_index = -1; 457 unsigned int closest_divergence = UINT_MAX; 458 459 if (ST_PINCONF_UNPACK_OE(config)) { 460 delay_times = data->output_delays; 461 num_delay_times = data->noutput_delays; 462 } else { 463 delay_times = data->input_delays; 464 num_delay_times = data->ninput_delays; 465 } 466 467 for (i = 0; i < num_delay_times; i++) { 468 unsigned int divergence = abs(delay - delay_times[i]); 469 470 if (divergence == 0) 471 return i; 472 473 if (divergence < closest_divergence) { 474 closest_divergence = divergence; 475 closest_index = i; 476 } 477 } 478 479 pr_warn("Attempt to set delay %d, closest available %d\n", 480 delay, delay_times[closest_index]); 481 482 return closest_index; 483 } 484 485 static unsigned long st_pinconf_bit_to_delay(unsigned int index, 486 const struct st_pctl_data *data, unsigned long output) 487 { 488 const unsigned int *delay_times; 489 int num_delay_times; 490 491 if (output) { 492 delay_times = data->output_delays; 493 num_delay_times = data->noutput_delays; 494 } else { 495 delay_times = data->input_delays; 496 num_delay_times = data->ninput_delays; 497 } 498 499 if (index < num_delay_times) { 500 return delay_times[index]; 501 } else { 502 pr_warn("Delay not found in/out delay list\n"); 503 return 0; 504 } 505 } 506 507 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, 508 int enable, int pin) 509 { 510 unsigned int val = 0; 511 512 regmap_field_read(field, &val); 513 if (enable) 514 val |= BIT(pin); 515 else 516 val &= ~BIT(pin); 517 regmap_field_write(field, val); 518 } 519 520 static void st_pinconf_set_retime_packed(struct st_pinctrl *info, 521 struct st_pio_control *pc, unsigned long config, int pin) 522 { 523 const struct st_pctl_data *data = info->data; 524 struct st_retime_packed *rt_p = &pc->rt.rt_p; 525 unsigned int delay; 526 527 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, 528 ST_PINCONF_UNPACK_RT_CLK(config), pin); 529 530 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, 531 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); 532 533 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, 534 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); 535 536 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, 537 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); 538 539 st_regmap_field_bit_set_clear_pin(rt_p->retime, 540 ST_PINCONF_UNPACK_RT(config), pin); 541 542 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), 543 data, config); 544 /* 2 bit delay, lsb */ 545 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); 546 /* 2 bit delay, msb */ 547 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); 548 } 549 550 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, 551 struct st_pio_control *pc, unsigned long config, int pin) 552 { 553 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; 554 int clk = ST_PINCONF_UNPACK_RT_CLK(config); 555 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); 556 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); 557 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); 558 int retime = ST_PINCONF_UNPACK_RT(config); 559 560 unsigned long delay = st_pinconf_delay_to_bit( 561 ST_PINCONF_UNPACK_RT_DELAY(config), 562 info->data, config); 563 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 564 565 unsigned long retime_config = 566 ((clk) << RT_D_CFG_CLK_SHIFT) | 567 ((delay) << RT_D_CFG_DELAY_SHIFT) | 568 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | 569 ((retime) << RT_D_CFG_RETIME_SHIFT) | 570 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | 571 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | 572 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); 573 574 regmap_field_write(rt_d->rt[pin], retime_config); 575 } 576 577 static void st_pinconf_get_direction(struct st_pio_control *pc, 578 int pin, unsigned long *config) 579 { 580 unsigned int oe_value, pu_value, od_value; 581 582 if (pc->oe) { 583 regmap_field_read(pc->oe, &oe_value); 584 if (oe_value & BIT(pin)) 585 ST_PINCONF_PACK_OE(*config); 586 } 587 588 if (pc->pu) { 589 regmap_field_read(pc->pu, &pu_value); 590 if (pu_value & BIT(pin)) 591 ST_PINCONF_PACK_PU(*config); 592 } 593 594 if (pc->od) { 595 regmap_field_read(pc->od, &od_value); 596 if (od_value & BIT(pin)) 597 ST_PINCONF_PACK_OD(*config); 598 } 599 } 600 601 static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 602 struct st_pio_control *pc, int pin, unsigned long *config) 603 { 604 const struct st_pctl_data *data = info->data; 605 struct st_retime_packed *rt_p = &pc->rt.rt_p; 606 unsigned int delay_bits, delay, delay0, delay1, val; 607 int output = ST_PINCONF_UNPACK_OE(*config); 608 609 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) 610 ST_PINCONF_PACK_RT(*config); 611 612 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) 613 ST_PINCONF_PACK_RT_CLK(*config, 1); 614 615 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) 616 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 617 618 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) 619 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 620 621 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) 622 ST_PINCONF_PACK_RT_INVERTCLK(*config); 623 624 regmap_field_read(rt_p->delay_0, &delay0); 625 regmap_field_read(rt_p->delay_1, &delay1); 626 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | 627 (((delay0 & BIT(pin)) ? 1 : 0)); 628 delay = st_pinconf_bit_to_delay(delay_bits, data, output); 629 ST_PINCONF_PACK_RT_DELAY(*config, delay); 630 631 return 0; 632 } 633 634 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, 635 struct st_pio_control *pc, int pin, unsigned long *config) 636 { 637 unsigned int value; 638 unsigned long delay_bits, delay, rt_clk; 639 int output = ST_PINCONF_UNPACK_OE(*config); 640 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 641 642 regmap_field_read(rt_d->rt[pin], &value); 643 644 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; 645 ST_PINCONF_PACK_RT_CLK(*config, rt_clk); 646 647 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; 648 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); 649 ST_PINCONF_PACK_RT_DELAY(*config, delay); 650 651 if (value & RT_D_CFG_CLKNOTDATA_MASK) 652 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 653 654 if (value & RT_D_CFG_DOUBLE_EDGE_MASK) 655 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 656 657 if (value & RT_D_CFG_INVERTCLK_MASK) 658 ST_PINCONF_PACK_RT_INVERTCLK(*config); 659 660 if (value & RT_D_CFG_RETIME_MASK) 661 ST_PINCONF_PACK_RT(*config); 662 663 return 0; 664 } 665 666 /* GPIO related functions */ 667 668 static inline void __st_gpio_set(struct st_gpio_bank *bank, 669 unsigned offset, int value) 670 { 671 if (value) 672 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); 673 else 674 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); 675 } 676 677 static void st_gpio_direction(struct st_gpio_bank *bank, 678 unsigned int gpio, unsigned int direction) 679 { 680 int offset = st_gpio_pin(gpio); 681 int i = 0; 682 /** 683 * There are three configuration registers (PIOn_PC0, PIOn_PC1 684 * and PIOn_PC2) for each port. These are used to configure the 685 * PIO port pins. Each pin can be configured as an input, output, 686 * bidirectional, or alternative function pin. Three bits, one bit 687 * from each of the three registers, configure the corresponding bit of 688 * the port. Valid bit settings is: 689 * 690 * PC2 PC1 PC0 Direction. 691 * 0 0 0 [Input Weak pull-up] 692 * 0 0 or 1 1 [Bidirection] 693 * 0 1 0 [Output] 694 * 1 0 0 [Input] 695 * 696 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits 697 * individually. 698 */ 699 for (i = 0; i <= 2; i++) { 700 if (direction & BIT(i)) 701 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); 702 else 703 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); 704 } 705 } 706 707 static int st_gpio_get(struct gpio_chip *chip, unsigned offset) 708 { 709 struct st_gpio_bank *bank = gpiochip_get_data(chip); 710 711 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); 712 } 713 714 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 715 { 716 struct st_gpio_bank *bank = gpiochip_get_data(chip); 717 __st_gpio_set(bank, offset, value); 718 } 719 720 static int st_gpio_direction_output(struct gpio_chip *chip, 721 unsigned offset, int value) 722 { 723 struct st_gpio_bank *bank = gpiochip_get_data(chip); 724 725 __st_gpio_set(bank, offset, value); 726 pinctrl_gpio_direction_output(chip, offset); 727 728 return 0; 729 } 730 731 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 732 { 733 struct st_gpio_bank *bank = gpiochip_get_data(chip); 734 struct st_pio_control pc = bank->pc; 735 unsigned long config; 736 unsigned int direction = 0; 737 unsigned int function; 738 unsigned int value; 739 int i = 0; 740 741 /* Alternate function direction is handled by Pinctrl */ 742 function = st_pctl_get_pin_function(&pc, offset); 743 if (function) { 744 st_pinconf_get_direction(&pc, offset, &config); 745 if (ST_PINCONF_UNPACK_OE(config)) 746 return GPIO_LINE_DIRECTION_OUT; 747 748 return GPIO_LINE_DIRECTION_IN; 749 } 750 751 /* 752 * GPIO direction is handled differently 753 * - See st_gpio_direction() above for an explanation 754 */ 755 for (i = 0; i <= 2; i++) { 756 value = readl(bank->base + REG_PIO_PC(i)); 757 direction |= ((value >> offset) & 0x1) << i; 758 } 759 760 if (direction == ST_GPIO_DIRECTION_IN) 761 return GPIO_LINE_DIRECTION_IN; 762 763 return GPIO_LINE_DIRECTION_OUT; 764 } 765 766 /* Pinctrl Groups */ 767 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) 768 { 769 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 770 771 return info->ngroups; 772 } 773 774 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, 775 unsigned selector) 776 { 777 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 778 779 return info->groups[selector].name; 780 } 781 782 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, 783 unsigned selector, const unsigned **pins, unsigned *npins) 784 { 785 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 786 787 if (selector >= info->ngroups) 788 return -EINVAL; 789 790 *pins = info->groups[selector].pins; 791 *npins = info->groups[selector].npins; 792 793 return 0; 794 } 795 796 static inline const struct st_pctl_group *st_pctl_find_group_by_name( 797 const struct st_pinctrl *info, const char *name) 798 { 799 int i; 800 801 for (i = 0; i < info->ngroups; i++) { 802 if (!strcmp(info->groups[i].name, name)) 803 return &info->groups[i]; 804 } 805 806 return NULL; 807 } 808 809 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 810 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) 811 { 812 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 813 const struct st_pctl_group *grp; 814 struct device *dev = info->dev; 815 struct pinctrl_map *new_map; 816 struct device_node *parent; 817 int map_num, i; 818 819 grp = st_pctl_find_group_by_name(info, np->name); 820 if (!grp) { 821 dev_err(dev, "unable to find group for node %pOFn\n", np); 822 return -EINVAL; 823 } 824 825 map_num = grp->npins + 1; 826 new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL); 827 if (!new_map) 828 return -ENOMEM; 829 830 parent = of_get_parent(np); 831 if (!parent) { 832 devm_kfree(dev, new_map); 833 return -EINVAL; 834 } 835 836 *map = new_map; 837 *num_maps = map_num; 838 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 839 new_map[0].data.mux.function = parent->name; 840 new_map[0].data.mux.group = np->name; 841 of_node_put(parent); 842 843 /* create config map per pin */ 844 new_map++; 845 for (i = 0; i < grp->npins; i++) { 846 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 847 new_map[i].data.configs.group_or_pin = 848 pin_get_name(pctldev, grp->pins[i]); 849 new_map[i].data.configs.configs = &grp->pin_conf[i].config; 850 new_map[i].data.configs.num_configs = 1; 851 } 852 dev_info(dev, "maps: function %s group %s num %d\n", 853 (*map)->data.mux.function, grp->name, map_num); 854 855 return 0; 856 } 857 858 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, 859 struct pinctrl_map *map, unsigned num_maps) 860 { 861 } 862 863 static const struct pinctrl_ops st_pctlops = { 864 .get_groups_count = st_pctl_get_groups_count, 865 .get_group_pins = st_pctl_get_group_pins, 866 .get_group_name = st_pctl_get_group_name, 867 .dt_node_to_map = st_pctl_dt_node_to_map, 868 .dt_free_map = st_pctl_dt_free_map, 869 }; 870 871 /* Pinmux */ 872 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 873 { 874 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 875 876 return info->nfunctions; 877 } 878 879 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, 880 unsigned selector) 881 { 882 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 883 884 return info->functions[selector].name; 885 } 886 887 static int st_pmx_get_groups(struct pinctrl_dev *pctldev, 888 unsigned selector, const char * const **grps, unsigned * const ngrps) 889 { 890 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 891 *grps = info->functions[selector].groups; 892 *ngrps = info->functions[selector].ngroups; 893 894 return 0; 895 } 896 897 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 898 unsigned group) 899 { 900 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 901 struct st_pinconf *conf = info->groups[group].pin_conf; 902 struct st_pio_control *pc; 903 int i; 904 905 for (i = 0; i < info->groups[group].npins; i++) { 906 pc = st_get_pio_control(pctldev, conf[i].pin); 907 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); 908 } 909 910 return 0; 911 } 912 913 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 914 struct pinctrl_gpio_range *range, unsigned gpio, 915 bool input) 916 { 917 struct st_gpio_bank *bank = gpio_range_to_bank(range); 918 /* 919 * When a PIO bank is used in its primary function mode (altfunc = 0) 920 * Output Enable (OE), Open Drain(OD), and Pull Up (PU) 921 * for the primary PIO functions are driven by the related PIO block 922 */ 923 st_pctl_set_function(&bank->pc, gpio, 0); 924 st_gpio_direction(bank, gpio, input ? 925 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); 926 927 return 0; 928 } 929 930 static const struct pinmux_ops st_pmxops = { 931 .get_functions_count = st_pmx_get_funcs_count, 932 .get_function_name = st_pmx_get_fname, 933 .get_function_groups = st_pmx_get_groups, 934 .set_mux = st_pmx_set_mux, 935 .gpio_set_direction = st_pmx_set_gpio_direction, 936 .strict = true, 937 }; 938 939 /* Pinconf */ 940 static void st_pinconf_get_retime(struct st_pinctrl *info, 941 struct st_pio_control *pc, int pin, unsigned long *config) 942 { 943 if (info->data->rt_style == st_retime_style_packed) 944 st_pinconf_get_retime_packed(info, pc, pin, config); 945 else if (info->data->rt_style == st_retime_style_dedicated) 946 if ((BIT(pin) & pc->rt_pin_mask)) 947 st_pinconf_get_retime_dedicated(info, pc, 948 pin, config); 949 } 950 951 static void st_pinconf_set_retime(struct st_pinctrl *info, 952 struct st_pio_control *pc, int pin, unsigned long config) 953 { 954 if (info->data->rt_style == st_retime_style_packed) 955 st_pinconf_set_retime_packed(info, pc, config, pin); 956 else if (info->data->rt_style == st_retime_style_dedicated) 957 if ((BIT(pin) & pc->rt_pin_mask)) 958 st_pinconf_set_retime_dedicated(info, pc, 959 config, pin); 960 } 961 962 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, 963 unsigned long *configs, unsigned num_configs) 964 { 965 int pin = st_gpio_pin(pin_id); 966 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 967 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 968 int i; 969 970 for (i = 0; i < num_configs; i++) { 971 st_pinconf_set_config(pc, pin, configs[i]); 972 st_pinconf_set_retime(info, pc, pin, configs[i]); 973 } /* for each config */ 974 975 return 0; 976 } 977 978 static int st_pinconf_get(struct pinctrl_dev *pctldev, 979 unsigned pin_id, unsigned long *config) 980 { 981 int pin = st_gpio_pin(pin_id); 982 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 983 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 984 985 *config = 0; 986 st_pinconf_get_direction(pc, pin, config); 987 st_pinconf_get_retime(info, pc, pin, config); 988 989 return 0; 990 } 991 992 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 993 struct seq_file *s, unsigned pin_id) 994 { 995 struct st_pio_control *pc; 996 unsigned long config; 997 unsigned int function; 998 int offset = st_gpio_pin(pin_id); 999 char f[16]; 1000 int oe; 1001 1002 mutex_unlock(&pctldev->mutex); 1003 pc = st_get_pio_control(pctldev, pin_id); 1004 st_pinconf_get(pctldev, pin_id, &config); 1005 mutex_lock(&pctldev->mutex); 1006 1007 function = st_pctl_get_pin_function(pc, offset); 1008 if (function) 1009 snprintf(f, 10, "Alt Fn %u", function); 1010 else 1011 snprintf(f, 5, "GPIO"); 1012 1013 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); 1014 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" 1015 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1016 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1017 (oe == GPIO_LINE_DIRECTION_OUT), 1018 ST_PINCONF_UNPACK_PU(config), 1019 ST_PINCONF_UNPACK_OD(config), 1020 f, 1021 ST_PINCONF_UNPACK_RT(config), 1022 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1023 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1024 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), 1025 ST_PINCONF_UNPACK_RT_CLK(config), 1026 ST_PINCONF_UNPACK_RT_DELAY(config)); 1027 } 1028 1029 static const struct pinconf_ops st_confops = { 1030 .pin_config_get = st_pinconf_get, 1031 .pin_config_set = st_pinconf_set, 1032 .pin_config_dbg_show = st_pinconf_dbg_show, 1033 }; 1034 1035 static void st_pctl_dt_child_count(struct st_pinctrl *info, 1036 struct device_node *np) 1037 { 1038 struct device_node *child; 1039 for_each_child_of_node(np, child) { 1040 if (of_property_read_bool(child, "gpio-controller")) { 1041 info->nbanks++; 1042 } else { 1043 info->nfunctions++; 1044 info->ngroups += of_get_child_count(child); 1045 } 1046 } 1047 } 1048 1049 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, 1050 int bank, struct st_pio_control *pc) 1051 { 1052 struct device *dev = info->dev; 1053 struct regmap *rm = info->regmap; 1054 const struct st_pctl_data *data = info->data; 1055 /* 2 registers per bank */ 1056 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; 1057 struct st_retime_packed *rt_p = &pc->rt.rt_p; 1058 /* cfg0 */ 1059 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); 1060 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); 1061 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); 1062 /* cfg1 */ 1063 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); 1064 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); 1065 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); 1066 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); 1067 1068 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); 1069 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); 1070 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); 1071 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); 1072 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); 1073 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); 1074 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); 1075 1076 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || 1077 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || 1078 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || 1079 IS_ERR(rt_p->double_edge)) 1080 return -EINVAL; 1081 1082 return 0; 1083 } 1084 1085 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, 1086 int bank, struct st_pio_control *pc) 1087 { 1088 struct device *dev = info->dev; 1089 struct regmap *rm = info->regmap; 1090 const struct st_pctl_data *data = info->data; 1091 /* 8 registers per bank */ 1092 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; 1093 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 1094 unsigned int j; 1095 u32 pin_mask = pc->rt_pin_mask; 1096 1097 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { 1098 if (BIT(j) & pin_mask) { 1099 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); 1100 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); 1101 if (IS_ERR(rt_d->rt[j])) 1102 return -EINVAL; 1103 reg_offset += 4; 1104 } 1105 } 1106 return 0; 1107 } 1108 1109 static int st_pctl_dt_setup_retime(struct st_pinctrl *info, 1110 int bank, struct st_pio_control *pc) 1111 { 1112 const struct st_pctl_data *data = info->data; 1113 if (data->rt_style == st_retime_style_packed) 1114 return st_pctl_dt_setup_retime_packed(info, bank, pc); 1115 else if (data->rt_style == st_retime_style_dedicated) 1116 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); 1117 1118 return -EINVAL; 1119 } 1120 1121 1122 static struct regmap_field *st_pc_get_value(struct device *dev, 1123 struct regmap *regmap, int bank, 1124 int data, int lsb, int msb) 1125 { 1126 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); 1127 1128 if (data < 0) 1129 return NULL; 1130 1131 return devm_regmap_field_alloc(dev, regmap, reg); 1132 } 1133 1134 static void st_parse_syscfgs(struct st_pinctrl *info, int bank, 1135 struct device_node *np) 1136 { 1137 const struct st_pctl_data *data = info->data; 1138 /** 1139 * For a given shared register like OE/PU/OD, there are 8 bits per bank 1140 * 0:7 belongs to bank0, 8:15 belongs to bank1 ... 1141 * So each register is shared across 4 banks. 1142 */ 1143 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1144 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1145 struct st_pio_control *pc = &info->banks[bank].pc; 1146 struct device *dev = info->dev; 1147 struct regmap *regmap = info->regmap; 1148 1149 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); 1150 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); 1151 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); 1152 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); 1153 1154 /* retime avaiable for all pins by default */ 1155 pc->rt_pin_mask = 0xff; 1156 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1157 st_pctl_dt_setup_retime(info, bank, pc); 1158 1159 return; 1160 } 1161 1162 static int st_pctl_dt_calculate_pin(struct st_pinctrl *info, 1163 phandle bank, unsigned int offset) 1164 { 1165 struct device_node *np; 1166 struct gpio_chip *chip; 1167 int retval = -EINVAL; 1168 int i; 1169 1170 np = of_find_node_by_phandle(bank); 1171 if (!np) 1172 return -EINVAL; 1173 1174 for (i = 0; i < info->nbanks; i++) { 1175 chip = &info->banks[i].gpio_chip; 1176 if (chip->fwnode == of_fwnode_handle(np)) { 1177 if (offset < chip->ngpio) 1178 retval = chip->base + offset; 1179 break; 1180 } 1181 } 1182 1183 of_node_put(np); 1184 return retval; 1185 } 1186 1187 /* 1188 * Each pin is represented in of the below forms. 1189 * <bank offset mux direction rt_type rt_delay rt_clk> 1190 */ 1191 static int st_pctl_dt_parse_groups(struct device_node *np, 1192 struct st_pctl_group *grp, struct st_pinctrl *info, int idx) 1193 { 1194 /* bank pad direction val altfunction */ 1195 const __be32 *list; 1196 struct property *pp; 1197 struct device *dev = info->dev; 1198 struct st_pinconf *conf; 1199 struct device_node *pins; 1200 phandle bank; 1201 unsigned int offset; 1202 int i = 0, npins = 0, nr_props, ret = 0; 1203 1204 pins = of_get_child_by_name(np, "st,pins"); 1205 if (!pins) 1206 return -ENODATA; 1207 1208 for_each_property_of_node(pins, pp) { 1209 /* Skip those we do not want to proceed */ 1210 if (!strcmp(pp->name, "name")) 1211 continue; 1212 1213 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { 1214 npins++; 1215 } else { 1216 pr_warn("Invalid st,pins in %pOFn node\n", np); 1217 ret = -EINVAL; 1218 goto out_put_node; 1219 } 1220 } 1221 1222 grp->npins = npins; 1223 grp->name = np->name; 1224 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); 1225 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); 1226 1227 if (!grp->pins || !grp->pin_conf) { 1228 ret = -ENOMEM; 1229 goto out_put_node; 1230 } 1231 1232 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1233 for_each_property_of_node(pins, pp) { 1234 if (!strcmp(pp->name, "name")) 1235 continue; 1236 nr_props = pp->length/sizeof(u32); 1237 list = pp->value; 1238 conf = &grp->pin_conf[i]; 1239 1240 /* bank & offset */ 1241 bank = be32_to_cpup(list++); 1242 offset = be32_to_cpup(list++); 1243 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset); 1244 conf->name = pp->name; 1245 grp->pins[i] = conf->pin; 1246 /* mux */ 1247 conf->altfunc = be32_to_cpup(list++); 1248 conf->config = 0; 1249 /* direction */ 1250 conf->config |= be32_to_cpup(list++); 1251 /* rt_type rt_delay rt_clk */ 1252 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { 1253 /* rt_type */ 1254 conf->config |= be32_to_cpup(list++); 1255 /* rt_delay */ 1256 conf->config |= be32_to_cpup(list++); 1257 /* rt_clk */ 1258 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) 1259 conf->config |= be32_to_cpup(list++); 1260 } 1261 i++; 1262 } 1263 1264 out_put_node: 1265 of_node_put(pins); 1266 1267 return ret; 1268 } 1269 1270 static int st_pctl_parse_functions(struct device_node *np, 1271 struct st_pinctrl *info, u32 index, int *grp_index) 1272 { 1273 struct device *dev = info->dev; 1274 struct device_node *child; 1275 struct st_pmx_func *func; 1276 struct st_pctl_group *grp; 1277 int ret, i; 1278 1279 func = &info->functions[index]; 1280 func->name = np->name; 1281 func->ngroups = of_get_child_count(np); 1282 if (func->ngroups == 0) 1283 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); 1284 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 1285 if (!func->groups) 1286 return -ENOMEM; 1287 1288 i = 0; 1289 for_each_child_of_node(np, child) { 1290 func->groups[i] = child->name; 1291 grp = &info->groups[*grp_index]; 1292 *grp_index += 1; 1293 ret = st_pctl_dt_parse_groups(child, grp, info, i++); 1294 if (ret) { 1295 of_node_put(child); 1296 return ret; 1297 } 1298 } 1299 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); 1300 1301 return 0; 1302 } 1303 1304 static void st_gpio_irq_mask(struct irq_data *d) 1305 { 1306 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1307 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1308 1309 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK); 1310 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 1311 } 1312 1313 static void st_gpio_irq_unmask(struct irq_data *d) 1314 { 1315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1316 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1317 1318 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 1319 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK); 1320 } 1321 1322 static int st_gpio_irq_request_resources(struct irq_data *d) 1323 { 1324 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1325 1326 pinctrl_gpio_direction_input(gc, d->hwirq); 1327 1328 return gpiochip_reqres_irq(gc, d->hwirq); 1329 } 1330 1331 static void st_gpio_irq_release_resources(struct irq_data *d) 1332 { 1333 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1334 1335 gpiochip_relres_irq(gc, d->hwirq); 1336 } 1337 1338 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1339 { 1340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1341 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1342 unsigned long flags; 1343 int comp, pin = d->hwirq; 1344 u32 val; 1345 u32 pin_edge_conf = 0; 1346 1347 switch (type) { 1348 case IRQ_TYPE_LEVEL_HIGH: 1349 comp = 0; 1350 break; 1351 case IRQ_TYPE_EDGE_FALLING: 1352 comp = 0; 1353 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); 1354 break; 1355 case IRQ_TYPE_LEVEL_LOW: 1356 comp = 1; 1357 break; 1358 case IRQ_TYPE_EDGE_RISING: 1359 comp = 1; 1360 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); 1361 break; 1362 case IRQ_TYPE_EDGE_BOTH: 1363 comp = st_gpio_get(&bank->gpio_chip, pin); 1364 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); 1365 break; 1366 default: 1367 return -EINVAL; 1368 } 1369 1370 spin_lock_irqsave(&bank->lock, flags); 1371 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( 1372 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); 1373 bank->irq_edge_conf |= pin_edge_conf; 1374 spin_unlock_irqrestore(&bank->lock, flags); 1375 1376 val = readl(bank->base + REG_PIO_PCOMP); 1377 val &= ~BIT(pin); 1378 val |= (comp << pin); 1379 writel(val, bank->base + REG_PIO_PCOMP); 1380 1381 return 0; 1382 } 1383 1384 /* 1385 * As edge triggers are not supported at hardware level, it is supported by 1386 * software by exploiting the level trigger support in hardware. 1387 * 1388 * Steps for detection raising edge interrupt in software. 1389 * 1390 * Step 1: CONFIGURE pin to detect level LOW interrupts. 1391 * 1392 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, 1393 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. 1394 * IGNORE calling the actual interrupt handler for the pin at this stage. 1395 * 1396 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler 1397 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then 1398 * DISPATCH the interrupt to the interrupt handler of the pin. 1399 * 1400 * step-1 ________ __________ 1401 * | | step - 3 1402 * | | 1403 * step -2 |_____| 1404 * 1405 * falling edge is also detected int the same way. 1406 * 1407 */ 1408 static void __gpio_irq_handler(struct st_gpio_bank *bank) 1409 { 1410 unsigned long port_in, port_mask, port_comp, active_irqs; 1411 unsigned long bank_edge_mask, flags; 1412 int n, val, ecfg; 1413 1414 spin_lock_irqsave(&bank->lock, flags); 1415 bank_edge_mask = bank->irq_edge_conf; 1416 spin_unlock_irqrestore(&bank->lock, flags); 1417 1418 for (;;) { 1419 port_in = readl(bank->base + REG_PIO_PIN); 1420 port_comp = readl(bank->base + REG_PIO_PCOMP); 1421 port_mask = readl(bank->base + REG_PIO_PMASK); 1422 1423 active_irqs = (port_in ^ port_comp) & port_mask; 1424 1425 if (active_irqs == 0) 1426 break; 1427 1428 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { 1429 /* check if we are detecting fake edges ... */ 1430 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); 1431 1432 if (ecfg) { 1433 /* edge detection. */ 1434 val = st_gpio_get(&bank->gpio_chip, n); 1435 1436 writel(BIT(n), 1437 val ? bank->base + REG_PIO_SET_PCOMP : 1438 bank->base + REG_PIO_CLR_PCOMP); 1439 1440 if (ecfg != ST_IRQ_EDGE_BOTH && 1441 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) 1442 continue; 1443 } 1444 1445 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); 1446 } 1447 } 1448 } 1449 1450 static void st_gpio_irq_handler(struct irq_desc *desc) 1451 { 1452 /* interrupt dedicated per bank */ 1453 struct irq_chip *chip = irq_desc_get_chip(desc); 1454 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1455 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1456 1457 chained_irq_enter(chip, desc); 1458 __gpio_irq_handler(bank); 1459 chained_irq_exit(chip, desc); 1460 } 1461 1462 static void st_gpio_irqmux_handler(struct irq_desc *desc) 1463 { 1464 struct irq_chip *chip = irq_desc_get_chip(desc); 1465 struct st_pinctrl *info = irq_desc_get_handler_data(desc); 1466 unsigned long status; 1467 int n; 1468 1469 chained_irq_enter(chip, desc); 1470 1471 status = readl(info->irqmux_base); 1472 1473 for_each_set_bit(n, &status, info->nbanks) 1474 __gpio_irq_handler(&info->banks[n]); 1475 1476 chained_irq_exit(chip, desc); 1477 } 1478 1479 static const struct gpio_chip st_gpio_template = { 1480 .request = gpiochip_generic_request, 1481 .free = gpiochip_generic_free, 1482 .get = st_gpio_get, 1483 .set = st_gpio_set, 1484 .direction_input = pinctrl_gpio_direction_input, 1485 .direction_output = st_gpio_direction_output, 1486 .get_direction = st_gpio_get_direction, 1487 .ngpio = ST_GPIO_PINS_PER_BANK, 1488 }; 1489 1490 static const struct irq_chip st_gpio_irqchip = { 1491 .name = "GPIO", 1492 .irq_request_resources = st_gpio_irq_request_resources, 1493 .irq_release_resources = st_gpio_irq_release_resources, 1494 .irq_disable = st_gpio_irq_mask, 1495 .irq_mask = st_gpio_irq_mask, 1496 .irq_unmask = st_gpio_irq_unmask, 1497 .irq_set_type = st_gpio_irq_set_type, 1498 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 1499 }; 1500 1501 static int st_gpiolib_register_bank(struct st_pinctrl *info, 1502 int bank_nr, struct device_node *np) 1503 { 1504 struct st_gpio_bank *bank = &info->banks[bank_nr]; 1505 struct pinctrl_gpio_range *range = &bank->range; 1506 struct device *dev = info->dev; 1507 int bank_num = of_alias_get_id(np, "gpio"); 1508 struct resource res, irq_res; 1509 int err; 1510 1511 if (of_address_to_resource(np, 0, &res)) 1512 return -ENODEV; 1513 1514 bank->base = devm_ioremap_resource(dev, &res); 1515 if (IS_ERR(bank->base)) 1516 return PTR_ERR(bank->base); 1517 1518 bank->gpio_chip = st_gpio_template; 1519 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1520 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1521 bank->gpio_chip.fwnode = of_fwnode_handle(np); 1522 bank->gpio_chip.parent = dev; 1523 spin_lock_init(&bank->lock); 1524 1525 of_property_read_string(np, "st,bank-name", &range->name); 1526 bank->gpio_chip.label = range->name; 1527 1528 range->id = bank_num; 1529 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; 1530 range->npins = bank->gpio_chip.ngpio; 1531 range->gc = &bank->gpio_chip; 1532 1533 /** 1534 * GPIO bank can have one of the two possible types of 1535 * interrupt-wirings. 1536 * 1537 * First type is via irqmux, single interrupt is used by multiple 1538 * gpio banks. This reduces number of overall interrupts numbers 1539 * required. All these banks belong to a single pincontroller. 1540 * _________ 1541 * | |----> [gpio-bank (n) ] 1542 * | |----> [gpio-bank (n + 1)] 1543 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] 1544 * | |----> [gpio-bank (... )] 1545 * |_________|----> [gpio-bank (n + 7)] 1546 * 1547 * Second type has a dedicated interrupt per each gpio bank. 1548 * 1549 * [irqN]----> [gpio-bank (n)] 1550 */ 1551 1552 if (of_irq_to_resource(np, 0, &irq_res) > 0) { 1553 struct gpio_irq_chip *girq; 1554 int gpio_irq = irq_res.start; 1555 1556 /* This is not a valid IRQ */ 1557 if (gpio_irq <= 0) { 1558 dev_err(dev, "invalid IRQ for %pOF bank\n", np); 1559 goto skip_irq; 1560 } 1561 /* We need to have a mux as well */ 1562 if (!info->irqmux_base) { 1563 dev_err(dev, "no irqmux for %pOF bank\n", np); 1564 goto skip_irq; 1565 } 1566 1567 girq = &bank->gpio_chip.irq; 1568 gpio_irq_chip_set_chip(girq, &st_gpio_irqchip); 1569 girq->parent_handler = st_gpio_irq_handler; 1570 girq->num_parents = 1; 1571 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 1572 GFP_KERNEL); 1573 if (!girq->parents) 1574 return -ENOMEM; 1575 girq->parents[0] = gpio_irq; 1576 girq->default_type = IRQ_TYPE_NONE; 1577 girq->handler = handle_simple_irq; 1578 } 1579 1580 skip_irq: 1581 err = gpiochip_add_data(&bank->gpio_chip, bank); 1582 if (err) 1583 return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num); 1584 dev_info(dev, "%s bank added.\n", range->name); 1585 1586 return 0; 1587 } 1588 1589 static const struct of_device_id st_pctl_of_match[] = { 1590 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data}, 1591 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data}, 1592 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data}, 1593 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, 1594 { /* sentinel */ } 1595 }; 1596 1597 static int st_pctl_probe_dt(struct platform_device *pdev, 1598 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) 1599 { 1600 struct device *dev = &pdev->dev; 1601 int ret = 0; 1602 int i = 0, j = 0, k = 0, bank; 1603 struct pinctrl_pin_desc *pdesc; 1604 struct device_node *np = dev->of_node; 1605 struct device_node *child; 1606 int grp_index = 0; 1607 int irq = 0; 1608 1609 st_pctl_dt_child_count(info, np); 1610 if (!info->nbanks) 1611 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); 1612 1613 dev_info(dev, "nbanks = %d\n", info->nbanks); 1614 dev_info(dev, "nfunctions = %d\n", info->nfunctions); 1615 dev_info(dev, "ngroups = %d\n", info->ngroups); 1616 1617 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 1618 1619 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 1620 1621 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1622 1623 if (!info->functions || !info->groups || !info->banks) 1624 return -ENOMEM; 1625 1626 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1627 if (IS_ERR(info->regmap)) 1628 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); 1629 info->data = of_match_node(st_pctl_of_match, np)->data; 1630 1631 irq = platform_get_irq(pdev, 0); 1632 1633 if (irq > 0) { 1634 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); 1635 if (IS_ERR(info->irqmux_base)) 1636 return PTR_ERR(info->irqmux_base); 1637 1638 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, 1639 info); 1640 } 1641 1642 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1643 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1644 if (!pdesc) 1645 return -ENOMEM; 1646 1647 pctl_desc->pins = pdesc; 1648 1649 bank = 0; 1650 for_each_child_of_node(np, child) { 1651 if (of_property_read_bool(child, "gpio-controller")) { 1652 const char *bank_name = NULL; 1653 char **pin_names; 1654 1655 ret = st_gpiolib_register_bank(info, bank, child); 1656 if (ret) { 1657 of_node_put(child); 1658 return ret; 1659 } 1660 1661 k = info->banks[bank].range.pin_base; 1662 bank_name = info->banks[bank].range.name; 1663 1664 pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK); 1665 if (IS_ERR(pin_names)) { 1666 of_node_put(child); 1667 return PTR_ERR(pin_names); 1668 } 1669 1670 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { 1671 pdesc->number = k; 1672 pdesc->name = pin_names[j]; 1673 pdesc++; 1674 } 1675 st_parse_syscfgs(info, bank, child); 1676 bank++; 1677 } else { 1678 ret = st_pctl_parse_functions(child, info, 1679 i++, &grp_index); 1680 if (ret) { 1681 dev_err(dev, "No functions found.\n"); 1682 of_node_put(child); 1683 return ret; 1684 } 1685 } 1686 } 1687 1688 return 0; 1689 } 1690 1691 static int st_pctl_probe(struct platform_device *pdev) 1692 { 1693 struct device *dev = &pdev->dev; 1694 struct st_pinctrl *info; 1695 struct pinctrl_desc *pctl_desc; 1696 int ret, i; 1697 1698 if (!dev->of_node) { 1699 dev_err(dev, "device node not found.\n"); 1700 return -EINVAL; 1701 } 1702 1703 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); 1704 if (!pctl_desc) 1705 return -ENOMEM; 1706 1707 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1708 if (!info) 1709 return -ENOMEM; 1710 1711 info->dev = dev; 1712 platform_set_drvdata(pdev, info); 1713 ret = st_pctl_probe_dt(pdev, pctl_desc, info); 1714 if (ret) 1715 return ret; 1716 1717 pctl_desc->owner = THIS_MODULE; 1718 pctl_desc->pctlops = &st_pctlops; 1719 pctl_desc->pmxops = &st_pmxops; 1720 pctl_desc->confops = &st_confops; 1721 pctl_desc->name = dev_name(dev); 1722 1723 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); 1724 if (IS_ERR(info->pctl)) 1725 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); 1726 1727 for (i = 0; i < info->nbanks; i++) 1728 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); 1729 1730 return 0; 1731 } 1732 1733 static struct platform_driver st_pctl_driver = { 1734 .driver = { 1735 .name = "st-pinctrl", 1736 .of_match_table = st_pctl_of_match, 1737 }, 1738 .probe = st_pctl_probe, 1739 }; 1740 1741 static int __init st_pctl_init(void) 1742 { 1743 return platform_driver_register(&st_pctl_driver); 1744 } 1745 arch_initcall(st_pctl_init); 1746