1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef KFD_PRIV_H_INCLUDED 25 #define KFD_PRIV_H_INCLUDED 26 27 #include <linux/hashtable.h> 28 #include <linux/mmu_notifier.h> 29 #include <linux/memremap.h> 30 #include <linux/mutex.h> 31 #include <linux/types.h> 32 #include <linux/atomic.h> 33 #include <linux/workqueue.h> 34 #include <linux/spinlock.h> 35 #include <linux/kfd_ioctl.h> 36 #include <linux/idr.h> 37 #include <linux/kfifo.h> 38 #include <linux/seq_file.h> 39 #include <linux/kref.h> 40 #include <linux/sysfs.h> 41 #include <linux/device_cgroup.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_device.h> 45 #include <drm/drm_ioctl.h> 46 #include <kgd_kfd_interface.h> 47 #include <linux/swap.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu.h" 51 52 #define KFD_MAX_RING_ENTRY_SIZE 8 53 54 #define KFD_SYSFS_FILE_MODE 0444 55 56 /* GPU ID hash width in bits */ 57 #define KFD_GPU_ID_HASH_WIDTH 16 58 59 /* Use upper bits of mmap offset to store KFD driver specific information. 60 * BITS[63:62] - Encode MMAP type 61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to 62 * BITS[45:0] - MMAP offset value 63 * 64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these 65 * defines are w.r.t to PAGE_SIZE 66 */ 67 #define KFD_MMAP_TYPE_SHIFT 62 68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT) 69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) 70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT) 71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT) 72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT) 73 74 #define KFD_MMAP_GPU_ID_SHIFT 46 75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \ 76 << KFD_MMAP_GPU_ID_SHIFT) 77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\ 78 & KFD_MMAP_GPU_ID_MASK) 79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \ 80 >> KFD_MMAP_GPU_ID_SHIFT) 81 82 /* 83 * When working with cp scheduler we should assign the HIQ manually or via 84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot 85 * definitions for Kaveri. In Kaveri only the first ME queues participates 86 * in the cp scheduling taking that in mind we set the HIQ slot in the 87 * second ME. 88 */ 89 #define KFD_CIK_HIQ_PIPE 4 90 #define KFD_CIK_HIQ_QUEUE 0 91 92 /* Macro for allocating structures */ 93 #define kfd_alloc_struct(ptr_to_struct) \ 94 ((typeof(ptr_to_struct)) kzalloc(sizeof(*ptr_to_struct), GFP_KERNEL)) 95 96 #define KFD_MAX_NUM_OF_PROCESSES 512 97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 98 99 /* 100 * Size of the per-process TBA+TMA buffer: 2 pages 101 * 102 * The first page is the TBA used for the CWSR ISA code. The second 103 * page is used as TMA for user-mode trap handler setup in daisy-chain mode. 104 */ 105 #define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2) 106 #define KFD_CWSR_TMA_OFFSET PAGE_SIZE 107 108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ 109 (KFD_MAX_NUM_OF_PROCESSES * \ 110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 111 112 #define KFD_KERNEL_QUEUE_SIZE 2048 113 114 #define KFD_UNMAP_LATENCY_MS (4000) 115 116 #define KFD_MAX_SDMA_QUEUES 128 117 118 /* 119 * 512 = 0x200 120 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the 121 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA. 122 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC 123 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in 124 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE. 125 */ 126 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512 127 128 /** 129 * enum kfd_ioctl_flags - KFD ioctl flags 130 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how 131 * userspace can use a given ioctl. 132 */ 133 enum kfd_ioctl_flags { 134 /* 135 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE: 136 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially 137 * perform privileged operations and load arbitrary data into MQDs and 138 * eventually HQD registers when the queue is mapped by HWS. In order to 139 * prevent this we should perform additional security checks. 140 * 141 * This is equivalent to callers with the CHECKPOINT_RESTORE capability. 142 * 143 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE, 144 * we also allow ioctls with SYS_ADMIN capability. 145 */ 146 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), 147 }; 148 /* 149 * Kernel module parameter to specify maximum number of supported queues per 150 * device 151 */ 152 extern int max_num_of_queues_per_device; 153 154 155 /* Kernel module parameter to specify the scheduling policy */ 156 extern int sched_policy; 157 158 /* 159 * Kernel module parameter to specify the maximum process 160 * number per HW scheduler 161 */ 162 extern int hws_max_conc_proc; 163 164 extern int cwsr_enable; 165 166 /* 167 * Kernel module parameter to specify whether to send sigterm to HSA process on 168 * unhandled exception 169 */ 170 extern int send_sigterm; 171 172 /* 173 * This kernel module is used to simulate large bar machine on non-large bar 174 * enabled machines. 175 */ 176 extern int debug_largebar; 177 178 /* Set sh_mem_config.retry_disable on GFX v9 */ 179 extern int amdgpu_noretry; 180 181 /* Halt if HWS hang is detected */ 182 extern int halt_if_hws_hang; 183 184 /* Whether MEC FW support GWS barriers */ 185 extern bool hws_gws_support; 186 187 /* Queue preemption timeout in ms */ 188 extern int queue_preemption_timeout_ms; 189 190 /* 191 * Don't evict process queues on vm fault 192 */ 193 extern int amdgpu_no_queue_eviction_on_vm_fault; 194 195 /* Enable eviction debug messages */ 196 extern bool debug_evictions; 197 198 extern struct mutex kfd_processes_mutex; 199 200 enum cache_policy { 201 cache_policy_coherent, 202 cache_policy_noncoherent 203 }; 204 205 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0)) 206 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1))) 207 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\ 208 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ 209 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3))) 210 211 struct kfd_node; 212 213 struct kfd_event_interrupt_class { 214 bool (*interrupt_isr)(struct kfd_node *dev, 215 const uint32_t *ih_ring_entry, uint32_t *patched_ihre, 216 bool *patched_flag); 217 void (*interrupt_wq)(struct kfd_node *dev, 218 const uint32_t *ih_ring_entry); 219 }; 220 221 struct kfd_device_info { 222 uint32_t gfx_target_version; 223 const struct kfd_event_interrupt_class *event_interrupt_class; 224 unsigned int max_pasid_bits; 225 unsigned int max_no_of_hqd; 226 unsigned int doorbell_size; 227 size_t ih_ring_entry_size; 228 uint8_t num_of_watch_points; 229 uint16_t mqd_size_aligned; 230 bool supports_cwsr; 231 bool needs_pci_atomics; 232 uint32_t no_atomic_fw_version; 233 unsigned int num_sdma_queues_per_engine; 234 unsigned int num_reserved_sdma_queues_per_engine; 235 DECLARE_BITMAP(reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 236 }; 237 238 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev); 239 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev); 240 241 struct kfd_mem_obj { 242 uint32_t range_start; 243 uint32_t range_end; 244 uint64_t gpu_addr; 245 uint32_t *cpu_ptr; 246 void *gtt_mem; 247 }; 248 249 struct kfd_vmid_info { 250 uint32_t first_vmid_kfd; 251 uint32_t last_vmid_kfd; 252 uint32_t vmid_num_kfd; 253 }; 254 255 #define MAX_KFD_NODES 8 256 257 struct kfd_dev; 258 259 struct kfd_node { 260 unsigned int node_id; 261 struct amdgpu_device *adev; /* Duplicated here along with keeping 262 * a copy in kfd_dev to save a hop 263 */ 264 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with 265 * keeping a copy in kfd_dev to 266 * save a hop 267 */ 268 struct kfd_vmid_info vm_info; 269 unsigned int id; /* topology stub index */ 270 uint32_t xcc_mask; /* Instance mask of XCCs present */ 271 struct amdgpu_xcp *xcp; 272 273 /* Interrupts */ 274 struct kfifo ih_fifo; 275 struct workqueue_struct *ih_wq; 276 struct work_struct interrupt_work; 277 spinlock_t interrupt_lock; 278 279 /* 280 * Interrupts of interest to KFD are copied 281 * from the HW ring into a SW ring. 282 */ 283 bool interrupts_active; 284 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */ 285 286 /* QCM Device instance */ 287 struct device_queue_manager *dqm; 288 289 /* Global GWS resource shared between processes */ 290 void *gws; 291 bool gws_debug_workaround; 292 293 /* Clients watching SMI events */ 294 struct list_head smi_clients; 295 spinlock_t smi_lock; 296 uint32_t reset_seq_num; 297 298 /* SRAM ECC flag */ 299 atomic_t sram_ecc_flag; 300 301 /*spm process id */ 302 unsigned int spm_pasid; 303 304 /* Maximum process number mapped to HW scheduler */ 305 unsigned int max_proc_per_quantum; 306 307 unsigned int compute_vmid_bitmap; 308 309 struct kfd_local_mem_info local_mem_info; 310 311 struct kfd_dev *kfd; 312 }; 313 314 struct kfd_dev { 315 struct amdgpu_device *adev; 316 317 struct kfd_device_info device_info; 318 319 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells 320 * page used by kernel queue 321 */ 322 323 struct kgd2kfd_shared_resources shared_resources; 324 325 const struct kfd2kgd_calls *kfd2kgd; 326 struct mutex doorbell_mutex; 327 328 void *gtt_mem; 329 uint64_t gtt_start_gpu_addr; 330 void *gtt_start_cpu_ptr; 331 void *gtt_sa_bitmap; 332 struct mutex gtt_sa_lock; 333 unsigned int gtt_sa_chunk_size; 334 unsigned int gtt_sa_num_of_chunks; 335 336 bool init_complete; 337 338 /* Firmware versions */ 339 uint16_t mec_fw_version; 340 uint16_t mec2_fw_version; 341 uint16_t sdma_fw_version; 342 343 /* CWSR */ 344 bool cwsr_enabled; 345 const void *cwsr_isa; 346 unsigned int cwsr_isa_size; 347 348 /* xGMI */ 349 uint64_t hive_id; 350 351 bool pci_atomic_requested; 352 353 /* Compute Profile ref. count */ 354 atomic_t compute_profile; 355 356 struct ida doorbell_ida; 357 unsigned int max_doorbell_slices; 358 359 int noretry; 360 361 struct kfd_node *nodes[MAX_KFD_NODES]; 362 unsigned int num_nodes; 363 364 /* Track per device allocated watch points */ 365 uint32_t alloc_watch_ids; 366 spinlock_t watch_points_lock; 367 368 /* Kernel doorbells for KFD device */ 369 struct amdgpu_bo *doorbells; 370 371 /* bitmap for dynamic doorbell allocation from doorbell object */ 372 unsigned long *doorbell_bitmap; 373 }; 374 375 enum kfd_mempool { 376 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, 377 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, 378 KFD_MEMPOOL_FRAMEBUFFER = 3, 379 }; 380 381 /* Character device interface */ 382 int kfd_chardev_init(void); 383 void kfd_chardev_exit(void); 384 385 /** 386 * enum kfd_unmap_queues_filter - Enum for queue filters. 387 * 388 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the 389 * running queues list. 390 * 391 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues 392 * in the run list. 393 * 394 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to 395 * specific process. 396 * 397 */ 398 enum kfd_unmap_queues_filter { 399 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1, 400 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2, 401 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3 402 }; 403 404 /** 405 * enum kfd_queue_type - Enum for various queue types. 406 * 407 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type. 408 * 409 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type. 410 * 411 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type. 412 * 413 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type. 414 * 415 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface. 416 */ 417 enum kfd_queue_type { 418 KFD_QUEUE_TYPE_COMPUTE, 419 KFD_QUEUE_TYPE_SDMA, 420 KFD_QUEUE_TYPE_HIQ, 421 KFD_QUEUE_TYPE_DIQ, 422 KFD_QUEUE_TYPE_SDMA_XGMI 423 }; 424 425 enum kfd_queue_format { 426 KFD_QUEUE_FORMAT_PM4, 427 KFD_QUEUE_FORMAT_AQL 428 }; 429 430 enum KFD_QUEUE_PRIORITY { 431 KFD_QUEUE_PRIORITY_MINIMUM = 0, 432 KFD_QUEUE_PRIORITY_MAXIMUM = 15 433 }; 434 435 /** 436 * struct queue_properties 437 * 438 * @type: The queue type. 439 * 440 * @queue_id: Queue identifier. 441 * 442 * @queue_address: Queue ring buffer address. 443 * 444 * @queue_size: Queue ring buffer size. 445 * 446 * @priority: Defines the queue priority relative to other queues in the 447 * process. 448 * This is just an indication and HW scheduling may override the priority as 449 * necessary while keeping the relative prioritization. 450 * the priority granularity is from 0 to f which f is the highest priority. 451 * currently all queues are initialized with the highest priority. 452 * 453 * @queue_percent: This field is partially implemented and currently a zero in 454 * this field defines that the queue is non active. 455 * 456 * @read_ptr: User space address which points to the number of dwords the 457 * cp read from the ring buffer. This field updates automatically by the H/W. 458 * 459 * @write_ptr: Defines the number of dwords written to the ring buffer. 460 * 461 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring 462 * buffer. This field should be similar to write_ptr and the user should 463 * update this field after updating the write_ptr. 464 * 465 * @doorbell_off: The doorbell offset in the doorbell pci-bar. 466 * 467 * @is_interop: Defines if this is a interop queue. Interop queue means that 468 * the queue can access both graphics and compute resources. 469 * 470 * @is_evicted: Defines if the queue is evicted. Only active queues 471 * are evicted, rendering them inactive. 472 * 473 * @is_active: Defines if the queue is active or not. @is_active and 474 * @is_evicted are protected by the DQM lock. 475 * 476 * @is_gws: Defines if the queue has been updated to be GWS-capable or not. 477 * @is_gws should be protected by the DQM lock, since changing it can yield the 478 * possibility of updating DQM state on number of GWS queues. 479 * 480 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid 481 * of the queue. 482 * 483 * This structure represents the queue properties for each queue no matter if 484 * it's user mode or kernel mode queue. 485 * 486 */ 487 488 struct queue_properties { 489 enum kfd_queue_type type; 490 enum kfd_queue_format format; 491 unsigned int queue_id; 492 uint64_t queue_address; 493 uint64_t queue_size; 494 uint32_t priority; 495 uint32_t queue_percent; 496 uint32_t *read_ptr; 497 uint32_t *write_ptr; 498 void __iomem *doorbell_ptr; 499 uint32_t doorbell_off; 500 bool is_interop; 501 bool is_evicted; 502 bool is_suspended; 503 bool is_being_destroyed; 504 bool is_active; 505 bool is_gws; 506 uint32_t pm4_target_xcc; 507 bool is_dbg_wa; 508 bool is_user_cu_masked; 509 /* Not relevant for user mode queues in cp scheduling */ 510 unsigned int vmid; 511 /* Relevant only for sdma queues*/ 512 uint32_t sdma_engine_id; 513 uint32_t sdma_queue_id; 514 uint32_t sdma_vm_addr; 515 /* Relevant only for VI */ 516 uint64_t eop_ring_buffer_address; 517 uint32_t eop_ring_buffer_size; 518 uint64_t ctx_save_restore_area_address; 519 uint32_t ctx_save_restore_area_size; 520 uint32_t ctl_stack_size; 521 uint64_t tba_addr; 522 uint64_t tma_addr; 523 uint64_t exception_status; 524 }; 525 526 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \ 527 (q).queue_address != 0 && \ 528 (q).queue_percent > 0 && \ 529 !(q).is_evicted && \ 530 !(q).is_suspended) 531 532 enum mqd_update_flag { 533 UPDATE_FLAG_DBG_WA_ENABLE = 1, 534 UPDATE_FLAG_DBG_WA_DISABLE = 2, 535 }; 536 537 struct mqd_update_info { 538 union { 539 struct { 540 uint32_t count; /* Must be a multiple of 32 */ 541 uint32_t *ptr; 542 } cu_mask; 543 }; 544 enum mqd_update_flag update_flag; 545 }; 546 547 /** 548 * struct queue 549 * 550 * @list: Queue linked list. 551 * 552 * @mqd: The queue MQD (memory queue descriptor). 553 * 554 * @mqd_mem_obj: The MQD local gpu memory object. 555 * 556 * @gart_mqd_addr: The MQD gart mc address. 557 * 558 * @properties: The queue properties. 559 * 560 * @mec: Used only in no cp scheduling mode and identifies to micro engine id 561 * that the queue should be executed on. 562 * 563 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe 564 * id. 565 * 566 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. 567 * 568 * @process: The kfd process that created this queue. 569 * 570 * @device: The kfd device that created this queue. 571 * 572 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL 573 * otherwise. 574 * 575 * This structure represents user mode compute queues. 576 * It contains all the necessary data to handle such queues. 577 * 578 */ 579 580 struct queue { 581 struct list_head list; 582 void *mqd; 583 struct kfd_mem_obj *mqd_mem_obj; 584 uint64_t gart_mqd_addr; 585 struct queue_properties properties; 586 587 uint32_t mec; 588 uint32_t pipe; 589 uint32_t queue; 590 591 unsigned int sdma_id; 592 unsigned int doorbell_id; 593 594 struct kfd_process *process; 595 struct kfd_node *device; 596 void *gws; 597 598 /* procfs */ 599 struct kobject kobj; 600 601 void *gang_ctx_bo; 602 uint64_t gang_ctx_gpu_addr; 603 void *gang_ctx_cpu_ptr; 604 605 struct amdgpu_bo *wptr_bo; 606 }; 607 608 enum KFD_MQD_TYPE { 609 KFD_MQD_TYPE_HIQ = 0, /* for hiq */ 610 KFD_MQD_TYPE_CP, /* for cp queues and diq */ 611 KFD_MQD_TYPE_SDMA, /* for sdma queues */ 612 KFD_MQD_TYPE_DIQ, /* for diq */ 613 KFD_MQD_TYPE_MAX 614 }; 615 616 enum KFD_PIPE_PRIORITY { 617 KFD_PIPE_PRIORITY_CS_LOW = 0, 618 KFD_PIPE_PRIORITY_CS_MEDIUM, 619 KFD_PIPE_PRIORITY_CS_HIGH 620 }; 621 622 struct scheduling_resources { 623 unsigned int vmid_mask; 624 enum kfd_queue_type type; 625 uint64_t queue_mask; 626 uint64_t gws_mask; 627 uint32_t oac_mask; 628 uint32_t gds_heap_base; 629 uint32_t gds_heap_size; 630 }; 631 632 struct process_queue_manager { 633 /* data */ 634 struct kfd_process *process; 635 struct list_head queues; 636 unsigned long *queue_slot_bitmap; 637 }; 638 639 struct qcm_process_device { 640 /* The Device Queue Manager that owns this data */ 641 struct device_queue_manager *dqm; 642 struct process_queue_manager *pqm; 643 /* Queues list */ 644 struct list_head queues_list; 645 struct list_head priv_queue_list; 646 647 unsigned int queue_count; 648 unsigned int vmid; 649 bool is_debug; 650 unsigned int evicted; /* eviction counter, 0=active */ 651 652 /* This flag tells if we should reset all wavefronts on 653 * process termination 654 */ 655 bool reset_wavefronts; 656 657 /* This flag tells us if this process has a GWS-capable 658 * queue that will be mapped into the runlist. It's 659 * possible to request a GWS BO, but not have the queue 660 * currently mapped, and this changes how the MAP_PROCESS 661 * PM4 packet is configured. 662 */ 663 bool mapped_gws_queue; 664 665 /* All the memory management data should be here too */ 666 uint64_t gds_context_area; 667 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */ 668 uint64_t page_table_base; 669 uint32_t sh_mem_config; 670 uint32_t sh_mem_bases; 671 uint32_t sh_mem_ape1_base; 672 uint32_t sh_mem_ape1_limit; 673 uint32_t gds_size; 674 uint32_t num_gws; 675 uint32_t num_oac; 676 uint32_t sh_hidden_private_base; 677 678 /* CWSR memory */ 679 struct kgd_mem *cwsr_mem; 680 void *cwsr_kaddr; 681 uint64_t cwsr_base; 682 uint64_t tba_addr; 683 uint64_t tma_addr; 684 685 /* IB memory */ 686 struct kgd_mem *ib_mem; 687 uint64_t ib_base; 688 void *ib_kaddr; 689 690 /* doorbells for kfd process */ 691 struct amdgpu_bo *proc_doorbells; 692 693 /* bitmap for dynamic doorbell allocation from the bo */ 694 unsigned long *doorbell_bitmap; 695 }; 696 697 /* KFD Memory Eviction */ 698 699 /* Approx. wait time before attempting to restore evicted BOs */ 700 #define PROCESS_RESTORE_TIME_MS 100 701 /* Approx. back off time if restore fails due to lack of memory */ 702 #define PROCESS_BACK_OFF_TIME_MS 100 703 /* Approx. time before evicting the process again */ 704 #define PROCESS_ACTIVE_TIME_MS 10 705 706 /* 8 byte handle containing GPU ID in the most significant 4 bytes and 707 * idr_handle in the least significant 4 bytes 708 */ 709 #define MAKE_HANDLE(gpu_id, idr_handle) \ 710 (((uint64_t)(gpu_id) << 32) + idr_handle) 711 #define GET_GPU_ID(handle) (handle >> 32) 712 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF) 713 714 enum kfd_pdd_bound { 715 PDD_UNBOUND = 0, 716 PDD_BOUND, 717 PDD_BOUND_SUSPENDED, 718 }; 719 720 #define MAX_SYSFS_FILENAME_LEN 15 721 722 /* 723 * SDMA counter runs at 100MHz frequency. 724 * We display SDMA activity in microsecond granularity in sysfs. 725 * As a result, the divisor is 100. 726 */ 727 #define SDMA_ACTIVITY_DIVISOR 100 728 729 /* Data that is per-process-per device. */ 730 struct kfd_process_device { 731 /* The device that owns this data. */ 732 struct kfd_node *dev; 733 734 /* The process that owns this kfd_process_device. */ 735 struct kfd_process *process; 736 737 /* per-process-per device QCM data structure */ 738 struct qcm_process_device qpd; 739 740 /*Apertures*/ 741 uint64_t lds_base; 742 uint64_t lds_limit; 743 uint64_t gpuvm_base; 744 uint64_t gpuvm_limit; 745 uint64_t scratch_base; 746 uint64_t scratch_limit; 747 748 /* VM context for GPUVM allocations */ 749 struct file *drm_file; 750 void *drm_priv; 751 752 /* GPUVM allocations storage */ 753 struct idr alloc_idr; 754 755 /* Flag used to tell the pdd has dequeued from the dqm. 756 * This is used to prevent dev->dqm->ops.process_termination() from 757 * being called twice when it is already called in IOMMU callback 758 * function. 759 */ 760 bool already_dequeued; 761 bool runtime_inuse; 762 763 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ 764 enum kfd_pdd_bound bound; 765 766 /* VRAM usage */ 767 uint64_t vram_usage; 768 struct attribute attr_vram; 769 char vram_filename[MAX_SYSFS_FILENAME_LEN]; 770 771 /* SDMA activity tracking */ 772 uint64_t sdma_past_activity_counter; 773 struct attribute attr_sdma; 774 char sdma_filename[MAX_SYSFS_FILENAME_LEN]; 775 776 /* Eviction activity tracking */ 777 uint64_t last_evict_timestamp; 778 atomic64_t evict_duration_counter; 779 struct attribute attr_evict; 780 781 struct kobject *kobj_stats; 782 783 /* 784 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process 785 * that is associated with device encoded by "this" struct instance. The 786 * value reflects CU usage by all of the waves launched by this process 787 * on this device. A very important property of occupancy parameter is 788 * that its value is a snapshot of current use. 789 * 790 * Following is to be noted regarding how this parameter is reported: 791 * 792 * The number of waves that a CU can launch is limited by couple of 793 * parameters. These are encoded by struct amdgpu_cu_info instance 794 * that is part of every device definition. For GFX9 devices this 795 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves 796 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu) 797 * when they do use scratch memory. This could change for future 798 * devices and therefore this example should be considered as a guide. 799 * 800 * All CU's of a device are available for the process. This may not be true 801 * under certain conditions - e.g. CU masking. 802 * 803 * Finally number of CU's that are occupied by a process is affected by both 804 * number of CU's a device has along with number of other competing processes 805 */ 806 struct attribute attr_cu_occupancy; 807 808 /* sysfs counters for GPU retry fault and page migration tracking */ 809 struct kobject *kobj_counters; 810 struct attribute attr_faults; 811 struct attribute attr_page_in; 812 struct attribute attr_page_out; 813 uint64_t faults; 814 uint64_t page_in; 815 uint64_t page_out; 816 817 /* Exception code status*/ 818 uint64_t exception_status; 819 void *vm_fault_exc_data; 820 size_t vm_fault_exc_data_size; 821 822 /* Tracks debug per-vmid request settings */ 823 uint32_t spi_dbg_override; 824 uint32_t spi_dbg_launch_mode; 825 uint32_t watch_points[4]; 826 uint32_t alloc_watch_ids; 827 828 /* 829 * If this process has been checkpointed before, then the user 830 * application will use the original gpu_id on the 831 * checkpointed node to refer to this device. 832 */ 833 uint32_t user_gpu_id; 834 835 void *proc_ctx_bo; 836 uint64_t proc_ctx_gpu_addr; 837 void *proc_ctx_cpu_ptr; 838 }; 839 840 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) 841 842 struct svm_range_list { 843 struct mutex lock; 844 struct rb_root_cached objects; 845 struct list_head list; 846 struct work_struct deferred_list_work; 847 struct list_head deferred_range_list; 848 struct list_head criu_svm_metadata_list; 849 spinlock_t deferred_list_lock; 850 atomic_t evicted_ranges; 851 atomic_t drain_pagefaults; 852 struct delayed_work restore_work; 853 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); 854 struct task_struct *faulting_task; 855 }; 856 857 /* Process data */ 858 struct kfd_process { 859 /* 860 * kfd_process are stored in an mm_struct*->kfd_process* 861 * hash table (kfd_processes in kfd_process.c) 862 */ 863 struct hlist_node kfd_processes; 864 865 /* 866 * Opaque pointer to mm_struct. We don't hold a reference to 867 * it so it should never be dereferenced from here. This is 868 * only used for looking up processes by their mm. 869 */ 870 void *mm; 871 872 struct kref ref; 873 struct work_struct release_work; 874 875 struct mutex mutex; 876 877 /* 878 * In any process, the thread that started main() is the lead 879 * thread and outlives the rest. 880 * It is here because amd_iommu_bind_pasid wants a task_struct. 881 * It can also be used for safely getting a reference to the 882 * mm_struct of the process. 883 */ 884 struct task_struct *lead_thread; 885 886 /* We want to receive a notification when the mm_struct is destroyed */ 887 struct mmu_notifier mmu_notifier; 888 889 u32 pasid; 890 891 /* 892 * Array of kfd_process_device pointers, 893 * one for each device the process is using. 894 */ 895 struct kfd_process_device *pdds[MAX_GPU_INSTANCE]; 896 uint32_t n_pdds; 897 898 struct process_queue_manager pqm; 899 900 /*Is the user space process 32 bit?*/ 901 bool is_32bit_user_mode; 902 903 /* Event-related data */ 904 struct mutex event_mutex; 905 /* Event ID allocator and lookup */ 906 struct idr event_idr; 907 /* Event page */ 908 u64 signal_handle; 909 struct kfd_signal_page *signal_page; 910 size_t signal_mapped_size; 911 size_t signal_event_count; 912 bool signal_event_limit_reached; 913 914 /* Information used for memory eviction */ 915 void *kgd_process_info; 916 /* Eviction fence that is attached to all the BOs of this process. The 917 * fence will be triggered during eviction and new one will be created 918 * during restore 919 */ 920 struct dma_fence *ef; 921 922 /* Work items for evicting and restoring BOs */ 923 struct delayed_work eviction_work; 924 struct delayed_work restore_work; 925 /* seqno of the last scheduled eviction */ 926 unsigned int last_eviction_seqno; 927 /* Approx. the last timestamp (in jiffies) when the process was 928 * restored after an eviction 929 */ 930 unsigned long last_restore_timestamp; 931 932 /* Indicates device process is debug attached with reserved vmid. */ 933 bool debug_trap_enabled; 934 935 /* per-process-per device debug event fd file */ 936 struct file *dbg_ev_file; 937 938 /* If the process is a kfd debugger, we need to know so we can clean 939 * up at exit time. If a process enables debugging on itself, it does 940 * its own clean-up, so we don't set the flag here. We track this by 941 * counting the number of processes this process is debugging. 942 */ 943 atomic_t debugged_process_count; 944 945 /* If the process is a debugged, this is the debugger process */ 946 struct kfd_process *debugger_process; 947 948 /* Kobj for our procfs */ 949 struct kobject *kobj; 950 struct kobject *kobj_queues; 951 struct attribute attr_pasid; 952 953 /* Keep track cwsr init */ 954 bool has_cwsr; 955 956 /* Exception code enable mask and status */ 957 uint64_t exception_enable_mask; 958 uint64_t exception_status; 959 960 /* Used to drain stale interrupts */ 961 wait_queue_head_t wait_irq_drain; 962 bool irq_drain_is_open; 963 964 /* shared virtual memory registered by this process */ 965 struct svm_range_list svms; 966 967 bool xnack_enabled; 968 969 /* Work area for debugger event writer worker. */ 970 struct work_struct debug_event_workarea; 971 972 /* Tracks debug per-vmid request for debug flags */ 973 bool dbg_flags; 974 975 atomic_t poison; 976 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */ 977 bool queues_paused; 978 979 /* Tracks runtime enable status */ 980 struct semaphore runtime_enable_sema; 981 bool is_runtime_retry; 982 struct kfd_runtime_info runtime_info; 983 }; 984 985 #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ 986 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); 987 extern struct srcu_struct kfd_processes_srcu; 988 989 /** 990 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer. 991 * 992 * @filep: pointer to file structure. 993 * @p: amdkfd process pointer. 994 * @data: pointer to arg that was copied from user. 995 * 996 * Return: returns ioctl completion code. 997 */ 998 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, 999 void *data); 1000 1001 struct amdkfd_ioctl_desc { 1002 unsigned int cmd; 1003 int flags; 1004 amdkfd_ioctl_t *func; 1005 unsigned int cmd_drv; 1006 const char *name; 1007 }; 1008 bool kfd_dev_is_large_bar(struct kfd_node *dev); 1009 1010 int kfd_process_create_wq(void); 1011 void kfd_process_destroy_wq(void); 1012 void kfd_cleanup_processes(void); 1013 struct kfd_process *kfd_create_process(struct task_struct *thread); 1014 struct kfd_process *kfd_get_process(const struct task_struct *task); 1015 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid); 1016 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); 1017 1018 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); 1019 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, 1020 uint32_t *gpuid, uint32_t *gpuidx); 1021 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, 1022 uint32_t gpuidx, uint32_t *gpuid) { 1023 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; 1024 } 1025 static inline struct kfd_process_device *kfd_process_device_from_gpuidx( 1026 struct kfd_process *p, uint32_t gpuidx) { 1027 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; 1028 } 1029 1030 void kfd_unref_process(struct kfd_process *p); 1031 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); 1032 int kfd_process_restore_queues(struct kfd_process *p); 1033 void kfd_suspend_all_processes(void); 1034 int kfd_resume_all_processes(void); 1035 1036 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, 1037 uint32_t gpu_id); 1038 1039 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id); 1040 1041 int kfd_process_device_init_vm(struct kfd_process_device *pdd, 1042 struct file *drm_file); 1043 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, 1044 struct kfd_process *p); 1045 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev, 1046 struct kfd_process *p); 1047 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, 1048 struct kfd_process *p); 1049 1050 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); 1051 1052 int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, 1053 struct vm_area_struct *vma); 1054 1055 /* KFD process API for creating and translating handles */ 1056 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, 1057 void *mem); 1058 void *kfd_process_device_translate_handle(struct kfd_process_device *p, 1059 int handle); 1060 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, 1061 int handle); 1062 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); 1063 1064 /* PASIDs */ 1065 int kfd_pasid_init(void); 1066 void kfd_pasid_exit(void); 1067 bool kfd_set_pasid_limit(unsigned int new_limit); 1068 unsigned int kfd_get_pasid_limit(void); 1069 u32 kfd_pasid_alloc(void); 1070 void kfd_pasid_free(u32 pasid); 1071 1072 /* Doorbells */ 1073 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd); 1074 int kfd_doorbell_init(struct kfd_dev *kfd); 1075 void kfd_doorbell_fini(struct kfd_dev *kfd); 1076 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, 1077 struct vm_area_struct *vma); 1078 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, 1079 unsigned int *doorbell_off); 1080 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); 1081 u32 read_kernel_doorbell(u32 __iomem *db); 1082 void write_kernel_doorbell(void __iomem *db, u32 value); 1083 void write_kernel_doorbell64(void __iomem *db, u64 value); 1084 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd, 1085 struct kfd_process_device *pdd, 1086 unsigned int doorbell_id); 1087 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd); 1088 int kfd_alloc_process_doorbells(struct kfd_dev *kfd, 1089 struct kfd_process_device *pdd); 1090 void kfd_free_process_doorbells(struct kfd_dev *kfd, 1091 struct kfd_process_device *pdd); 1092 /* GTT Sub-Allocator */ 1093 1094 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1095 struct kfd_mem_obj **mem_obj); 1096 1097 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj); 1098 1099 extern struct device *kfd_device; 1100 1101 /* KFD's procfs */ 1102 void kfd_procfs_init(void); 1103 void kfd_procfs_shutdown(void); 1104 int kfd_procfs_add_queue(struct queue *q); 1105 void kfd_procfs_del_queue(struct queue *q); 1106 1107 /* Topology */ 1108 int kfd_topology_init(void); 1109 void kfd_topology_shutdown(void); 1110 int kfd_topology_add_device(struct kfd_node *gpu); 1111 int kfd_topology_remove_device(struct kfd_node *gpu); 1112 struct kfd_topology_device *kfd_topology_device_by_proximity_domain( 1113 uint32_t proximity_domain); 1114 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock( 1115 uint32_t proximity_domain); 1116 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); 1117 struct kfd_node *kfd_device_by_id(uint32_t gpu_id); 1118 struct kfd_node *kfd_device_by_pci_dev(const struct pci_dev *pdev); 1119 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id, 1120 uint32_t vmid) 1121 { 1122 return (node->interrupt_bitmap & (1 << node_id)) != 0 && 1123 (node->compute_vmid_bitmap & (1 << vmid)) != 0; 1124 } 1125 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, 1126 uint32_t node_id, uint32_t vmid) { 1127 struct kfd_dev *dev = adev->kfd.dev; 1128 uint32_t i; 1129 1130 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) 1131 return dev->nodes[0]; 1132 1133 for (i = 0; i < dev->num_nodes; i++) 1134 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid)) 1135 return dev->nodes[i]; 1136 1137 return NULL; 1138 } 1139 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); 1140 int kfd_numa_node_to_apic_id(int numa_node_id); 1141 1142 /* Interrupts */ 1143 #define KFD_IRQ_FENCE_CLIENTID 0xff 1144 #define KFD_IRQ_FENCE_SOURCEID 0xff 1145 #define KFD_IRQ_IS_FENCE(client, source) \ 1146 ((client) == KFD_IRQ_FENCE_CLIENTID && \ 1147 (source) == KFD_IRQ_FENCE_SOURCEID) 1148 int kfd_interrupt_init(struct kfd_node *dev); 1149 void kfd_interrupt_exit(struct kfd_node *dev); 1150 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry); 1151 bool interrupt_is_wanted(struct kfd_node *dev, 1152 const uint32_t *ih_ring_entry, 1153 uint32_t *patched_ihre, bool *flag); 1154 int kfd_process_drain_interrupts(struct kfd_process_device *pdd); 1155 void kfd_process_close_interrupt_drain(unsigned int pasid); 1156 1157 /* amdkfd Apertures */ 1158 int kfd_init_apertures(struct kfd_process *process); 1159 1160 void kfd_process_set_trap_handler(struct qcm_process_device *qpd, 1161 uint64_t tba_addr, 1162 uint64_t tma_addr); 1163 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, 1164 bool enabled); 1165 1166 /* CWSR initialization */ 1167 int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); 1168 1169 /* CRIU */ 1170 /* 1171 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private 1172 * structures: 1173 * kfd_criu_process_priv_data 1174 * kfd_criu_device_priv_data 1175 * kfd_criu_bo_priv_data 1176 * kfd_criu_queue_priv_data 1177 * kfd_criu_event_priv_data 1178 * kfd_criu_svm_range_priv_data 1179 */ 1180 1181 #define KFD_CRIU_PRIV_VERSION 1 1182 1183 struct kfd_criu_process_priv_data { 1184 uint32_t version; 1185 uint32_t xnack_mode; 1186 }; 1187 1188 struct kfd_criu_device_priv_data { 1189 /* For future use */ 1190 uint64_t reserved; 1191 }; 1192 1193 struct kfd_criu_bo_priv_data { 1194 uint64_t user_addr; 1195 uint32_t idr_handle; 1196 uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; 1197 }; 1198 1199 /* 1200 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data, 1201 * kfd_criu_svm_range_priv_data is the object type 1202 */ 1203 enum kfd_criu_object_type { 1204 KFD_CRIU_OBJECT_TYPE_QUEUE, 1205 KFD_CRIU_OBJECT_TYPE_EVENT, 1206 KFD_CRIU_OBJECT_TYPE_SVM_RANGE, 1207 }; 1208 1209 struct kfd_criu_svm_range_priv_data { 1210 uint32_t object_type; 1211 uint64_t start_addr; 1212 uint64_t size; 1213 /* Variable length array of attributes */ 1214 struct kfd_ioctl_svm_attribute attrs[]; 1215 }; 1216 1217 struct kfd_criu_queue_priv_data { 1218 uint32_t object_type; 1219 uint64_t q_address; 1220 uint64_t q_size; 1221 uint64_t read_ptr_addr; 1222 uint64_t write_ptr_addr; 1223 uint64_t doorbell_off; 1224 uint64_t eop_ring_buffer_address; 1225 uint64_t ctx_save_restore_area_address; 1226 uint32_t gpu_id; 1227 uint32_t type; 1228 uint32_t format; 1229 uint32_t q_id; 1230 uint32_t priority; 1231 uint32_t q_percent; 1232 uint32_t doorbell_id; 1233 uint32_t gws; 1234 uint32_t sdma_id; 1235 uint32_t eop_ring_buffer_size; 1236 uint32_t ctx_save_restore_area_size; 1237 uint32_t ctl_stack_size; 1238 uint32_t mqd_size; 1239 }; 1240 1241 struct kfd_criu_event_priv_data { 1242 uint32_t object_type; 1243 uint64_t user_handle; 1244 uint32_t event_id; 1245 uint32_t auto_reset; 1246 uint32_t type; 1247 uint32_t signaled; 1248 1249 union { 1250 struct kfd_hsa_memory_exception_data memory_exception_data; 1251 struct kfd_hsa_hw_exception_data hw_exception_data; 1252 }; 1253 }; 1254 1255 int kfd_process_get_queue_info(struct kfd_process *p, 1256 uint32_t *num_queues, 1257 uint64_t *priv_data_sizes); 1258 1259 int kfd_criu_checkpoint_queues(struct kfd_process *p, 1260 uint8_t __user *user_priv_data, 1261 uint64_t *priv_data_offset); 1262 1263 int kfd_criu_restore_queue(struct kfd_process *p, 1264 uint8_t __user *user_priv_data, 1265 uint64_t *priv_data_offset, 1266 uint64_t max_priv_data_size); 1267 1268 int kfd_criu_checkpoint_events(struct kfd_process *p, 1269 uint8_t __user *user_priv_data, 1270 uint64_t *priv_data_offset); 1271 1272 int kfd_criu_restore_event(struct file *devkfd, 1273 struct kfd_process *p, 1274 uint8_t __user *user_priv_data, 1275 uint64_t *priv_data_offset, 1276 uint64_t max_priv_data_size); 1277 /* CRIU - End */ 1278 1279 /* Queue Context Management */ 1280 int init_queue(struct queue **q, const struct queue_properties *properties); 1281 void uninit_queue(struct queue *q); 1282 void print_queue_properties(struct queue_properties *q); 1283 void print_queue(struct queue *q); 1284 1285 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 1286 struct kfd_node *dev); 1287 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 1288 struct kfd_node *dev); 1289 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 1290 struct kfd_node *dev); 1291 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 1292 struct kfd_node *dev); 1293 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 1294 struct kfd_node *dev); 1295 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev); 1296 void device_queue_manager_uninit(struct device_queue_manager *dqm); 1297 struct kernel_queue *kernel_queue_init(struct kfd_node *dev, 1298 enum kfd_queue_type type); 1299 void kernel_queue_uninit(struct kernel_queue *kq, bool hanging); 1300 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid); 1301 1302 /* Process Queue Manager */ 1303 struct process_queue_node { 1304 struct queue *q; 1305 struct kernel_queue *kq; 1306 struct list_head process_queue_list; 1307 }; 1308 1309 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd); 1310 void kfd_process_dequeue_from_all_devices(struct kfd_process *p); 1311 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); 1312 void pqm_uninit(struct process_queue_manager *pqm); 1313 int pqm_create_queue(struct process_queue_manager *pqm, 1314 struct kfd_node *dev, 1315 struct file *f, 1316 struct queue_properties *properties, 1317 unsigned int *qid, 1318 struct amdgpu_bo *wptr_bo, 1319 const struct kfd_criu_queue_priv_data *q_data, 1320 const void *restore_mqd, 1321 const void *restore_ctl_stack, 1322 uint32_t *p_doorbell_offset_in_process); 1323 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); 1324 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid, 1325 struct queue_properties *p); 1326 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid, 1327 struct mqd_update_info *minfo); 1328 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 1329 void *gws); 1330 struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm, 1331 unsigned int qid); 1332 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 1333 unsigned int qid); 1334 int pqm_get_wave_state(struct process_queue_manager *pqm, 1335 unsigned int qid, 1336 void __user *ctl_stack, 1337 u32 *ctl_stack_used_size, 1338 u32 *save_area_used_size); 1339 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 1340 uint64_t exception_clear_mask, 1341 void __user *buf, 1342 int *num_qss_entries, 1343 uint32_t *entry_size); 1344 1345 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 1346 uint64_t fence_value, 1347 unsigned int timeout_ms); 1348 1349 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1350 unsigned int qid, 1351 u32 *mqd_size, 1352 u32 *ctl_stack_size); 1353 /* Packet Manager */ 1354 1355 #define KFD_FENCE_COMPLETED (100) 1356 #define KFD_FENCE_INIT (10) 1357 1358 struct packet_manager { 1359 struct device_queue_manager *dqm; 1360 struct kernel_queue *priv_queue; 1361 struct mutex lock; 1362 bool allocated; 1363 struct kfd_mem_obj *ib_buffer_obj; 1364 unsigned int ib_size_bytes; 1365 bool is_over_subscription; 1366 1367 const struct packet_manager_funcs *pmf; 1368 }; 1369 1370 struct packet_manager_funcs { 1371 /* Support ASIC-specific packet formats for PM4 packets */ 1372 int (*map_process)(struct packet_manager *pm, uint32_t *buffer, 1373 struct qcm_process_device *qpd); 1374 int (*runlist)(struct packet_manager *pm, uint32_t *buffer, 1375 uint64_t ib, size_t ib_size_in_dwords, bool chain); 1376 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, 1377 struct scheduling_resources *res); 1378 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, 1379 struct queue *q, bool is_static); 1380 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, 1381 enum kfd_unmap_queues_filter mode, 1382 uint32_t filter_param, bool reset); 1383 int (*set_grace_period)(struct packet_manager *pm, uint32_t *buffer, 1384 uint32_t grace_period); 1385 int (*query_status)(struct packet_manager *pm, uint32_t *buffer, 1386 uint64_t fence_address, uint64_t fence_value); 1387 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); 1388 1389 /* Packet sizes */ 1390 int map_process_size; 1391 int runlist_size; 1392 int set_resources_size; 1393 int map_queues_size; 1394 int unmap_queues_size; 1395 int set_grace_period_size; 1396 int query_status_size; 1397 int release_mem_size; 1398 }; 1399 1400 extern const struct packet_manager_funcs kfd_vi_pm_funcs; 1401 extern const struct packet_manager_funcs kfd_v9_pm_funcs; 1402 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; 1403 1404 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); 1405 void pm_uninit(struct packet_manager *pm, bool hanging); 1406 int pm_send_set_resources(struct packet_manager *pm, 1407 struct scheduling_resources *res); 1408 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); 1409 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, 1410 uint64_t fence_value); 1411 1412 int pm_send_unmap_queue(struct packet_manager *pm, 1413 enum kfd_unmap_queues_filter mode, 1414 uint32_t filter_param, bool reset); 1415 1416 void pm_release_ib(struct packet_manager *pm); 1417 1418 int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period); 1419 1420 /* Following PM funcs can be shared among VI and AI */ 1421 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); 1422 1423 uint64_t kfd_get_number_elems(struct kfd_dev *kfd); 1424 1425 /* Events */ 1426 extern const struct kfd_event_interrupt_class event_interrupt_class_cik; 1427 extern const struct kfd_event_interrupt_class event_interrupt_class_v9; 1428 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3; 1429 extern const struct kfd_event_interrupt_class event_interrupt_class_v10; 1430 extern const struct kfd_event_interrupt_class event_interrupt_class_v11; 1431 1432 extern const struct kfd_device_global_init_class device_global_init_class_cik; 1433 1434 int kfd_event_init_process(struct kfd_process *p); 1435 void kfd_event_free_process(struct kfd_process *p); 1436 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); 1437 int kfd_wait_on_events(struct kfd_process *p, 1438 uint32_t num_events, void __user *data, 1439 bool all, uint32_t *user_timeout_ms, 1440 uint32_t *wait_result); 1441 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, 1442 uint32_t valid_id_bits); 1443 void kfd_signal_hw_exception_event(u32 pasid); 1444 int kfd_set_event(struct kfd_process *p, uint32_t event_id); 1445 int kfd_reset_event(struct kfd_process *p, uint32_t event_id); 1446 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset); 1447 1448 int kfd_event_create(struct file *devkfd, struct kfd_process *p, 1449 uint32_t event_type, bool auto_reset, uint32_t node_id, 1450 uint32_t *event_id, uint32_t *event_trigger_data, 1451 uint64_t *event_page_offset, uint32_t *event_slot_index); 1452 1453 int kfd_get_num_events(struct kfd_process *p); 1454 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); 1455 1456 void kfd_signal_vm_fault_event(struct kfd_node *dev, u32 pasid, 1457 struct kfd_vm_fault_info *info, 1458 struct kfd_hsa_memory_exception_data *data); 1459 1460 void kfd_signal_reset_event(struct kfd_node *dev); 1461 1462 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); 1463 1464 static inline void kfd_flush_tlb(struct kfd_process_device *pdd, 1465 enum TLB_FLUSH_TYPE type) 1466 { 1467 struct amdgpu_device *adev = pdd->dev->adev; 1468 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv); 1469 1470 amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask); 1471 } 1472 1473 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) 1474 { 1475 return KFD_GC_VERSION(dev) > IP_VERSION(9, 4, 2) || 1476 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || 1477 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); 1478 } 1479 1480 int kfd_send_exception_to_runtime(struct kfd_process *p, 1481 unsigned int queue_id, 1482 uint64_t error_reason); 1483 bool kfd_is_locked(void); 1484 1485 /* Compute profile */ 1486 void kfd_inc_compute_active(struct kfd_node *dev); 1487 void kfd_dec_compute_active(struct kfd_node *dev); 1488 1489 /* Cgroup Support */ 1490 /* Check with device cgroup if @kfd device is accessible */ 1491 static inline int kfd_devcgroup_check_permission(struct kfd_node *kfd) 1492 { 1493 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) 1494 struct drm_device *ddev = adev_to_drm(kfd->adev); 1495 1496 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, 1497 ddev->render->index, 1498 DEVCG_ACC_WRITE | DEVCG_ACC_READ); 1499 #else 1500 return 0; 1501 #endif 1502 } 1503 1504 static inline bool kfd_is_first_node(struct kfd_node *node) 1505 { 1506 return (node == node->kfd->nodes[0]); 1507 } 1508 1509 /* Debugfs */ 1510 #if defined(CONFIG_DEBUG_FS) 1511 1512 void kfd_debugfs_init(void); 1513 void kfd_debugfs_fini(void); 1514 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); 1515 int pqm_debugfs_mqds(struct seq_file *m, void *data); 1516 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); 1517 int dqm_debugfs_hqds(struct seq_file *m, void *data); 1518 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); 1519 int pm_debugfs_runlist(struct seq_file *m, void *data); 1520 1521 int kfd_debugfs_hang_hws(struct kfd_node *dev); 1522 int pm_debugfs_hang_hws(struct packet_manager *pm); 1523 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm); 1524 1525 #else 1526 1527 static inline void kfd_debugfs_init(void) {} 1528 static inline void kfd_debugfs_fini(void) {} 1529 1530 #endif 1531 1532 #endif 1533