1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned int type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 * sequences performed by PSP BL 423 */ 424 if (adev->asic_type >= CHIP_VEGA20) 425 return 0; 426 427 bits = 0x7f; 428 429 switch (state) { 430 case AMDGPU_IRQ_STATE_DISABLE: 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 439 tmp = RREG32(reg); 440 tmp &= ~bits; 441 WREG32(reg, tmp); 442 } 443 break; 444 case AMDGPU_IRQ_STATE_ENABLE: 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 453 tmp = RREG32(reg); 454 tmp |= bits; 455 WREG32(reg, tmp); 456 } 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 466 struct amdgpu_irq_src *src, 467 unsigned int type, 468 enum amdgpu_interrupt_state state) 469 { 470 struct amdgpu_vmhub *hub; 471 u32 tmp, reg, bits, i, j; 472 473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 480 481 switch (state) { 482 case AMDGPU_IRQ_STATE_DISABLE: 483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 484 hub = &adev->vmhub[j]; 485 for (i = 0; i < 16; i++) { 486 reg = hub->vm_context0_cntl + i; 487 488 /* This works because this interrupt is only 489 * enabled at init/resume and disabled in 490 * fini/suspend, so the overall state doesn't 491 * change over the course of suspend/resume. 492 */ 493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 494 continue; 495 496 if (j >= AMDGPU_MMHUB0(0)) 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 498 else 499 tmp = RREG32_XCC(reg, j); 500 501 tmp &= ~bits; 502 503 if (j >= AMDGPU_MMHUB0(0)) 504 WREG32_SOC15_IP(MMHUB, reg, tmp); 505 else 506 WREG32_XCC(reg, tmp, j); 507 } 508 } 509 break; 510 case AMDGPU_IRQ_STATE_ENABLE: 511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 512 hub = &adev->vmhub[j]; 513 for (i = 0; i < 16; i++) { 514 reg = hub->vm_context0_cntl + i; 515 516 /* This works because this interrupt is only 517 * enabled at init/resume and disabled in 518 * fini/suspend, so the overall state doesn't 519 * change over the course of suspend/resume. 520 */ 521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 522 continue; 523 524 if (j >= AMDGPU_MMHUB0(0)) 525 tmp = RREG32_SOC15_IP(MMHUB, reg); 526 else 527 tmp = RREG32_XCC(reg, j); 528 529 tmp |= bits; 530 531 if (j >= AMDGPU_MMHUB0(0)) 532 WREG32_SOC15_IP(MMHUB, reg, tmp); 533 else 534 WREG32_XCC(reg, tmp, j); 535 } 536 } 537 break; 538 default: 539 break; 540 } 541 542 return 0; 543 } 544 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 546 struct amdgpu_irq_src *source, 547 struct amdgpu_iv_entry *entry) 548 { 549 bool retry_fault = !!(entry->src_data[1] & 0x80); 550 bool write_fault = !!(entry->src_data[1] & 0x20); 551 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 552 struct amdgpu_task_info *task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, entry->timestamp, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, entry->timestamp, write_fault)) 622 return 1; 623 } 624 } 625 626 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) 627 return 1; 628 629 if (!printk_ratelimit()) 630 return 0; 631 632 dev_err(adev->dev, 633 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 634 retry_fault ? "retry" : "no-retry", 635 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 636 637 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 638 if (task_info) { 639 dev_err(adev->dev, 640 " for process %s pid %d thread %s pid %d)\n", 641 task_info->process_name, task_info->tgid, 642 task_info->task_name, task_info->pid); 643 amdgpu_vm_put_task_info(task_info); 644 } 645 646 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 647 addr, entry->client_id, 648 soc15_ih_clientid_name[entry->client_id]); 649 650 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 651 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 652 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 653 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 654 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 655 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 656 657 if (amdgpu_sriov_vf(adev)) 658 return 0; 659 660 /* 661 * Issue a dummy read to wait for the status register to 662 * be updated to avoid reading an incorrect value due to 663 * the new fast GRBM interface. 664 */ 665 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 666 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 667 RREG32(hub->vm_l2_pro_fault_status); 668 669 status = RREG32(hub->vm_l2_pro_fault_status); 670 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 671 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 672 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 673 674 /* for fed error, kfd will handle it, return directly */ 675 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 676 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 677 return 0; 678 679 /* Only print L2 fault status if the status register could be read and 680 * contains useful information 681 */ 682 if (!status) 683 return 0; 684 685 if (!amdgpu_sriov_vf(adev)) 686 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 687 688 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 689 690 dev_err(adev->dev, 691 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 692 status); 693 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 694 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 695 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 696 gfxhub_client_ids[cid], 697 cid); 698 } else { 699 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 700 case IP_VERSION(9, 0, 0): 701 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 702 break; 703 case IP_VERSION(9, 3, 0): 704 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 705 break; 706 case IP_VERSION(9, 4, 0): 707 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 708 break; 709 case IP_VERSION(9, 4, 1): 710 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 711 break; 712 case IP_VERSION(9, 1, 0): 713 case IP_VERSION(9, 2, 0): 714 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 715 break; 716 case IP_VERSION(1, 5, 0): 717 case IP_VERSION(2, 4, 0): 718 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 719 break; 720 case IP_VERSION(1, 8, 0): 721 case IP_VERSION(9, 4, 2): 722 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 723 break; 724 default: 725 mmhub_cid = NULL; 726 break; 727 } 728 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 729 mmhub_cid ? mmhub_cid : "unknown", cid); 730 } 731 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 732 REG_GET_FIELD(status, 733 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 734 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 735 REG_GET_FIELD(status, 736 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 737 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 738 REG_GET_FIELD(status, 739 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 740 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 741 REG_GET_FIELD(status, 742 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 743 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 744 return 0; 745 } 746 747 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 748 .set = gmc_v9_0_vm_fault_interrupt_state, 749 .process = gmc_v9_0_process_interrupt, 750 }; 751 752 753 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 754 .set = gmc_v9_0_ecc_interrupt_state, 755 .process = amdgpu_umc_process_ecc_irq, 756 }; 757 758 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 759 { 760 adev->gmc.vm_fault.num_types = 1; 761 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 762 763 if (!amdgpu_sriov_vf(adev) && 764 !adev->gmc.xgmi.connected_to_cpu && 765 !adev->gmc.is_app_apu) { 766 adev->gmc.ecc_irq.num_types = 1; 767 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 768 } 769 } 770 771 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 772 uint32_t flush_type) 773 { 774 u32 req = 0; 775 776 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 777 PER_VMID_INVALIDATE_REQ, 1 << vmid); 778 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 779 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 780 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 781 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 782 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 783 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 784 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 785 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 786 787 return req; 788 } 789 790 /** 791 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 792 * 793 * @adev: amdgpu_device pointer 794 * @vmhub: vmhub type 795 * 796 */ 797 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 798 uint32_t vmhub) 799 { 800 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 801 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 802 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 803 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 804 return false; 805 806 return ((vmhub == AMDGPU_MMHUB0(0) || 807 vmhub == AMDGPU_MMHUB1(0)) && 808 (!amdgpu_sriov_vf(adev)) && 809 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 810 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 811 } 812 813 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 814 uint8_t vmid, uint16_t *p_pasid) 815 { 816 uint32_t value; 817 818 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 819 + vmid); 820 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 821 822 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 823 } 824 825 /* 826 * GART 827 * VMID 0 is the physical GPU addresses as used by the kernel. 828 * VMIDs 1-15 are used for userspace clients and are handled 829 * by the amdgpu vm/hsa code. 830 */ 831 832 /** 833 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 834 * 835 * @adev: amdgpu_device pointer 836 * @vmid: vm instance to flush 837 * @vmhub: which hub to flush 838 * @flush_type: the flush type 839 * 840 * Flush the TLB for the requested page table using certain type. 841 */ 842 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 843 uint32_t vmhub, uint32_t flush_type) 844 { 845 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 846 u32 j, inv_req, tmp, sem, req, ack, inst; 847 const unsigned int eng = 17; 848 struct amdgpu_vmhub *hub; 849 850 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 851 852 hub = &adev->vmhub[vmhub]; 853 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 854 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 855 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 856 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 857 858 if (vmhub >= AMDGPU_MMHUB0(0)) 859 inst = 0; 860 else 861 inst = vmhub; 862 863 /* This is necessary for SRIOV as well as for GFXOFF to function 864 * properly under bare metal 865 */ 866 if (adev->gfx.kiq[inst].ring.sched.ready && 867 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 868 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 869 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 870 871 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 872 1 << vmid, inst); 873 return; 874 } 875 876 /* This path is needed before KIQ/MES/GFXOFF are set up */ 877 spin_lock(&adev->gmc.invalidate_lock); 878 879 /* 880 * It may lose gpuvm invalidate acknowldege state across power-gating 881 * off cycle, add semaphore acquire before invalidation and semaphore 882 * release after invalidation to avoid entering power gated state 883 * to WA the Issue 884 */ 885 886 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 887 if (use_semaphore) { 888 for (j = 0; j < adev->usec_timeout; j++) { 889 /* a read return value of 1 means semaphore acquire */ 890 if (vmhub >= AMDGPU_MMHUB0(0)) 891 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 892 else 893 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 894 if (tmp & 0x1) 895 break; 896 udelay(1); 897 } 898 899 if (j >= adev->usec_timeout) 900 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 901 } 902 903 if (vmhub >= AMDGPU_MMHUB0(0)) 904 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 905 else 906 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 907 908 /* 909 * Issue a dummy read to wait for the ACK register to 910 * be cleared to avoid a false ACK due to the new fast 911 * GRBM interface. 912 */ 913 if ((vmhub == AMDGPU_GFXHUB(0)) && 914 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 915 RREG32_NO_KIQ(req); 916 917 for (j = 0; j < adev->usec_timeout; j++) { 918 if (vmhub >= AMDGPU_MMHUB0(0)) 919 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 920 else 921 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 922 if (tmp & (1 << vmid)) 923 break; 924 udelay(1); 925 } 926 927 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 928 if (use_semaphore) { 929 /* 930 * add semaphore release after invalidation, 931 * write with 0 means semaphore release 932 */ 933 if (vmhub >= AMDGPU_MMHUB0(0)) 934 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 935 else 936 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 937 } 938 939 spin_unlock(&adev->gmc.invalidate_lock); 940 941 if (j < adev->usec_timeout) 942 return; 943 944 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 945 } 946 947 /** 948 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 949 * 950 * @adev: amdgpu_device pointer 951 * @pasid: pasid to be flush 952 * @flush_type: the flush type 953 * @all_hub: flush all hubs 954 * @inst: is used to select which instance of KIQ to use for the invalidation 955 * 956 * Flush the TLB for the requested pasid. 957 */ 958 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 959 uint16_t pasid, uint32_t flush_type, 960 bool all_hub, uint32_t inst) 961 { 962 uint16_t queried; 963 int i, vmid; 964 965 for (vmid = 1; vmid < 16; vmid++) { 966 bool valid; 967 968 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 969 &queried); 970 if (!valid || queried != pasid) 971 continue; 972 973 if (all_hub) { 974 for_each_set_bit(i, adev->vmhubs_mask, 975 AMDGPU_MAX_VMHUBS) 976 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 977 flush_type); 978 } else { 979 gmc_v9_0_flush_gpu_tlb(adev, vmid, 980 AMDGPU_GFXHUB(0), 981 flush_type); 982 } 983 } 984 } 985 986 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 987 unsigned int vmid, uint64_t pd_addr) 988 { 989 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 990 struct amdgpu_device *adev = ring->adev; 991 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 992 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 993 unsigned int eng = ring->vm_inv_eng; 994 995 /* 996 * It may lose gpuvm invalidate acknowldege state across power-gating 997 * off cycle, add semaphore acquire before invalidation and semaphore 998 * release after invalidation to avoid entering power gated state 999 * to WA the Issue 1000 */ 1001 1002 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1003 if (use_semaphore) 1004 /* a read return value of 1 means semaphore acuqire */ 1005 amdgpu_ring_emit_reg_wait(ring, 1006 hub->vm_inv_eng0_sem + 1007 hub->eng_distance * eng, 0x1, 0x1); 1008 1009 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1010 (hub->ctx_addr_distance * vmid), 1011 lower_32_bits(pd_addr)); 1012 1013 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1014 (hub->ctx_addr_distance * vmid), 1015 upper_32_bits(pd_addr)); 1016 1017 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1018 hub->eng_distance * eng, 1019 hub->vm_inv_eng0_ack + 1020 hub->eng_distance * eng, 1021 req, 1 << vmid); 1022 1023 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1024 if (use_semaphore) 1025 /* 1026 * add semaphore release after invalidation, 1027 * write with 0 means semaphore release 1028 */ 1029 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1030 hub->eng_distance * eng, 0); 1031 1032 return pd_addr; 1033 } 1034 1035 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1036 unsigned int pasid) 1037 { 1038 struct amdgpu_device *adev = ring->adev; 1039 uint32_t reg; 1040 1041 /* Do nothing because there's no lut register for mmhub1. */ 1042 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1043 return; 1044 1045 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1046 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1047 else 1048 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1049 1050 amdgpu_ring_emit_wreg(ring, reg, pasid); 1051 } 1052 1053 /* 1054 * PTE format on VEGA 10: 1055 * 63:59 reserved 1056 * 58:57 mtype 1057 * 56 F 1058 * 55 L 1059 * 54 P 1060 * 53 SW 1061 * 52 T 1062 * 50:48 reserved 1063 * 47:12 4k physical page base address 1064 * 11:7 fragment 1065 * 6 write 1066 * 5 read 1067 * 4 exe 1068 * 3 Z 1069 * 2 snooped 1070 * 1 system 1071 * 0 valid 1072 * 1073 * PDE format on VEGA 10: 1074 * 63:59 block fragment size 1075 * 58:55 reserved 1076 * 54 P 1077 * 53:48 reserved 1078 * 47:6 physical base address of PD or PTE 1079 * 5:3 reserved 1080 * 2 C 1081 * 1 system 1082 * 0 valid 1083 */ 1084 1085 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1086 1087 { 1088 switch (flags) { 1089 case AMDGPU_VM_MTYPE_DEFAULT: 1090 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1091 case AMDGPU_VM_MTYPE_NC: 1092 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1093 case AMDGPU_VM_MTYPE_WC: 1094 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC); 1095 case AMDGPU_VM_MTYPE_RW: 1096 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW); 1097 case AMDGPU_VM_MTYPE_CC: 1098 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC); 1099 case AMDGPU_VM_MTYPE_UC: 1100 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC); 1101 default: 1102 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1103 } 1104 } 1105 1106 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1107 uint64_t *addr, uint64_t *flags) 1108 { 1109 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1110 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1111 BUG_ON(*addr & 0xFFFF00000000003FULL); 1112 1113 if (!adev->gmc.translate_further) 1114 return; 1115 1116 if (level == AMDGPU_VM_PDB1) { 1117 /* Set the block fragment size */ 1118 if (!(*flags & AMDGPU_PDE_PTE)) 1119 *flags |= AMDGPU_PDE_BFS(0x9); 1120 1121 } else if (level == AMDGPU_VM_PDB0) { 1122 if (*flags & AMDGPU_PDE_PTE) { 1123 *flags &= ~AMDGPU_PDE_PTE; 1124 if (!(*flags & AMDGPU_PTE_VALID)) 1125 *addr |= 1 << PAGE_SHIFT; 1126 } else { 1127 *flags |= AMDGPU_PTE_TF; 1128 } 1129 } 1130 } 1131 1132 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1133 struct amdgpu_bo *bo, 1134 struct amdgpu_bo_va_mapping *mapping, 1135 uint64_t *flags) 1136 { 1137 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1138 bool is_vram = bo->tbo.resource && 1139 bo->tbo.resource->mem_type == TTM_PL_VRAM; 1140 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 1141 AMDGPU_GEM_CREATE_EXT_COHERENT); 1142 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1143 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1144 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1145 unsigned int mtype_local, mtype; 1146 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 1147 bool snoop = false; 1148 bool is_local; 1149 1150 dma_resv_assert_held(bo->tbo.base.resv); 1151 1152 switch (gc_ip_version) { 1153 case IP_VERSION(9, 4, 1): 1154 case IP_VERSION(9, 4, 2): 1155 if (is_vram) { 1156 if (bo_adev == adev) { 1157 if (uncached) 1158 mtype = MTYPE_UC; 1159 else if (coherent) 1160 mtype = MTYPE_CC; 1161 else 1162 mtype = MTYPE_RW; 1163 /* FIXME: is this still needed? Or does 1164 * amdgpu_ttm_tt_pde_flags already handle this? 1165 */ 1166 if (gc_ip_version == IP_VERSION(9, 4, 2) && 1167 adev->gmc.xgmi.connected_to_cpu) 1168 snoop = true; 1169 } else { 1170 if (uncached || coherent) 1171 mtype = MTYPE_UC; 1172 else 1173 mtype = MTYPE_NC; 1174 if (mapping->bo_va->is_xgmi) 1175 snoop = true; 1176 } 1177 } else { 1178 if (uncached || coherent) 1179 mtype = MTYPE_UC; 1180 else 1181 mtype = MTYPE_NC; 1182 /* FIXME: is this still needed? Or does 1183 * amdgpu_ttm_tt_pde_flags already handle this? 1184 */ 1185 snoop = true; 1186 } 1187 break; 1188 case IP_VERSION(9, 4, 3): 1189 case IP_VERSION(9, 4, 4): 1190 case IP_VERSION(9, 5, 0): 1191 /* Only local VRAM BOs or system memory on non-NUMA APUs 1192 * can be assumed to be local in their entirety. Choose 1193 * MTYPE_NC as safe fallback for all system memory BOs on 1194 * NUMA systems. Their MTYPE can be overridden per-page in 1195 * gmc_v9_0_override_vm_pte_flags. 1196 */ 1197 mtype_local = MTYPE_RW; 1198 if (amdgpu_mtype_local == 1) { 1199 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1200 mtype_local = MTYPE_NC; 1201 } else if (amdgpu_mtype_local == 2) { 1202 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1203 mtype_local = MTYPE_CC; 1204 } else { 1205 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1206 } 1207 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1208 num_possible_nodes() <= 1) || 1209 (is_vram && adev == bo_adev && 1210 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1211 snoop = true; 1212 if (uncached) { 1213 mtype = MTYPE_UC; 1214 } else if (ext_coherent) { 1215 if (gc_ip_version == IP_VERSION(9, 5, 0) || adev->rev_id) 1216 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1217 else 1218 mtype = MTYPE_UC; 1219 } else if (adev->flags & AMD_IS_APU) { 1220 mtype = is_local ? mtype_local : MTYPE_NC; 1221 } else { 1222 /* dGPU */ 1223 if (is_local) 1224 mtype = mtype_local; 1225 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram) 1226 mtype = MTYPE_UC; 1227 else 1228 mtype = MTYPE_NC; 1229 } 1230 1231 break; 1232 default: 1233 if (uncached || coherent) 1234 mtype = MTYPE_UC; 1235 else 1236 mtype = MTYPE_NC; 1237 1238 /* FIXME: is this still needed? Or does 1239 * amdgpu_ttm_tt_pde_flags already handle this? 1240 */ 1241 if (!is_vram) 1242 snoop = true; 1243 } 1244 1245 if (mtype != MTYPE_NC) 1246 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1247 1248 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1249 } 1250 1251 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1252 struct amdgpu_bo_va_mapping *mapping, 1253 uint64_t *flags) 1254 { 1255 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1256 1257 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1258 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1259 1260 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1261 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1262 1263 if (mapping->flags & AMDGPU_PTE_PRT) { 1264 *flags |= AMDGPU_PTE_PRT; 1265 *flags &= ~AMDGPU_PTE_VALID; 1266 } 1267 1268 if ((*flags & AMDGPU_PTE_VALID) && bo) 1269 gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags); 1270 } 1271 1272 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1273 struct amdgpu_vm *vm, 1274 uint64_t addr, uint64_t *flags) 1275 { 1276 int local_node, nid; 1277 1278 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1279 * memory can use more efficient MTYPEs. 1280 */ 1281 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) && 1282 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) && 1283 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 5, 0)) 1284 return; 1285 1286 /* Only direct-mapped memory allows us to determine the NUMA node from 1287 * the DMA address. 1288 */ 1289 if (!adev->ram_is_direct_mapped) { 1290 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1291 return; 1292 } 1293 1294 /* MTYPE_NC is the same default and can be overridden. 1295 * MTYPE_UC will be present if the memory is extended-coherent 1296 * and can also be overridden. 1297 */ 1298 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1299 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1300 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1301 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1302 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1303 return; 1304 } 1305 1306 /* FIXME: Only supported on native mode for now. For carve-out, the 1307 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1308 * memory partitions are not associated with different NUMA nodes. 1309 */ 1310 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1311 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1312 } else { 1313 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1314 return; 1315 } 1316 1317 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1318 * page or NUMA nodes. 1319 */ 1320 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1321 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1322 return; 1323 } 1324 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1325 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1326 vm->mem_id, local_node, nid); 1327 if (nid == local_node) { 1328 uint64_t old_flags = *flags; 1329 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1330 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1331 unsigned int mtype_local = MTYPE_RW; 1332 1333 if (amdgpu_mtype_local == 1) 1334 mtype_local = MTYPE_NC; 1335 else if (amdgpu_mtype_local == 2) 1336 mtype_local = MTYPE_CC; 1337 1338 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1339 } else if (adev->rev_id) { 1340 /* MTYPE_UC case */ 1341 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1342 } 1343 1344 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1345 old_flags, *flags); 1346 } 1347 } 1348 1349 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1350 { 1351 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1352 unsigned int size; 1353 1354 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1355 1356 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1357 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1358 } else { 1359 u32 viewport; 1360 1361 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1362 case IP_VERSION(1, 0, 0): 1363 case IP_VERSION(1, 0, 1): 1364 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1365 size = (REG_GET_FIELD(viewport, 1366 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1367 REG_GET_FIELD(viewport, 1368 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1369 4); 1370 break; 1371 case IP_VERSION(2, 1, 0): 1372 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1373 size = (REG_GET_FIELD(viewport, 1374 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1375 REG_GET_FIELD(viewport, 1376 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1377 4); 1378 break; 1379 default: 1380 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1381 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1382 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1383 4); 1384 break; 1385 } 1386 } 1387 1388 return size; 1389 } 1390 1391 static enum amdgpu_memory_partition 1392 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1393 { 1394 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1395 1396 if (adev->nbio.funcs->get_memory_partition_mode) 1397 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1398 supp_modes); 1399 1400 return mode; 1401 } 1402 1403 static enum amdgpu_memory_partition 1404 gmc_v9_0_query_vf_memory_partition(struct amdgpu_device *adev) 1405 { 1406 switch (adev->gmc.num_mem_partitions) { 1407 case 0: 1408 return UNKNOWN_MEMORY_PARTITION_MODE; 1409 case 1: 1410 return AMDGPU_NPS1_PARTITION_MODE; 1411 case 2: 1412 return AMDGPU_NPS2_PARTITION_MODE; 1413 case 4: 1414 return AMDGPU_NPS4_PARTITION_MODE; 1415 default: 1416 return AMDGPU_NPS1_PARTITION_MODE; 1417 } 1418 1419 return AMDGPU_NPS1_PARTITION_MODE; 1420 } 1421 1422 static enum amdgpu_memory_partition 1423 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1424 { 1425 if (amdgpu_sriov_vf(adev)) 1426 return gmc_v9_0_query_vf_memory_partition(adev); 1427 1428 return gmc_v9_0_get_memory_partition(adev, NULL); 1429 } 1430 1431 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) 1432 { 1433 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && 1434 adev->nbio.funcs->is_nps_switch_requested(adev)) { 1435 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; 1436 return true; 1437 } 1438 1439 return false; 1440 } 1441 1442 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1443 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1444 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1445 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1446 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1447 .map_mtype = gmc_v9_0_map_mtype, 1448 .get_vm_pde = gmc_v9_0_get_vm_pde, 1449 .get_vm_pte = gmc_v9_0_get_vm_pte, 1450 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1451 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1452 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1453 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, 1454 .need_reset_on_init = &gmc_v9_0_need_reset_on_init, 1455 }; 1456 1457 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1458 { 1459 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1460 } 1461 1462 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1463 { 1464 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1465 case IP_VERSION(6, 0, 0): 1466 adev->umc.funcs = &umc_v6_0_funcs; 1467 break; 1468 case IP_VERSION(6, 1, 1): 1469 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1470 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1471 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1472 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1473 adev->umc.retire_unit = 1; 1474 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1475 adev->umc.ras = &umc_v6_1_ras; 1476 break; 1477 case IP_VERSION(6, 1, 2): 1478 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1479 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1480 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1481 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1482 adev->umc.retire_unit = 1; 1483 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1484 adev->umc.ras = &umc_v6_1_ras; 1485 break; 1486 case IP_VERSION(6, 7, 0): 1487 adev->umc.max_ras_err_cnt_per_query = 1488 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1489 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1490 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1491 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1492 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1493 if (!adev->gmc.xgmi.connected_to_cpu) 1494 adev->umc.ras = &umc_v6_7_ras; 1495 if (1 & adev->smuio.funcs->get_die_id(adev)) 1496 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1497 else 1498 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1499 break; 1500 case IP_VERSION(12, 0, 0): 1501 adev->umc.max_ras_err_cnt_per_query = 1502 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1503 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1504 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1505 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1506 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1507 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1508 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1509 adev->umc.ras = &umc_v12_0_ras; 1510 break; 1511 default: 1512 break; 1513 } 1514 } 1515 1516 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1517 { 1518 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1519 case IP_VERSION(9, 4, 1): 1520 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1521 break; 1522 case IP_VERSION(9, 4, 2): 1523 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1524 break; 1525 case IP_VERSION(1, 8, 0): 1526 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1527 break; 1528 default: 1529 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1530 break; 1531 } 1532 } 1533 1534 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1535 { 1536 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1537 case IP_VERSION(9, 4, 0): 1538 adev->mmhub.ras = &mmhub_v1_0_ras; 1539 break; 1540 case IP_VERSION(9, 4, 1): 1541 adev->mmhub.ras = &mmhub_v9_4_ras; 1542 break; 1543 case IP_VERSION(9, 4, 2): 1544 adev->mmhub.ras = &mmhub_v1_7_ras; 1545 break; 1546 case IP_VERSION(1, 8, 0): 1547 case IP_VERSION(1, 8, 1): 1548 adev->mmhub.ras = &mmhub_v1_8_ras; 1549 break; 1550 default: 1551 /* mmhub ras is not available */ 1552 break; 1553 } 1554 } 1555 1556 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1557 { 1558 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1559 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1560 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1561 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1562 else 1563 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1564 } 1565 1566 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1567 { 1568 adev->hdp.ras = &hdp_v4_0_ras; 1569 } 1570 1571 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1572 { 1573 struct amdgpu_mca *mca = &adev->mca; 1574 1575 /* is UMC the right IP to check for MCA? Maybe DF? */ 1576 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1577 case IP_VERSION(6, 7, 0): 1578 if (!adev->gmc.xgmi.connected_to_cpu) { 1579 mca->mp0.ras = &mca_v3_0_mp0_ras; 1580 mca->mp1.ras = &mca_v3_0_mp1_ras; 1581 mca->mpio.ras = &mca_v3_0_mpio_ras; 1582 } 1583 break; 1584 default: 1585 break; 1586 } 1587 } 1588 1589 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1590 { 1591 if (!adev->gmc.xgmi.connected_to_cpu) 1592 adev->gmc.xgmi.ras = &xgmi_ras; 1593 } 1594 1595 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) 1596 { 1597 adev->gmc.supported_nps_modes = 0; 1598 1599 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 1600 return; 1601 1602 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep 1603 * supported modes as 0. 1604 */ 1605 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1606 case IP_VERSION(9, 4, 3): 1607 case IP_VERSION(9, 4, 4): 1608 adev->gmc.supported_nps_modes = 1609 BIT(AMDGPU_NPS1_PARTITION_MODE) | 1610 BIT(AMDGPU_NPS4_PARTITION_MODE); 1611 break; 1612 default: 1613 break; 1614 } 1615 } 1616 1617 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) 1618 { 1619 struct amdgpu_device *adev = ip_block->adev; 1620 1621 /* 1622 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1623 * in their IP discovery tables 1624 */ 1625 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1626 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1627 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1628 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1629 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1630 adev->gmc.xgmi.supported = true; 1631 1632 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1633 adev->gmc.xgmi.supported = true; 1634 adev->gmc.xgmi.connected_to_cpu = 1635 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1636 } 1637 1638 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1639 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 1640 enum amdgpu_pkg_type pkg_type = 1641 adev->smuio.funcs->get_pkg_type(adev); 1642 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1643 * and the APU, can be in used two possible modes: 1644 * - carveout mode 1645 * - native APU mode 1646 * "is_app_apu" can be used to identify the APU in the native 1647 * mode. 1648 */ 1649 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1650 !pci_resource_len(adev->pdev, 0)); 1651 } 1652 1653 gmc_v9_0_set_gmc_funcs(adev); 1654 gmc_v9_0_set_irq_funcs(adev); 1655 gmc_v9_0_set_umc_funcs(adev); 1656 gmc_v9_0_set_mmhub_funcs(adev); 1657 gmc_v9_0_set_mmhub_ras_funcs(adev); 1658 gmc_v9_0_set_gfxhub_funcs(adev); 1659 gmc_v9_0_set_hdp_ras_funcs(adev); 1660 gmc_v9_0_set_mca_ras_funcs(adev); 1661 gmc_v9_0_set_xgmi_ras_funcs(adev); 1662 1663 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1664 adev->gmc.shared_aperture_end = 1665 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1666 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1667 adev->gmc.private_aperture_end = 1668 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1669 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1670 1671 return 0; 1672 } 1673 1674 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) 1675 { 1676 struct amdgpu_device *adev = ip_block->adev; 1677 int r; 1678 1679 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1680 if (r) 1681 return r; 1682 1683 /* 1684 * Workaround performance drop issue with VBIOS enables partial 1685 * writes, while disables HBM ECC for vega10. 1686 */ 1687 if (!amdgpu_sriov_vf(adev) && 1688 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1689 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1690 if (adev->df.funcs && 1691 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1692 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1693 } 1694 } 1695 1696 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1697 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1698 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1699 } 1700 1701 r = amdgpu_gmc_ras_late_init(adev); 1702 if (r) 1703 return r; 1704 1705 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1706 } 1707 1708 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1709 struct amdgpu_gmc *mc) 1710 { 1711 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1712 1713 amdgpu_gmc_set_agp_default(adev, mc); 1714 1715 /* add the xgmi offset of the physical node */ 1716 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1717 if (adev->gmc.xgmi.connected_to_cpu) { 1718 amdgpu_gmc_sysvm_location(adev, mc); 1719 } else { 1720 amdgpu_gmc_vram_location(adev, mc, base); 1721 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1722 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1723 amdgpu_gmc_agp_location(adev, mc); 1724 } 1725 /* base offset of vram pages */ 1726 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1727 1728 /* XXX: add the xgmi offset of the physical node? */ 1729 adev->vm_manager.vram_base_offset += 1730 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1731 } 1732 1733 /** 1734 * gmc_v9_0_mc_init - initialize the memory controller driver params 1735 * 1736 * @adev: amdgpu_device pointer 1737 * 1738 * Look up the amount of vram, vram width, and decide how to place 1739 * vram and gart within the GPU's physical address space. 1740 * Returns 0 for success. 1741 */ 1742 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1743 { 1744 int r; 1745 1746 /* size in MB on si */ 1747 if (!adev->gmc.is_app_apu) { 1748 adev->gmc.mc_vram_size = 1749 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1750 } else { 1751 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1752 adev->gmc.mc_vram_size = 0; 1753 } 1754 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1755 1756 if (!(adev->flags & AMD_IS_APU) && 1757 !adev->gmc.xgmi.connected_to_cpu) { 1758 r = amdgpu_device_resize_fb_bar(adev); 1759 if (r) 1760 return r; 1761 } 1762 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1763 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1764 1765 #ifdef CONFIG_X86_64 1766 /* 1767 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1768 * interface can use VRAM through here as it appears system reserved 1769 * memory in host address space. 1770 * 1771 * For APUs, VRAM is just the stolen system memory and can be accessed 1772 * directly. 1773 * 1774 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1775 */ 1776 1777 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1778 if ((!amdgpu_sriov_vf(adev) && 1779 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1780 (adev->gmc.xgmi.supported && 1781 adev->gmc.xgmi.connected_to_cpu)) { 1782 adev->gmc.aper_base = 1783 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1784 adev->gmc.xgmi.physical_node_id * 1785 adev->gmc.xgmi.node_segment_size; 1786 adev->gmc.aper_size = adev->gmc.real_vram_size; 1787 } 1788 1789 #endif 1790 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1791 1792 /* set the gart size */ 1793 if (amdgpu_gart_size == -1) { 1794 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1795 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1796 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1797 case IP_VERSION(9, 4, 0): 1798 case IP_VERSION(9, 4, 1): 1799 case IP_VERSION(9, 4, 2): 1800 case IP_VERSION(9, 4, 3): 1801 case IP_VERSION(9, 4, 4): 1802 case IP_VERSION(9, 5, 0): 1803 default: 1804 adev->gmc.gart_size = 512ULL << 20; 1805 break; 1806 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1807 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1808 case IP_VERSION(9, 3, 0): 1809 adev->gmc.gart_size = 1024ULL << 20; 1810 break; 1811 } 1812 } else { 1813 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1814 } 1815 1816 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1817 1818 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1819 1820 return 0; 1821 } 1822 1823 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1824 { 1825 int r; 1826 1827 if (adev->gart.bo) { 1828 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1829 return 0; 1830 } 1831 1832 if (adev->gmc.xgmi.connected_to_cpu) { 1833 adev->gmc.vmid0_page_table_depth = 1; 1834 adev->gmc.vmid0_page_table_block_size = 12; 1835 } else { 1836 adev->gmc.vmid0_page_table_depth = 0; 1837 adev->gmc.vmid0_page_table_block_size = 0; 1838 } 1839 1840 /* Initialize common gart structure */ 1841 r = amdgpu_gart_init(adev); 1842 if (r) 1843 return r; 1844 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1845 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1846 AMDGPU_PTE_EXECUTABLE; 1847 1848 if (!adev->gmc.real_vram_size) { 1849 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1850 r = amdgpu_gart_table_ram_alloc(adev); 1851 if (r) 1852 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1853 } else { 1854 r = amdgpu_gart_table_vram_alloc(adev); 1855 if (r) 1856 return r; 1857 1858 if (adev->gmc.xgmi.connected_to_cpu) 1859 r = amdgpu_gmc_pdb0_alloc(adev); 1860 } 1861 1862 return r; 1863 } 1864 1865 /** 1866 * gmc_v9_0_save_registers - saves regs 1867 * 1868 * @adev: amdgpu_device pointer 1869 * 1870 * This saves potential register values that should be 1871 * restored upon resume 1872 */ 1873 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1874 { 1875 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1876 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1877 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1878 } 1879 1880 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1881 { 1882 enum amdgpu_memory_partition mode; 1883 u32 supp_modes; 1884 bool valid; 1885 1886 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1887 1888 /* Mode detected by hardware not present in supported modes */ 1889 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1890 !(BIT(mode - 1) & supp_modes)) 1891 return false; 1892 1893 switch (mode) { 1894 case UNKNOWN_MEMORY_PARTITION_MODE: 1895 case AMDGPU_NPS1_PARTITION_MODE: 1896 valid = (adev->gmc.num_mem_partitions == 1); 1897 break; 1898 case AMDGPU_NPS2_PARTITION_MODE: 1899 valid = (adev->gmc.num_mem_partitions == 2); 1900 break; 1901 case AMDGPU_NPS4_PARTITION_MODE: 1902 valid = (adev->gmc.num_mem_partitions == 3 || 1903 adev->gmc.num_mem_partitions == 4); 1904 break; 1905 default: 1906 valid = false; 1907 } 1908 1909 return valid; 1910 } 1911 1912 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1913 { 1914 int i; 1915 1916 /* Check if node with id 'nid' is present in 'node_ids' array */ 1917 for (i = 0; i < num_ids; ++i) 1918 if (node_ids[i] == nid) 1919 return true; 1920 1921 return false; 1922 } 1923 1924 static void 1925 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1926 struct amdgpu_mem_partition_info *mem_ranges) 1927 { 1928 struct amdgpu_numa_info numa_info; 1929 int node_ids[MAX_MEM_RANGES]; 1930 int num_ranges = 0, ret; 1931 int num_xcc, xcc_id; 1932 uint32_t xcc_mask; 1933 1934 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1935 xcc_mask = (1U << num_xcc) - 1; 1936 1937 for_each_inst(xcc_id, xcc_mask) { 1938 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1939 if (ret) 1940 continue; 1941 1942 if (numa_info.nid == NUMA_NO_NODE) { 1943 mem_ranges[0].size = numa_info.size; 1944 mem_ranges[0].numa.node = numa_info.nid; 1945 num_ranges = 1; 1946 break; 1947 } 1948 1949 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1950 numa_info.nid)) 1951 continue; 1952 1953 node_ids[num_ranges] = numa_info.nid; 1954 mem_ranges[num_ranges].numa.node = numa_info.nid; 1955 mem_ranges[num_ranges].size = numa_info.size; 1956 ++num_ranges; 1957 } 1958 1959 adev->gmc.num_mem_partitions = num_ranges; 1960 } 1961 1962 static void 1963 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1964 struct amdgpu_mem_partition_info *mem_ranges) 1965 { 1966 enum amdgpu_memory_partition mode; 1967 u32 start_addr = 0, size; 1968 int i, r, l; 1969 1970 mode = gmc_v9_0_query_memory_partition(adev); 1971 1972 switch (mode) { 1973 case UNKNOWN_MEMORY_PARTITION_MODE: 1974 adev->gmc.num_mem_partitions = 0; 1975 break; 1976 case AMDGPU_NPS1_PARTITION_MODE: 1977 adev->gmc.num_mem_partitions = 1; 1978 break; 1979 case AMDGPU_NPS2_PARTITION_MODE: 1980 adev->gmc.num_mem_partitions = 2; 1981 break; 1982 case AMDGPU_NPS4_PARTITION_MODE: 1983 if (adev->flags & AMD_IS_APU) 1984 adev->gmc.num_mem_partitions = 3; 1985 else 1986 adev->gmc.num_mem_partitions = 4; 1987 break; 1988 default: 1989 adev->gmc.num_mem_partitions = 1; 1990 break; 1991 } 1992 1993 /* Use NPS range info, if populated */ 1994 r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, 1995 &adev->gmc.num_mem_partitions); 1996 if (!r) { 1997 l = 0; 1998 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { 1999 if (mem_ranges[i].range.lpfn > 2000 mem_ranges[i - 1].range.lpfn) 2001 l = i; 2002 } 2003 2004 } else { 2005 if (!adev->gmc.num_mem_partitions) { 2006 dev_err(adev->dev, 2007 "Not able to detect NPS mode, fall back to NPS1"); 2008 adev->gmc.num_mem_partitions = 1; 2009 } 2010 /* Fallback to sw based calculation */ 2011 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 2012 size /= adev->gmc.num_mem_partitions; 2013 2014 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 2015 mem_ranges[i].range.fpfn = start_addr; 2016 mem_ranges[i].size = 2017 ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 2018 mem_ranges[i].range.lpfn = start_addr + size - 1; 2019 start_addr += size; 2020 } 2021 2022 l = adev->gmc.num_mem_partitions - 1; 2023 } 2024 2025 /* Adjust the last one */ 2026 mem_ranges[l].range.lpfn = 2027 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 2028 mem_ranges[l].size = 2029 adev->gmc.real_vram_size - 2030 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT); 2031 } 2032 2033 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 2034 { 2035 bool valid; 2036 2037 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 2038 sizeof(struct amdgpu_mem_partition_info), 2039 GFP_KERNEL); 2040 if (!adev->gmc.mem_partitions) 2041 return -ENOMEM; 2042 2043 /* TODO : Get the range from PSP/Discovery for dGPU */ 2044 if (adev->gmc.is_app_apu) 2045 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 2046 else 2047 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2048 2049 if (amdgpu_sriov_vf(adev)) 2050 valid = true; 2051 else 2052 valid = gmc_v9_0_validate_partition_info(adev); 2053 if (!valid) { 2054 /* TODO: handle invalid case */ 2055 dev_WARN(adev->dev, 2056 "Mem ranges not matching with hardware config"); 2057 } 2058 2059 return 0; 2060 } 2061 2062 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 2063 { 2064 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2065 adev->gmc.vram_width = 128 * 64; 2066 } 2067 2068 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) 2069 { 2070 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 2071 struct amdgpu_device *adev = ip_block->adev; 2072 unsigned long inst_mask = adev->aid_mask; 2073 2074 adev->gfxhub.funcs->init(adev); 2075 2076 adev->mmhub.funcs->init(adev); 2077 2078 spin_lock_init(&adev->gmc.invalidate_lock); 2079 2080 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2081 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2082 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 2083 gmc_v9_4_3_init_vram_info(adev); 2084 } else if (!adev->bios) { 2085 if (adev->flags & AMD_IS_APU) { 2086 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 2087 adev->gmc.vram_width = 64 * 64; 2088 } else { 2089 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2090 adev->gmc.vram_width = 128 * 64; 2091 } 2092 } else { 2093 r = amdgpu_atomfirmware_get_vram_info(adev, 2094 &vram_width, &vram_type, &vram_vendor); 2095 if (amdgpu_sriov_vf(adev)) 2096 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2097 * and DF related registers is not readable, seems hardcord is the 2098 * only way to set the correct vram_width 2099 */ 2100 adev->gmc.vram_width = 2048; 2101 else if (amdgpu_emu_mode != 1) 2102 adev->gmc.vram_width = vram_width; 2103 2104 if (!adev->gmc.vram_width) { 2105 int chansize, numchan; 2106 2107 /* hbm memory channel size */ 2108 if (adev->flags & AMD_IS_APU) 2109 chansize = 64; 2110 else 2111 chansize = 128; 2112 if (adev->df.funcs && 2113 adev->df.funcs->get_hbm_channel_number) { 2114 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2115 adev->gmc.vram_width = numchan * chansize; 2116 } 2117 } 2118 2119 adev->gmc.vram_type = vram_type; 2120 adev->gmc.vram_vendor = vram_vendor; 2121 } 2122 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2123 case IP_VERSION(9, 1, 0): 2124 case IP_VERSION(9, 2, 2): 2125 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2126 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2127 2128 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2129 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2130 } else { 2131 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2132 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2133 adev->gmc.translate_further = 2134 adev->vm_manager.num_level > 1; 2135 } 2136 break; 2137 case IP_VERSION(9, 0, 1): 2138 case IP_VERSION(9, 2, 1): 2139 case IP_VERSION(9, 4, 0): 2140 case IP_VERSION(9, 3, 0): 2141 case IP_VERSION(9, 4, 2): 2142 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2143 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2144 2145 /* 2146 * To fulfill 4-level page support, 2147 * vm size is 256TB (48bit), maximum size of Vega10, 2148 * block size 512 (9bit) 2149 */ 2150 2151 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2152 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2153 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2154 break; 2155 case IP_VERSION(9, 4, 1): 2156 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2157 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2158 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2159 2160 /* Keep the vm size same with Vega20 */ 2161 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2162 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2163 break; 2164 case IP_VERSION(9, 4, 3): 2165 case IP_VERSION(9, 4, 4): 2166 case IP_VERSION(9, 5, 0): 2167 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2168 NUM_XCC(adev->gfx.xcc_mask)); 2169 2170 inst_mask <<= AMDGPU_MMHUB0(0); 2171 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2172 2173 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2174 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2175 break; 2176 default: 2177 break; 2178 } 2179 2180 /* This interrupt is VMC page fault.*/ 2181 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2182 &adev->gmc.vm_fault); 2183 if (r) 2184 return r; 2185 2186 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2187 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2188 &adev->gmc.vm_fault); 2189 if (r) 2190 return r; 2191 } 2192 2193 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2194 &adev->gmc.vm_fault); 2195 2196 if (r) 2197 return r; 2198 2199 if (!amdgpu_sriov_vf(adev) && 2200 !adev->gmc.xgmi.connected_to_cpu && 2201 !adev->gmc.is_app_apu) { 2202 /* interrupt sent to DF. */ 2203 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2204 &adev->gmc.ecc_irq); 2205 if (r) 2206 return r; 2207 } 2208 2209 /* Set the internal MC address mask 2210 * This is the max address of the GPU's 2211 * internal address space. 2212 */ 2213 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2214 2215 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2216 IP_VERSION(9, 4, 2) ? 2217 48 : 2218 44; 2219 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2220 if (r) { 2221 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2222 return r; 2223 } 2224 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2225 2226 r = gmc_v9_0_mc_init(adev); 2227 if (r) 2228 return r; 2229 2230 amdgpu_gmc_get_vbios_allocations(adev); 2231 2232 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2233 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2234 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 2235 r = gmc_v9_0_init_mem_ranges(adev); 2236 if (r) 2237 return r; 2238 } 2239 2240 /* Memory manager */ 2241 r = amdgpu_bo_init(adev); 2242 if (r) 2243 return r; 2244 2245 r = gmc_v9_0_gart_init(adev); 2246 if (r) 2247 return r; 2248 2249 gmc_v9_0_init_nps_details(adev); 2250 /* 2251 * number of VMs 2252 * VMID 0 is reserved for System 2253 * amdgpu graphics/compute will use VMIDs 1..n-1 2254 * amdkfd will use VMIDs n..15 2255 * 2256 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2257 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2258 * for video processing. 2259 */ 2260 adev->vm_manager.first_kfd_vmid = 2261 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2262 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2263 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2264 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2265 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) ? 2266 3 : 2267 8; 2268 2269 amdgpu_vm_manager_init(adev); 2270 2271 gmc_v9_0_save_registers(adev); 2272 2273 r = amdgpu_gmc_ras_sw_init(adev); 2274 if (r) 2275 return r; 2276 2277 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2278 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2279 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 2280 amdgpu_gmc_sysfs_init(adev); 2281 2282 return 0; 2283 } 2284 2285 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) 2286 { 2287 struct amdgpu_device *adev = ip_block->adev; 2288 2289 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2290 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2291 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 2292 amdgpu_gmc_sysfs_fini(adev); 2293 2294 amdgpu_gmc_ras_fini(adev); 2295 amdgpu_gem_force_release(adev); 2296 amdgpu_vm_manager_fini(adev); 2297 if (!adev->gmc.real_vram_size) { 2298 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2299 amdgpu_gart_table_ram_free(adev); 2300 } else { 2301 amdgpu_gart_table_vram_free(adev); 2302 } 2303 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2304 amdgpu_bo_fini(adev); 2305 2306 adev->gmc.num_mem_partitions = 0; 2307 kfree(adev->gmc.mem_partitions); 2308 2309 return 0; 2310 } 2311 2312 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2313 { 2314 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2315 case IP_VERSION(9, 0, 0): 2316 if (amdgpu_sriov_vf(adev)) 2317 break; 2318 fallthrough; 2319 case IP_VERSION(9, 4, 0): 2320 soc15_program_register_sequence(adev, 2321 golden_settings_mmhub_1_0_0, 2322 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2323 soc15_program_register_sequence(adev, 2324 golden_settings_athub_1_0_0, 2325 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2326 break; 2327 case IP_VERSION(9, 1, 0): 2328 case IP_VERSION(9, 2, 0): 2329 /* TODO for renoir */ 2330 soc15_program_register_sequence(adev, 2331 golden_settings_athub_1_0_0, 2332 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2333 break; 2334 default: 2335 break; 2336 } 2337 } 2338 2339 /** 2340 * gmc_v9_0_restore_registers - restores regs 2341 * 2342 * @adev: amdgpu_device pointer 2343 * 2344 * This restores register values, saved at suspend. 2345 */ 2346 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2347 { 2348 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2349 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2350 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2351 WARN_ON(adev->gmc.sdpif_register != 2352 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2353 } 2354 } 2355 2356 /** 2357 * gmc_v9_0_gart_enable - gart enable 2358 * 2359 * @adev: amdgpu_device pointer 2360 */ 2361 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2362 { 2363 int r; 2364 2365 if (adev->gmc.xgmi.connected_to_cpu) 2366 amdgpu_gmc_init_pdb0(adev); 2367 2368 if (adev->gart.bo == NULL) { 2369 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2370 return -EINVAL; 2371 } 2372 2373 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2374 2375 if (!adev->in_s0ix) { 2376 r = adev->gfxhub.funcs->gart_enable(adev); 2377 if (r) 2378 return r; 2379 } 2380 2381 r = adev->mmhub.funcs->gart_enable(adev); 2382 if (r) 2383 return r; 2384 2385 DRM_INFO("PCIE GART of %uM enabled.\n", 2386 (unsigned int)(adev->gmc.gart_size >> 20)); 2387 if (adev->gmc.pdb0_bo) 2388 DRM_INFO("PDB0 located at 0x%016llX\n", 2389 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2390 DRM_INFO("PTB located at 0x%016llX\n", 2391 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2392 2393 return 0; 2394 } 2395 2396 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) 2397 { 2398 struct amdgpu_device *adev = ip_block->adev; 2399 bool value; 2400 int i, r; 2401 2402 adev->gmc.flush_pasid_uses_kiq = true; 2403 2404 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2405 * (type 2), which flushes both. Due to a race condition with 2406 * concurrent memory accesses using the same TLB cache line, we still 2407 * need a second TLB flush after this. 2408 */ 2409 adev->gmc.flush_tlb_needs_extra_type_2 = 2410 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2411 adev->gmc.xgmi.num_physical_nodes; 2412 /* 2413 * TODO: This workaround is badly documented and had a buggy 2414 * implementation. We should probably verify what we do here. 2415 */ 2416 adev->gmc.flush_tlb_needs_extra_type_0 = 2417 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 2418 adev->rev_id == 0; 2419 2420 /* The sequence of these two function calls matters.*/ 2421 gmc_v9_0_init_golden_registers(adev); 2422 2423 if (adev->mode_info.num_crtc) { 2424 /* Lockout access through VGA aperture*/ 2425 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2426 /* disable VGA render */ 2427 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2428 } 2429 2430 if (adev->mmhub.funcs->update_power_gating) 2431 adev->mmhub.funcs->update_power_gating(adev, true); 2432 2433 adev->hdp.funcs->init_registers(adev); 2434 2435 /* After HDP is initialized, flush HDP.*/ 2436 adev->hdp.funcs->flush_hdp(adev, NULL); 2437 2438 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2439 value = false; 2440 else 2441 value = true; 2442 2443 if (!amdgpu_sriov_vf(adev)) { 2444 if (!adev->in_s0ix) 2445 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2446 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2447 } 2448 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2449 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2450 continue; 2451 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2452 } 2453 2454 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2455 adev->umc.funcs->init_registers(adev); 2456 2457 r = gmc_v9_0_gart_enable(adev); 2458 if (r) 2459 return r; 2460 2461 if (amdgpu_emu_mode == 1) 2462 return amdgpu_gmc_vram_checking(adev); 2463 2464 return 0; 2465 } 2466 2467 /** 2468 * gmc_v9_0_gart_disable - gart disable 2469 * 2470 * @adev: amdgpu_device pointer 2471 * 2472 * This disables all VM page table. 2473 */ 2474 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2475 { 2476 if (!adev->in_s0ix) 2477 adev->gfxhub.funcs->gart_disable(adev); 2478 adev->mmhub.funcs->gart_disable(adev); 2479 } 2480 2481 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) 2482 { 2483 struct amdgpu_device *adev = ip_block->adev; 2484 2485 gmc_v9_0_gart_disable(adev); 2486 2487 if (amdgpu_sriov_vf(adev)) { 2488 /* full access mode, so don't touch any GMC register */ 2489 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2490 return 0; 2491 } 2492 2493 /* 2494 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2495 * a correct cached state for GMC. Otherwise, the "gate" again 2496 * operation on S3 resuming will fail due to wrong cached state. 2497 */ 2498 if (adev->mmhub.funcs->update_power_gating) 2499 adev->mmhub.funcs->update_power_gating(adev, false); 2500 2501 /* 2502 * For minimal init, late_init is not called, hence VM fault/RAS irqs 2503 * are not enabled. 2504 */ 2505 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { 2506 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2507 2508 if (adev->gmc.ecc_irq.funcs && 2509 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2510 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2511 } 2512 2513 return 0; 2514 } 2515 2516 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) 2517 { 2518 return gmc_v9_0_hw_fini(ip_block); 2519 } 2520 2521 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) 2522 { 2523 struct amdgpu_device *adev = ip_block->adev; 2524 int r; 2525 2526 /* If a reset is done for NPS mode switch, read the memory range 2527 * information again. 2528 */ 2529 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { 2530 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2531 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; 2532 } 2533 2534 r = gmc_v9_0_hw_init(ip_block); 2535 if (r) 2536 return r; 2537 2538 amdgpu_vmid_reset_all(ip_block->adev); 2539 2540 return 0; 2541 } 2542 2543 static bool gmc_v9_0_is_idle(void *handle) 2544 { 2545 /* MC is always ready in GMC v9.*/ 2546 return true; 2547 } 2548 2549 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2550 { 2551 /* There is no need to wait for MC idle in GMC v9.*/ 2552 return 0; 2553 } 2554 2555 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) 2556 { 2557 /* XXX for emulation.*/ 2558 return 0; 2559 } 2560 2561 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2562 enum amd_clockgating_state state) 2563 { 2564 struct amdgpu_device *adev = ip_block->adev; 2565 2566 adev->mmhub.funcs->set_clockgating(adev, state); 2567 2568 athub_v1_0_set_clockgating(adev, state); 2569 2570 return 0; 2571 } 2572 2573 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2574 { 2575 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2576 2577 adev->mmhub.funcs->get_clockgating(adev, flags); 2578 2579 athub_v1_0_get_clockgating(adev, flags); 2580 } 2581 2582 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2583 enum amd_powergating_state state) 2584 { 2585 return 0; 2586 } 2587 2588 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2589 .name = "gmc_v9_0", 2590 .early_init = gmc_v9_0_early_init, 2591 .late_init = gmc_v9_0_late_init, 2592 .sw_init = gmc_v9_0_sw_init, 2593 .sw_fini = gmc_v9_0_sw_fini, 2594 .hw_init = gmc_v9_0_hw_init, 2595 .hw_fini = gmc_v9_0_hw_fini, 2596 .suspend = gmc_v9_0_suspend, 2597 .resume = gmc_v9_0_resume, 2598 .is_idle = gmc_v9_0_is_idle, 2599 .wait_for_idle = gmc_v9_0_wait_for_idle, 2600 .soft_reset = gmc_v9_0_soft_reset, 2601 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2602 .set_powergating_state = gmc_v9_0_set_powergating_state, 2603 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2604 }; 2605 2606 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2607 .type = AMD_IP_BLOCK_TYPE_GMC, 2608 .major = 9, 2609 .minor = 0, 2610 .rev = 0, 2611 .funcs = &gmc_v9_0_ip_funcs, 2612 }; 2613