1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/gpio/consumer.h> 9 #include <linux/regmap.h> 10 #include <linux/regulator/consumer.h> 11 #include <linux/types.h> 12 13 #include "cs35l56.h" 14 15 static const struct reg_sequence cs35l56_patch[] = { 16 /* 17 * Firmware can change these to non-defaults to satisfy SDCA. 18 * Ensure that they are at known defaults. 19 */ 20 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 21 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 22 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 23 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 24 25 /* These are not reset by a soft-reset, so patch to defaults. */ 26 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 27 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 28 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 29 }; 30 31 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 32 { 33 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 34 ARRAY_SIZE(cs35l56_patch)); 35 } 36 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED); 37 38 static const struct reg_default cs35l56_reg_defaults[] = { 39 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 40 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 41 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 42 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 43 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 44 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 45 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 46 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 47 48 /* no defaults for ASP1TX mixer */ 49 50 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 51 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 52 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 53 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 54 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 55 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 56 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 57 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 58 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 59 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 60 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 61 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 62 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 63 }; 64 65 static bool cs35l56_is_dsp_memory(unsigned int reg) 66 { 67 switch (reg) { 68 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 69 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 70 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 71 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 72 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 73 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 74 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 75 return true; 76 default: 77 return false; 78 } 79 } 80 81 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 82 { 83 switch (reg) { 84 case CS35L56_DEVID: 85 case CS35L56_REVID: 86 case CS35L56_RELID: 87 case CS35L56_OTPID: 88 case CS35L56_SFT_RESET: 89 case CS35L56_GLOBAL_ENABLES: 90 case CS35L56_BLOCK_ENABLES: 91 case CS35L56_BLOCK_ENABLES2: 92 case CS35L56_REFCLK_INPUT: 93 case CS35L56_GLOBAL_SAMPLE_RATE: 94 case CS35L56_ASP1_ENABLES1: 95 case CS35L56_ASP1_CONTROL1: 96 case CS35L56_ASP1_CONTROL2: 97 case CS35L56_ASP1_CONTROL3: 98 case CS35L56_ASP1_FRAME_CONTROL1: 99 case CS35L56_ASP1_FRAME_CONTROL5: 100 case CS35L56_ASP1_DATA_CONTROL1: 101 case CS35L56_ASP1_DATA_CONTROL5: 102 case CS35L56_DACPCM1_INPUT: 103 case CS35L56_DACPCM2_INPUT: 104 case CS35L56_ASP1TX1_INPUT: 105 case CS35L56_ASP1TX2_INPUT: 106 case CS35L56_ASP1TX3_INPUT: 107 case CS35L56_ASP1TX4_INPUT: 108 case CS35L56_DSP1RX1_INPUT: 109 case CS35L56_DSP1RX2_INPUT: 110 case CS35L56_SWIRE_DP3_CH1_INPUT: 111 case CS35L56_SWIRE_DP3_CH2_INPUT: 112 case CS35L56_SWIRE_DP3_CH3_INPUT: 113 case CS35L56_SWIRE_DP3_CH4_INPUT: 114 case CS35L56_IRQ1_CFG: 115 case CS35L56_IRQ1_STATUS: 116 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 117 case CS35L56_IRQ1_EINT_18: 118 case CS35L56_IRQ1_EINT_20: 119 case CS35L56_IRQ1_MASK_1: 120 case CS35L56_IRQ1_MASK_2: 121 case CS35L56_IRQ1_MASK_4: 122 case CS35L56_IRQ1_MASK_8: 123 case CS35L56_IRQ1_MASK_18: 124 case CS35L56_IRQ1_MASK_20: 125 case CS35L56_DSP_VIRTUAL1_MBOX_1: 126 case CS35L56_DSP_VIRTUAL1_MBOX_2: 127 case CS35L56_DSP_VIRTUAL1_MBOX_3: 128 case CS35L56_DSP_VIRTUAL1_MBOX_4: 129 case CS35L56_DSP_VIRTUAL1_MBOX_5: 130 case CS35L56_DSP_VIRTUAL1_MBOX_6: 131 case CS35L56_DSP_VIRTUAL1_MBOX_7: 132 case CS35L56_DSP_VIRTUAL1_MBOX_8: 133 case CS35L56_DSP_RESTRICT_STS1: 134 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 135 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 136 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 137 case CS35L56_DSP1_SCRATCH1: 138 case CS35L56_DSP1_SCRATCH2: 139 case CS35L56_DSP1_SCRATCH3: 140 case CS35L56_DSP1_SCRATCH4: 141 return true; 142 default: 143 return cs35l56_is_dsp_memory(reg); 144 } 145 } 146 147 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 148 { 149 switch (reg) { 150 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 151 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 152 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 153 return true; 154 default: 155 return false; 156 } 157 } 158 159 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 160 { 161 switch (reg) { 162 case CS35L56_DEVID: 163 case CS35L56_REVID: 164 case CS35L56_RELID: 165 case CS35L56_OTPID: 166 case CS35L56_SFT_RESET: 167 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 168 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 169 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 170 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 171 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 172 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 173 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 174 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 175 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 176 case CS35L56_IRQ1_STATUS: 177 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 178 case CS35L56_IRQ1_EINT_18: 179 case CS35L56_IRQ1_EINT_20: 180 case CS35L56_DSP_VIRTUAL1_MBOX_1: 181 case CS35L56_DSP_VIRTUAL1_MBOX_2: 182 case CS35L56_DSP_VIRTUAL1_MBOX_3: 183 case CS35L56_DSP_VIRTUAL1_MBOX_4: 184 case CS35L56_DSP_VIRTUAL1_MBOX_5: 185 case CS35L56_DSP_VIRTUAL1_MBOX_6: 186 case CS35L56_DSP_VIRTUAL1_MBOX_7: 187 case CS35L56_DSP_VIRTUAL1_MBOX_8: 188 case CS35L56_DSP_RESTRICT_STS1: 189 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 190 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 191 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 192 case CS35L56_DSP1_SCRATCH1: 193 case CS35L56_DSP1_SCRATCH2: 194 case CS35L56_DSP1_SCRATCH3: 195 case CS35L56_DSP1_SCRATCH4: 196 return true; 197 case CS35L56_MAIN_RENDER_USER_MUTE: 198 case CS35L56_MAIN_RENDER_USER_VOLUME: 199 case CS35L56_MAIN_POSTURE_NUMBER: 200 return false; 201 default: 202 return cs35l56_is_dsp_memory(reg); 203 } 204 } 205 206 /* 207 * The firmware boot sequence can overwrite the ASP1 config registers so that 208 * they don't match regmap's view of their values. Rewrite the values from the 209 * regmap cache into the hardware registers. 210 */ 211 int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base) 212 { 213 struct reg_sequence asp1_regs[] = { 214 { .reg = CS35L56_ASP1_ENABLES1 }, 215 { .reg = CS35L56_ASP1_CONTROL1 }, 216 { .reg = CS35L56_ASP1_CONTROL2 }, 217 { .reg = CS35L56_ASP1_CONTROL3 }, 218 { .reg = CS35L56_ASP1_FRAME_CONTROL1 }, 219 { .reg = CS35L56_ASP1_FRAME_CONTROL5 }, 220 { .reg = CS35L56_ASP1_DATA_CONTROL1 }, 221 { .reg = CS35L56_ASP1_DATA_CONTROL5 }, 222 }; 223 int i, ret; 224 225 /* Read values from regmap cache into a write sequence */ 226 for (i = 0; i < ARRAY_SIZE(asp1_regs); ++i) { 227 ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def); 228 if (ret) 229 goto err; 230 } 231 232 /* Write the values cache-bypassed so that they will be written to silicon */ 233 ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs, 234 ARRAY_SIZE(asp1_regs)); 235 if (ret) 236 goto err; 237 238 return 0; 239 240 err: 241 dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret); 242 243 return ret; 244 } 245 EXPORT_SYMBOL_NS_GPL(cs35l56_force_sync_asp1_registers_from_cache, SND_SOC_CS35L56_SHARED); 246 247 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 248 { 249 unsigned int val; 250 int ret; 251 252 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 253 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 254 val, (val == 0), 255 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 256 if (ret) { 257 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 258 return ret; 259 } 260 261 return 0; 262 } 263 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED); 264 265 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 266 { 267 int ret; 268 unsigned int reg; 269 unsigned int val; 270 271 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 272 if (ret) 273 return ret; 274 275 if (cs35l56_base->rev < CS35L56_REVID_B0) 276 reg = CS35L56_DSP1_PM_CUR_STATE_A1; 277 else 278 reg = CS35L56_DSP1_PM_CUR_STATE; 279 280 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg, 281 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 282 CS35L56_HALO_STATE_POLL_US, 283 CS35L56_HALO_STATE_TIMEOUT_US); 284 if (ret < 0) 285 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 286 val, ret); 287 return ret; 288 } 289 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED); 290 291 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 292 { 293 unsigned int reg; 294 unsigned int val = 0; 295 int read_ret, poll_ret; 296 297 if (cs35l56_base->rev < CS35L56_REVID_B0) 298 reg = CS35L56_DSP1_HALO_STATE_A1; 299 else 300 reg = CS35L56_DSP1_HALO_STATE; 301 302 /* 303 * This can't be a regmap_read_poll_timeout() because cs35l56 will NAK 304 * I2C until it has booted which would terminate the poll 305 */ 306 poll_ret = read_poll_timeout(regmap_read, read_ret, 307 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 308 CS35L56_HALO_STATE_POLL_US, 309 CS35L56_HALO_STATE_TIMEOUT_US, 310 false, 311 cs35l56_base->regmap, reg, &val); 312 313 if (poll_ret) { 314 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 315 read_ret, val); 316 return -EIO; 317 } 318 319 return 0; 320 } 321 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED); 322 323 void cs35l56_wait_control_port_ready(void) 324 { 325 /* Wait for control port to be ready (datasheet tIRS). */ 326 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 327 } 328 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED); 329 330 void cs35l56_wait_min_reset_pulse(void) 331 { 332 /* Satisfy minimum reset pulse width spec */ 333 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 334 } 335 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED); 336 337 static const struct reg_sequence cs35l56_system_reset_seq[] = { 338 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 339 }; 340 341 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 342 { 343 /* 344 * Must enter cache-only first so there can't be any more register 345 * accesses other than the controlled system reset sequence below. 346 */ 347 regcache_cache_only(cs35l56_base->regmap, true); 348 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 349 cs35l56_system_reset_seq, 350 ARRAY_SIZE(cs35l56_system_reset_seq)); 351 352 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 353 if (is_soundwire) 354 return; 355 356 cs35l56_wait_control_port_ready(); 357 regcache_cache_only(cs35l56_base->regmap, false); 358 } 359 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED); 360 361 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 362 { 363 int ret; 364 365 if (!irq) 366 return 0; 367 368 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 369 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 370 "cs35l56", cs35l56_base); 371 if (!ret) 372 cs35l56_base->irq = irq; 373 else 374 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 375 376 return ret; 377 } 378 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED); 379 380 irqreturn_t cs35l56_irq(int irq, void *data) 381 { 382 struct cs35l56_base *cs35l56_base = data; 383 unsigned int status1 = 0, status8 = 0, status20 = 0; 384 unsigned int mask1, mask8, mask20; 385 unsigned int val; 386 int rv; 387 388 irqreturn_t ret = IRQ_NONE; 389 390 if (!cs35l56_base->init_done) 391 return IRQ_NONE; 392 393 mutex_lock(&cs35l56_base->irq_lock); 394 395 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 396 if (rv < 0) { 397 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 398 goto err_unlock; 399 } 400 401 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 402 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 403 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 404 goto err; 405 } 406 407 /* Ack interrupts */ 408 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 409 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 410 status1 &= ~mask1; 411 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 412 413 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 414 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 415 status8 &= ~mask8; 416 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 417 418 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 419 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 420 status20 &= ~mask20; 421 /* We don't want EINT20 but they default to unmasked: force mask */ 422 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 423 424 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 425 426 /* Check to see if unmasked bits are active */ 427 if (!status1 && !status8 && !status20) 428 goto err; 429 430 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 431 dev_crit(cs35l56_base->dev, "Amp short error\n"); 432 433 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 434 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 435 436 ret = IRQ_HANDLED; 437 438 err: 439 pm_runtime_put(cs35l56_base->dev); 440 err_unlock: 441 mutex_unlock(&cs35l56_base->irq_lock); 442 443 return ret; 444 } 445 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED); 446 447 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 448 { 449 unsigned int val; 450 int ret; 451 452 /* 453 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 454 * can't be used here to test for memory retention. 455 * Assume that tuning must be re-loaded. 456 */ 457 if (cs35l56_base->secured) 458 return true; 459 460 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 461 if (ret) { 462 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 463 return ret; 464 } 465 466 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val); 467 if (ret) 468 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 469 else 470 ret = !!(val & CS35L56_FIRMWARE_MISSING); 471 472 pm_runtime_put_autosuspend(cs35l56_base->dev); 473 474 return ret; 475 } 476 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED); 477 478 static const struct reg_sequence cs35l56_hibernate_seq[] = { 479 /* This must be the last register access */ 480 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 481 }; 482 483 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 484 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 485 }; 486 487 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 488 { 489 /* 490 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 491 * transactions to meet the minimum required time from the rising edge 492 * to the last falling edge of wake. 493 * 494 * It uses bypassed write because we must wake the chip before 495 * disabling regmap cache-only. 496 * 497 * This can NAK on I2C which will terminate the write sequence so the 498 * single-write sequence is issued twice. 499 */ 500 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 501 cs35l56_hibernate_wake_seq, 502 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 503 504 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 505 506 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 507 cs35l56_hibernate_wake_seq, 508 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 509 510 cs35l56_wait_control_port_ready(); 511 } 512 513 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 514 { 515 unsigned int val; 516 int ret; 517 518 if (!cs35l56_base->init_done) 519 return 0; 520 521 /* Firmware must have entered a power-save state */ 522 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 523 CS35L56_TRANSDUCER_ACTUAL_PS, 524 val, (val >= CS35L56_PS3), 525 CS35L56_PS3_POLL_US, 526 CS35L56_PS3_TIMEOUT_US); 527 if (ret) 528 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 529 530 /* Clear BOOT_DONE so it can be used to detect a reboot */ 531 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 532 533 if (!cs35l56_base->can_hibernate) { 534 regcache_cache_only(cs35l56_base->regmap, true); 535 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 536 537 return 0; 538 } 539 540 /* 541 * Must enter cache-only first so there can't be any more register 542 * accesses other than the controlled hibernate sequence below. 543 */ 544 regcache_cache_only(cs35l56_base->regmap, true); 545 546 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 547 cs35l56_hibernate_seq, 548 ARRAY_SIZE(cs35l56_hibernate_seq)); 549 550 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 551 552 return 0; 553 } 554 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED); 555 556 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 557 { 558 unsigned int val; 559 int ret; 560 561 if (!cs35l56_base->init_done) 562 return 0; 563 564 if (!cs35l56_base->can_hibernate) 565 goto out_sync; 566 567 /* Must be done before releasing cache-only */ 568 if (!is_soundwire) 569 cs35l56_issue_wake_event(cs35l56_base); 570 571 out_sync: 572 regcache_cache_only(cs35l56_base->regmap, false); 573 574 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 575 if (ret) { 576 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 577 goto err; 578 } 579 580 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 581 if (ret) 582 goto err; 583 584 /* BOOT_DONE will be 1 if the amp reset */ 585 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 586 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 587 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 588 regcache_mark_dirty(cs35l56_base->regmap); 589 } 590 591 regcache_sync(cs35l56_base->regmap); 592 593 dev_dbg(cs35l56_base->dev, "Resumed"); 594 595 return 0; 596 597 err: 598 regcache_cache_only(cs35l56_base->regmap, true); 599 600 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 601 cs35l56_hibernate_seq, 602 ARRAY_SIZE(cs35l56_hibernate_seq)); 603 604 return ret; 605 } 606 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED); 607 608 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 609 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 610 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 611 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 612 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 613 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 614 }; 615 616 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 617 { 618 cs_dsp->num = 1; 619 cs_dsp->type = WMFW_HALO; 620 cs_dsp->rev = 0; 621 cs_dsp->dev = cs35l56_base->dev; 622 cs_dsp->regmap = cs35l56_base->regmap; 623 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 624 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 625 cs_dsp->mem = cs35l56_dsp1_regions; 626 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 627 cs_dsp->no_core_startstop = true; 628 } 629 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED); 630 631 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 632 bool *fw_missing, unsigned int *fw_version) 633 { 634 unsigned int prot_status; 635 int ret; 636 637 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status); 638 if (ret) { 639 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 640 return ret; 641 } 642 643 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 644 645 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version); 646 if (ret) { 647 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 648 return ret; 649 } 650 651 return 0; 652 } 653 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED); 654 655 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 656 { 657 int ret; 658 unsigned int devid, revid, otpid, secured, fw_ver; 659 bool fw_missing; 660 661 /* 662 * When the system is not using a reset_gpio ensure the device is 663 * awake, otherwise the device has just been released from reset and 664 * the driver must wait for the control port to become usable. 665 */ 666 if (!cs35l56_base->reset_gpio) 667 cs35l56_issue_wake_event(cs35l56_base); 668 else 669 cs35l56_wait_control_port_ready(); 670 671 /* 672 * The HALO_STATE register is in different locations on Ax and B0 673 * devices so the REVID needs to be determined before waiting for the 674 * firmware to boot. 675 */ 676 ret = regmap_read(cs35l56_base->regmap, CS35L56_REVID, &revid); 677 if (ret < 0) { 678 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 679 return ret; 680 } 681 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 682 683 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 684 if (ret) 685 return ret; 686 687 ret = regmap_read(cs35l56_base->regmap, CS35L56_DEVID, &devid); 688 if (ret < 0) { 689 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 690 return ret; 691 } 692 devid &= CS35L56_DEVID_MASK; 693 694 switch (devid) { 695 case 0x35A56: 696 break; 697 default: 698 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 699 return ret; 700 } 701 702 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 703 if (ret) { 704 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 705 return ret; 706 } 707 708 /* When any bus is restricted treat the device as secured */ 709 if (secured & CS35L56_RESTRICTED_MASK) 710 cs35l56_base->secured = true; 711 712 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 713 if (ret < 0) { 714 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 715 return ret; 716 } 717 718 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 719 if (ret) 720 return ret; 721 722 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L56%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 723 cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 724 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 725 726 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 727 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 728 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 729 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 730 0); 731 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 732 CS35L56_TEMP_ERR_EINT1_MASK, 733 0); 734 735 return 0; 736 } 737 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED); 738 739 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 740 { 741 struct gpio_descs *descs; 742 int speaker_id; 743 int i, ret; 744 745 /* Read the speaker type qualifier from the motherboard GPIOs */ 746 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 747 if (!descs) { 748 return -ENOENT; 749 } else if (IS_ERR(descs)) { 750 ret = PTR_ERR(descs); 751 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 752 } 753 754 speaker_id = 0; 755 for (i = 0; i < descs->ndescs; i++) { 756 ret = gpiod_get_value_cansleep(descs->desc[i]); 757 if (ret < 0) { 758 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 759 goto err; 760 } 761 762 speaker_id |= (ret << i); 763 } 764 765 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 766 ret = speaker_id; 767 err: 768 gpiod_put_array(descs); 769 770 return ret; 771 } 772 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED); 773 774 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 775 [0x0C] = 128000, 776 [0x0F] = 256000, 777 [0x11] = 384000, 778 [0x12] = 512000, 779 [0x15] = 768000, 780 [0x17] = 1024000, 781 [0x1A] = 1500000, 782 [0x1B] = 1536000, 783 [0x1C] = 2000000, 784 [0x1D] = 2048000, 785 [0x1E] = 2400000, 786 [0x20] = 3000000, 787 [0x21] = 3072000, 788 [0x23] = 4000000, 789 [0x24] = 4096000, 790 [0x25] = 4800000, 791 [0x27] = 6000000, 792 [0x28] = 6144000, 793 [0x29] = 6250000, 794 [0x2A] = 6400000, 795 [0x2E] = 8000000, 796 [0x2F] = 8192000, 797 [0x30] = 9600000, 798 [0x32] = 12000000, 799 [0x33] = 12288000, 800 [0x37] = 13500000, 801 [0x38] = 19200000, 802 [0x39] = 22579200, 803 [0x3B] = 24576000, 804 }; 805 806 int cs35l56_get_bclk_freq_id(unsigned int freq) 807 { 808 int i; 809 810 if (freq == 0) 811 return -EINVAL; 812 813 /* The BCLK frequency must be a valid PLL REFCLK */ 814 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 815 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 816 return i; 817 } 818 819 return -EINVAL; 820 } 821 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED); 822 823 static const char * const cs35l56_supplies[/* auto-sized */] = { 824 "VDD_P", 825 "VDD_IO", 826 "VDD_A", 827 }; 828 829 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 830 { 831 int i; 832 833 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 834 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 835 data[i].supply = cs35l56_supplies[i]; 836 } 837 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED); 838 839 const char * const cs35l56_tx_input_texts[] = { 840 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 841 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 842 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 843 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 844 }; 845 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED); 846 847 const unsigned int cs35l56_tx_input_values[] = { 848 CS35L56_INPUT_SRC_NONE, 849 CS35L56_INPUT_SRC_ASP1RX1, 850 CS35L56_INPUT_SRC_ASP1RX2, 851 CS35L56_INPUT_SRC_VMON, 852 CS35L56_INPUT_SRC_IMON, 853 CS35L56_INPUT_SRC_ERR_VOL, 854 CS35L56_INPUT_SRC_CLASSH, 855 CS35L56_INPUT_SRC_VDDBMON, 856 CS35L56_INPUT_SRC_VBSTMON, 857 CS35L56_INPUT_SRC_DSP1TX1, 858 CS35L56_INPUT_SRC_DSP1TX2, 859 CS35L56_INPUT_SRC_DSP1TX3, 860 CS35L56_INPUT_SRC_DSP1TX4, 861 CS35L56_INPUT_SRC_DSP1TX5, 862 CS35L56_INPUT_SRC_DSP1TX6, 863 CS35L56_INPUT_SRC_DSP1TX7, 864 CS35L56_INPUT_SRC_DSP1TX8, 865 CS35L56_INPUT_SRC_TEMPMON, 866 CS35L56_INPUT_SRC_INTERPOLATOR, 867 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 868 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 869 }; 870 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED); 871 872 struct regmap_config cs35l56_regmap_i2c = { 873 .reg_bits = 32, 874 .val_bits = 32, 875 .reg_stride = 4, 876 .reg_format_endian = REGMAP_ENDIAN_BIG, 877 .val_format_endian = REGMAP_ENDIAN_BIG, 878 .max_register = CS35L56_DSP1_PMEM_5114, 879 .reg_defaults = cs35l56_reg_defaults, 880 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 881 .volatile_reg = cs35l56_volatile_reg, 882 .readable_reg = cs35l56_readable_reg, 883 .precious_reg = cs35l56_precious_reg, 884 .cache_type = REGCACHE_MAPLE, 885 }; 886 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED); 887 888 struct regmap_config cs35l56_regmap_spi = { 889 .reg_bits = 32, 890 .val_bits = 32, 891 .pad_bits = 16, 892 .reg_stride = 4, 893 .reg_format_endian = REGMAP_ENDIAN_BIG, 894 .val_format_endian = REGMAP_ENDIAN_BIG, 895 .max_register = CS35L56_DSP1_PMEM_5114, 896 .reg_defaults = cs35l56_reg_defaults, 897 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 898 .volatile_reg = cs35l56_volatile_reg, 899 .readable_reg = cs35l56_readable_reg, 900 .precious_reg = cs35l56_precious_reg, 901 .cache_type = REGCACHE_MAPLE, 902 }; 903 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED); 904 905 struct regmap_config cs35l56_regmap_sdw = { 906 .reg_bits = 32, 907 .val_bits = 32, 908 .reg_stride = 4, 909 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 910 .val_format_endian = REGMAP_ENDIAN_BIG, 911 .max_register = CS35L56_DSP1_PMEM_5114, 912 .reg_defaults = cs35l56_reg_defaults, 913 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 914 .volatile_reg = cs35l56_volatile_reg, 915 .readable_reg = cs35l56_readable_reg, 916 .precious_reg = cs35l56_precious_reg, 917 .cache_type = REGCACHE_MAPLE, 918 }; 919 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED); 920 921 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 922 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 923 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 924 MODULE_LICENSE("GPL"); 925