1[ 2 { 3 "BriefDescription": "Number of times HLE abort was triggered", 4 "EventCode": "0xc8", 5 "EventName": "HLE_RETIRED.ABORTED", 6 "PEBS": "1", 7 "PublicDescription": "Number of times HLE abort was triggered.", 8 "SampleAfterValue": "2000003", 9 "UMask": "0x4" 10 }, 11 { 12 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 13 "EventCode": "0xc8", 14 "EventName": "HLE_RETIRED.ABORTED_MISC1", 15 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 16 "SampleAfterValue": "2000003", 17 "UMask": "0x8" 18 }, 19 { 20 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", 21 "EventCode": "0xc8", 22 "EventName": "HLE_RETIRED.ABORTED_MISC2", 23 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", 24 "SampleAfterValue": "2000003", 25 "UMask": "0x10" 26 }, 27 { 28 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", 29 "EventCode": "0xc8", 30 "EventName": "HLE_RETIRED.ABORTED_MISC3", 31 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", 32 "SampleAfterValue": "2000003", 33 "UMask": "0x20" 34 }, 35 { 36 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 37 "EventCode": "0xc8", 38 "EventName": "HLE_RETIRED.ABORTED_MISC4", 39 "PublicDescription": "Number of times HLE caused a fault.", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x40" 42 }, 43 { 44 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 45 "EventCode": "0xc8", 46 "EventName": "HLE_RETIRED.ABORTED_MISC5", 47 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", 48 "SampleAfterValue": "2000003", 49 "UMask": "0x80" 50 }, 51 { 52 "BriefDescription": "Number of times HLE commit succeeded", 53 "EventCode": "0xc8", 54 "EventName": "HLE_RETIRED.COMMIT", 55 "PublicDescription": "Number of times HLE commit succeeded.", 56 "SampleAfterValue": "2000003", 57 "UMask": "0x2" 58 }, 59 { 60 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", 61 "EventCode": "0xc8", 62 "EventName": "HLE_RETIRED.START", 63 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", 64 "SampleAfterValue": "2000003", 65 "UMask": "0x1" 66 }, 67 { 68 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 69 "EventCode": "0xC3", 70 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 71 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 72 "SampleAfterValue": "100003", 73 "UMask": "0x2" 74 }, 75 { 76 "BriefDescription": "Randomly selected loads with latency value being above 128", 77 "Data_LA": "1", 78 "Errata": "BDM100, BDM35", 79 "EventCode": "0xcd", 80 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 81 "MSRIndex": "0x3F6", 82 "MSRValue": "0x80", 83 "PEBS": "2", 84 "PublicDescription": "Counts randomly selected loads with latency value being above 128.", 85 "SampleAfterValue": "1009", 86 "UMask": "0x1" 87 }, 88 { 89 "BriefDescription": "Randomly selected loads with latency value being above 16", 90 "Data_LA": "1", 91 "Errata": "BDM100, BDM35", 92 "EventCode": "0xcd", 93 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 94 "MSRIndex": "0x3F6", 95 "MSRValue": "0x10", 96 "PEBS": "2", 97 "PublicDescription": "Counts randomly selected loads with latency value being above 16.", 98 "SampleAfterValue": "20011", 99 "UMask": "0x1" 100 }, 101 { 102 "BriefDescription": "Randomly selected loads with latency value being above 256", 103 "Data_LA": "1", 104 "Errata": "BDM100, BDM35", 105 "EventCode": "0xcd", 106 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 107 "MSRIndex": "0x3F6", 108 "MSRValue": "0x100", 109 "PEBS": "2", 110 "PublicDescription": "Counts randomly selected loads with latency value being above 256.", 111 "SampleAfterValue": "503", 112 "UMask": "0x1" 113 }, 114 { 115 "BriefDescription": "Randomly selected loads with latency value being above 32", 116 "Data_LA": "1", 117 "Errata": "BDM100, BDM35", 118 "EventCode": "0xcd", 119 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 120 "MSRIndex": "0x3F6", 121 "MSRValue": "0x20", 122 "PEBS": "2", 123 "PublicDescription": "Counts randomly selected loads with latency value being above 32.", 124 "SampleAfterValue": "100007", 125 "UMask": "0x1" 126 }, 127 { 128 "BriefDescription": "Randomly selected loads with latency value being above 4", 129 "Data_LA": "1", 130 "Errata": "BDM100, BDM35", 131 "EventCode": "0xcd", 132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 133 "MSRIndex": "0x3F6", 134 "MSRValue": "0x4", 135 "PEBS": "2", 136 "PublicDescription": "Counts randomly selected loads with latency value being above four.", 137 "SampleAfterValue": "100003", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Randomly selected loads with latency value being above 512", 142 "Data_LA": "1", 143 "Errata": "BDM100, BDM35", 144 "EventCode": "0xcd", 145 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 146 "MSRIndex": "0x3F6", 147 "MSRValue": "0x200", 148 "PEBS": "2", 149 "PublicDescription": "Counts randomly selected loads with latency value being above 512.", 150 "SampleAfterValue": "101", 151 "UMask": "0x1" 152 }, 153 { 154 "BriefDescription": "Randomly selected loads with latency value being above 64", 155 "Data_LA": "1", 156 "Errata": "BDM100, BDM35", 157 "EventCode": "0xcd", 158 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 159 "MSRIndex": "0x3F6", 160 "MSRValue": "0x40", 161 "PEBS": "2", 162 "PublicDescription": "Counts randomly selected loads with latency value being above 64.", 163 "SampleAfterValue": "2003", 164 "UMask": "0x1" 165 }, 166 { 167 "BriefDescription": "Randomly selected loads with latency value being above 8", 168 "Data_LA": "1", 169 "Errata": "BDM100, BDM35", 170 "EventCode": "0xcd", 171 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 172 "MSRIndex": "0x3F6", 173 "MSRValue": "0x8", 174 "PEBS": "2", 175 "PublicDescription": "Counts randomly selected loads with latency value being above eight.", 176 "SampleAfterValue": "50021", 177 "UMask": "0x1" 178 }, 179 { 180 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 181 "EventCode": "0x05", 182 "EventName": "MISALIGN_MEM_REF.LOADS", 183 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", 184 "SampleAfterValue": "2000003", 185 "UMask": "0x1" 186 }, 187 { 188 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 189 "EventCode": "0x05", 190 "EventName": "MISALIGN_MEM_REF.STORES", 191 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", 192 "SampleAfterValue": "2000003", 193 "UMask": "0x2" 194 }, 195 { 196 "BriefDescription": "Number of times RTM abort was triggered", 197 "EventCode": "0xc9", 198 "EventName": "RTM_RETIRED.ABORTED", 199 "PEBS": "1", 200 "PublicDescription": "Number of times RTM abort was triggered .", 201 "SampleAfterValue": "2000003", 202 "UMask": "0x4" 203 }, 204 { 205 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 206 "EventCode": "0xc9", 207 "EventName": "RTM_RETIRED.ABORTED_MISC1", 208 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 209 "SampleAfterValue": "2000003", 210 "UMask": "0x8" 211 }, 212 { 213 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 214 "EventCode": "0xc9", 215 "EventName": "RTM_RETIRED.ABORTED_MISC2", 216 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", 217 "SampleAfterValue": "2000003", 218 "UMask": "0x10" 219 }, 220 { 221 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 222 "EventCode": "0xc9", 223 "EventName": "RTM_RETIRED.ABORTED_MISC3", 224 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", 225 "SampleAfterValue": "2000003", 226 "UMask": "0x20" 227 }, 228 { 229 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 230 "EventCode": "0xc9", 231 "EventName": "RTM_RETIRED.ABORTED_MISC4", 232 "PublicDescription": "Number of times a RTM caused a fault.", 233 "SampleAfterValue": "2000003", 234 "UMask": "0x40" 235 }, 236 { 237 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 238 "EventCode": "0xc9", 239 "EventName": "RTM_RETIRED.ABORTED_MISC5", 240 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", 241 "SampleAfterValue": "2000003", 242 "UMask": "0x80" 243 }, 244 { 245 "BriefDescription": "Number of times RTM commit succeeded", 246 "EventCode": "0xc9", 247 "EventName": "RTM_RETIRED.COMMIT", 248 "PublicDescription": "Number of times RTM commit succeeded.", 249 "SampleAfterValue": "2000003", 250 "UMask": "0x2" 251 }, 252 { 253 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", 254 "EventCode": "0xc9", 255 "EventName": "RTM_RETIRED.START", 256 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", 257 "SampleAfterValue": "2000003", 258 "UMask": "0x1" 259 }, 260 { 261 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 262 "EventCode": "0x5d", 263 "EventName": "TX_EXEC.MISC1", 264 "SampleAfterValue": "2000003", 265 "UMask": "0x1" 266 }, 267 { 268 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 269 "EventCode": "0x5d", 270 "EventName": "TX_EXEC.MISC2", 271 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 272 "SampleAfterValue": "2000003", 273 "UMask": "0x2" 274 }, 275 { 276 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 277 "EventCode": "0x5d", 278 "EventName": "TX_EXEC.MISC3", 279 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 280 "SampleAfterValue": "2000003", 281 "UMask": "0x4" 282 }, 283 { 284 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 285 "EventCode": "0x5d", 286 "EventName": "TX_EXEC.MISC4", 287 "PublicDescription": "RTM region detected inside HLE.", 288 "SampleAfterValue": "2000003", 289 "UMask": "0x8" 290 }, 291 { 292 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 293 "EventCode": "0x5d", 294 "EventName": "TX_EXEC.MISC5", 295 "SampleAfterValue": "2000003", 296 "UMask": "0x10" 297 }, 298 { 299 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", 300 "EventCode": "0x54", 301 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 302 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", 303 "SampleAfterValue": "2000003", 304 "UMask": "0x2" 305 }, 306 { 307 "BriefDescription": "Number of times a TSX line had a cache conflict", 308 "EventCode": "0x54", 309 "EventName": "TX_MEM.ABORT_CONFLICT", 310 "PublicDescription": "Number of times a TSX line had a cache conflict.", 311 "SampleAfterValue": "2000003", 312 "UMask": "0x1" 313 }, 314 { 315 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 316 "EventCode": "0x54", 317 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 318 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 319 "SampleAfterValue": "2000003", 320 "UMask": "0x10" 321 }, 322 { 323 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", 324 "EventCode": "0x54", 325 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 326 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 327 "SampleAfterValue": "2000003", 328 "UMask": "0x8" 329 }, 330 { 331 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", 332 "EventCode": "0x54", 333 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 334 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 335 "SampleAfterValue": "2000003", 336 "UMask": "0x20" 337 }, 338 { 339 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", 340 "EventCode": "0x54", 341 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 342 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 343 "SampleAfterValue": "2000003", 344 "UMask": "0x4" 345 }, 346 { 347 "BriefDescription": "Number of times we could not allocate Lock Buffer", 348 "EventCode": "0x54", 349 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 350 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 351 "SampleAfterValue": "2000003", 352 "UMask": "0x40" 353 } 354] 355