1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/slab.h> /* fault-inject.h is not standalone! */ 7 8 #include <linux/fault-inject.h> 9 #include <linux/sched/mm.h> 10 11 #include <drm/drm_cache.h> 12 13 #include "gem/i915_gem_internal.h" 14 #include "gem/i915_gem_lmem.h" 15 #include "i915_reg.h" 16 #include "i915_trace.h" 17 #include "i915_utils.h" 18 #include "intel_gt.h" 19 #include "intel_gt_mcr.h" 20 #include "intel_gt_print.h" 21 #include "intel_gt_regs.h" 22 #include "intel_gtt.h" 23 24 bool i915_ggtt_require_binder(struct drm_i915_private *i915) 25 { 26 /* Wa_13010847436 & Wa_14019519902 */ 27 return MEDIA_VER_FULL(i915) == IP_VER(13, 0); 28 } 29 30 static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915) 31 { 32 return IS_BROXTON(i915) && i915_vtd_active(i915); 33 } 34 35 bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915) 36 { 37 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); 38 } 39 40 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz) 41 { 42 struct drm_i915_gem_object *obj; 43 44 /* 45 * To avoid severe over-allocation when dealing with min_page_size 46 * restrictions, we override that behaviour here by allowing an object 47 * size and page layout which can be smaller. In practice this should be 48 * totally fine, since GTT paging structures are not typically inserted 49 * into the GTT. 50 * 51 * Note that we also hit this path for the scratch page, and for this 52 * case it might need to be 64K, but that should work fine here since we 53 * used the passed in size for the page size, which should ensure it 54 * also has the same alignment. 55 */ 56 obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 57 vm->lmem_pt_obj_flags); 58 /* 59 * Ensure all paging structures for this vm share the same dma-resv 60 * object underneath, with the idea that one object_lock() will lock 61 * them all at once. 62 */ 63 if (!IS_ERR(obj)) { 64 obj->base.resv = i915_vm_resv_get(vm); 65 obj->shares_resv_from = vm; 66 } 67 68 return obj; 69 } 70 71 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) 72 { 73 struct drm_i915_gem_object *obj; 74 75 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) 76 i915_gem_shrink_all(vm->i915); 77 78 obj = i915_gem_object_create_internal(vm->i915, sz); 79 /* 80 * Ensure all paging structures for this vm share the same dma-resv 81 * object underneath, with the idea that one object_lock() will lock 82 * them all at once. 83 */ 84 if (!IS_ERR(obj)) { 85 obj->base.resv = i915_vm_resv_get(vm); 86 obj->shares_resv_from = vm; 87 } 88 89 return obj; 90 } 91 92 int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 93 { 94 enum i915_map_type type; 95 void *vaddr; 96 97 type = intel_gt_coherent_map_type(vm->gt, obj, true); 98 vaddr = i915_gem_object_pin_map_unlocked(obj, type); 99 if (IS_ERR(vaddr)) 100 return PTR_ERR(vaddr); 101 102 i915_gem_object_make_unshrinkable(obj); 103 return 0; 104 } 105 106 int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 107 { 108 enum i915_map_type type; 109 void *vaddr; 110 111 type = intel_gt_coherent_map_type(vm->gt, obj, true); 112 vaddr = i915_gem_object_pin_map(obj, type); 113 if (IS_ERR(vaddr)) 114 return PTR_ERR(vaddr); 115 116 i915_gem_object_make_unshrinkable(obj); 117 return 0; 118 } 119 120 static void clear_vm_list(struct list_head *list) 121 { 122 struct i915_vma *vma, *vn; 123 124 list_for_each_entry_safe(vma, vn, list, vm_link) { 125 struct drm_i915_gem_object *obj = vma->obj; 126 127 if (!i915_gem_object_get_rcu(obj)) { 128 /* 129 * Object is dying, but has not yet cleared its 130 * vma list. 131 * Unbind the dying vma to ensure our list 132 * is completely drained. We leave the destruction to 133 * the object destructor to avoid the vma 134 * disappearing under it. 135 */ 136 atomic_and(~I915_VMA_PIN_MASK, &vma->flags); 137 WARN_ON(__i915_vma_unbind(vma)); 138 139 /* Remove from the unbound list */ 140 list_del_init(&vma->vm_link); 141 142 /* 143 * Delay the vm and vm mutex freeing until the 144 * object is done with destruction. 145 */ 146 i915_vm_resv_get(vma->vm); 147 vma->vm_ddestroy = true; 148 } else { 149 i915_vma_destroy_locked(vma); 150 i915_gem_object_put(obj); 151 } 152 153 } 154 } 155 156 static void __i915_vm_close(struct i915_address_space *vm) 157 { 158 mutex_lock(&vm->mutex); 159 160 clear_vm_list(&vm->bound_list); 161 clear_vm_list(&vm->unbound_list); 162 163 /* Check for must-fix unanticipated side-effects */ 164 GEM_BUG_ON(!list_empty(&vm->bound_list)); 165 GEM_BUG_ON(!list_empty(&vm->unbound_list)); 166 167 mutex_unlock(&vm->mutex); 168 } 169 170 /* lock the vm into the current ww, if we lock one, we lock all */ 171 int i915_vm_lock_objects(struct i915_address_space *vm, 172 struct i915_gem_ww_ctx *ww) 173 { 174 if (vm->scratch[0]->base.resv == &vm->_resv) { 175 return i915_gem_object_lock(vm->scratch[0], ww); 176 } else { 177 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); 178 179 /* We borrowed the scratch page from ggtt, take the top level object */ 180 return i915_gem_object_lock(ppgtt->pd->pt.base, ww); 181 } 182 } 183 184 void i915_address_space_fini(struct i915_address_space *vm) 185 { 186 drm_mm_takedown(&vm->mm); 187 } 188 189 /** 190 * i915_vm_resv_release - Final struct i915_address_space destructor 191 * @kref: Pointer to the &i915_address_space.resv_ref member. 192 * 193 * This function is called when the last lock sharer no longer shares the 194 * &i915_address_space._resv lock, and also if we raced when 195 * destroying a vma by the vma destruction 196 */ 197 void i915_vm_resv_release(struct kref *kref) 198 { 199 struct i915_address_space *vm = 200 container_of(kref, typeof(*vm), resv_ref); 201 202 dma_resv_fini(&vm->_resv); 203 mutex_destroy(&vm->mutex); 204 205 kfree(vm); 206 } 207 208 static void __i915_vm_release(struct work_struct *work) 209 { 210 struct i915_address_space *vm = 211 container_of(work, struct i915_address_space, release_work); 212 213 __i915_vm_close(vm); 214 215 /* Synchronize async unbinds. */ 216 i915_vma_resource_bind_dep_sync_all(vm); 217 218 vm->cleanup(vm); 219 i915_address_space_fini(vm); 220 221 i915_vm_resv_put(vm); 222 } 223 224 void i915_vm_release(struct kref *kref) 225 { 226 struct i915_address_space *vm = 227 container_of(kref, struct i915_address_space, ref); 228 229 GEM_BUG_ON(i915_is_ggtt(vm)); 230 trace_i915_ppgtt_release(vm); 231 232 queue_work(vm->i915->wq, &vm->release_work); 233 } 234 235 void i915_address_space_init(struct i915_address_space *vm, int subclass) 236 { 237 kref_init(&vm->ref); 238 239 /* 240 * Special case for GGTT that has already done an early 241 * kref_init here. 242 */ 243 if (!kref_read(&vm->resv_ref)) 244 kref_init(&vm->resv_ref); 245 246 vm->pending_unbind = RB_ROOT_CACHED; 247 INIT_WORK(&vm->release_work, __i915_vm_release); 248 249 /* 250 * The vm->mutex must be reclaim safe (for use in the shrinker). 251 * Do a dummy acquire now under fs_reclaim so that any allocation 252 * attempt holding the lock is immediately reported by lockdep. 253 */ 254 mutex_init(&vm->mutex); 255 lockdep_set_subclass(&vm->mutex, subclass); 256 257 if (!intel_vm_no_concurrent_access_wa(vm->i915)) { 258 i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex); 259 } else { 260 /* 261 * CHV + BXT VTD workaround use stop_machine(), 262 * which is allowed to allocate memory. This means &vm->mutex 263 * is the outer lock, and in theory we can allocate memory inside 264 * it through stop_machine(). 265 * 266 * Add the annotation for this, we use trylock in shrinker. 267 */ 268 mutex_acquire(&vm->mutex.dep_map, 0, 0, _THIS_IP_); 269 might_alloc(GFP_KERNEL); 270 mutex_release(&vm->mutex.dep_map, _THIS_IP_); 271 } 272 dma_resv_init(&vm->_resv); 273 274 GEM_BUG_ON(!vm->total); 275 drm_mm_init(&vm->mm, 0, vm->total); 276 277 memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT, 278 ARRAY_SIZE(vm->min_alignment)); 279 280 if (HAS_64K_PAGES(vm->i915)) { 281 vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K; 282 vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_64K; 283 } 284 285 vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; 286 287 INIT_LIST_HEAD(&vm->bound_list); 288 INIT_LIST_HEAD(&vm->unbound_list); 289 } 290 291 void *__px_vaddr(struct drm_i915_gem_object *p) 292 { 293 enum i915_map_type type; 294 295 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 296 return page_unpack_bits(p->mm.mapping, &type); 297 } 298 299 dma_addr_t __px_dma(struct drm_i915_gem_object *p) 300 { 301 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 302 return sg_dma_address(p->mm.pages->sgl); 303 } 304 305 struct page *__px_page(struct drm_i915_gem_object *p) 306 { 307 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 308 return sg_page(p->mm.pages->sgl); 309 } 310 311 void 312 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) 313 { 314 void *vaddr = __px_vaddr(p); 315 316 memset64(vaddr, val, count); 317 drm_clflush_virt_range(vaddr, PAGE_SIZE); 318 } 319 320 static void poison_scratch_page(struct drm_i915_gem_object *scratch) 321 { 322 void *vaddr = __px_vaddr(scratch); 323 u8 val; 324 325 val = 0; 326 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 327 val = POISON_FREE; 328 329 memset(vaddr, val, scratch->base.size); 330 drm_clflush_virt_range(vaddr, scratch->base.size); 331 } 332 333 int setup_scratch_page(struct i915_address_space *vm) 334 { 335 unsigned long size; 336 337 /* 338 * In order to utilize 64K pages for an object with a size < 2M, we will 339 * need to support a 64K scratch page, given that every 16th entry for a 340 * page-table operating in 64K mode must point to a properly aligned 64K 341 * region, including any PTEs which happen to point to scratch. 342 * 343 * This is only relevant for the 48b PPGTT where we support 344 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the 345 * scratch (read-only) between all vm, we create one 64k scratch page 346 * for all. 347 */ 348 size = I915_GTT_PAGE_SIZE_4K; 349 if (i915_vm_is_4lvl(vm) && 350 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K) && 351 !HAS_64K_PAGES(vm->i915)) 352 size = I915_GTT_PAGE_SIZE_64K; 353 354 do { 355 struct drm_i915_gem_object *obj; 356 357 obj = vm->alloc_scratch_dma(vm, size); 358 if (IS_ERR(obj)) 359 goto skip; 360 361 if (map_pt_dma(vm, obj)) 362 goto skip_obj; 363 364 /* We need a single contiguous page for our scratch */ 365 if (obj->mm.page_sizes.sg < size) 366 goto skip_obj; 367 368 /* And it needs to be correspondingly aligned */ 369 if (__px_dma(obj) & (size - 1)) 370 goto skip_obj; 371 372 /* 373 * Use a non-zero scratch page for debugging. 374 * 375 * We want a value that should be reasonably obvious 376 * to spot in the error state, while also causing a GPU hang 377 * if executed. We prefer using a clear page in production, so 378 * should it ever be accidentally used, the effect should be 379 * fairly benign. 380 */ 381 poison_scratch_page(obj); 382 383 vm->scratch[0] = obj; 384 vm->scratch_order = get_order(size); 385 return 0; 386 387 skip_obj: 388 i915_gem_object_put(obj); 389 skip: 390 if (size == I915_GTT_PAGE_SIZE_4K) 391 return -ENOMEM; 392 393 size = I915_GTT_PAGE_SIZE_4K; 394 } while (1); 395 } 396 397 void free_scratch(struct i915_address_space *vm) 398 { 399 int i; 400 401 if (!vm->scratch[0]) 402 return; 403 404 for (i = 0; i <= vm->top; i++) 405 i915_gem_object_put(vm->scratch[i]); 406 } 407 408 void gtt_write_workarounds(struct intel_gt *gt) 409 { 410 struct drm_i915_private *i915 = gt->i915; 411 struct intel_uncore *uncore = gt->uncore; 412 413 /* 414 * This function is for gtt related workarounds. This function is 415 * called on driver load and after a GPU reset, so you can place 416 * workarounds here even if they get overwritten by GPU reset. 417 */ 418 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ 419 if (IS_BROADWELL(i915)) 420 intel_uncore_write(uncore, 421 GEN8_L3_LRA_1_GPGPU, 422 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); 423 else if (IS_CHERRYVIEW(i915)) 424 intel_uncore_write(uncore, 425 GEN8_L3_LRA_1_GPGPU, 426 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); 427 else if (IS_GEN9_LP(i915)) 428 intel_uncore_write(uncore, 429 GEN8_L3_LRA_1_GPGPU, 430 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); 431 else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11) 432 intel_uncore_write(uncore, 433 GEN8_L3_LRA_1_GPGPU, 434 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); 435 436 /* 437 * To support 64K PTEs we need to first enable the use of the 438 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical 439 * mmio, otherwise the page-walker will simply ignore the IPS bit. This 440 * shouldn't be needed after GEN10. 441 * 442 * 64K pages were first introduced from BDW+, although technically they 443 * only *work* from gen9+. For pre-BDW we instead have the option for 444 * 32K pages, but we don't currently have any support for it in our 445 * driver. 446 */ 447 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) && 448 GRAPHICS_VER(i915) <= 10) 449 intel_uncore_rmw(uncore, 450 GEN8_GAMW_ECO_DEV_RW_IA, 451 0, 452 GAMW_ECO_ENABLE_64K_IPS_FIELD); 453 454 if (IS_GRAPHICS_VER(i915, 8, 11)) { 455 bool can_use_gtt_cache = true; 456 457 /* 458 * According to the BSpec if we use 2M/1G pages then we also 459 * need to disable the GTT cache. At least on BDW we can see 460 * visual corruption when using 2M pages, and not disabling the 461 * GTT cache. 462 */ 463 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M)) 464 can_use_gtt_cache = false; 465 466 /* WaGttCachingOffByDefault */ 467 intel_uncore_write(uncore, 468 HSW_GTT_CACHE_EN, 469 can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); 470 gt_WARN_ON_ONCE(gt, can_use_gtt_cache && 471 intel_uncore_read(uncore, 472 HSW_GTT_CACHE_EN) == 0); 473 } 474 } 475 476 static void xelpmp_setup_private_ppat(struct intel_uncore *uncore) 477 { 478 intel_uncore_write(uncore, XELPMP_PAT_INDEX(0), 479 MTL_PPAT_L4_0_WB); 480 intel_uncore_write(uncore, XELPMP_PAT_INDEX(1), 481 MTL_PPAT_L4_1_WT); 482 intel_uncore_write(uncore, XELPMP_PAT_INDEX(2), 483 MTL_PPAT_L4_3_UC); 484 intel_uncore_write(uncore, XELPMP_PAT_INDEX(3), 485 MTL_PPAT_L4_0_WB | MTL_2_COH_1W); 486 intel_uncore_write(uncore, XELPMP_PAT_INDEX(4), 487 MTL_PPAT_L4_0_WB | MTL_3_COH_2W); 488 489 /* 490 * Remaining PAT entries are left at the hardware-default 491 * fully-cached setting 492 */ 493 } 494 495 static void xelpg_setup_private_ppat(struct intel_gt *gt) 496 { 497 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0), 498 MTL_PPAT_L4_0_WB); 499 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1), 500 MTL_PPAT_L4_1_WT); 501 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2), 502 MTL_PPAT_L4_3_UC); 503 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3), 504 MTL_PPAT_L4_0_WB | MTL_2_COH_1W); 505 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4), 506 MTL_PPAT_L4_0_WB | MTL_3_COH_2W); 507 508 /* 509 * Remaining PAT entries are left at the hardware-default 510 * fully-cached setting 511 */ 512 } 513 514 static void tgl_setup_private_ppat(struct intel_uncore *uncore) 515 { 516 /* TGL doesn't support LLC or AGE settings */ 517 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB); 518 intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC); 519 intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT); 520 intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC); 521 intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB); 522 intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB); 523 intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB); 524 intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB); 525 } 526 527 static void xehp_setup_private_ppat(struct intel_gt *gt) 528 { 529 enum forcewake_domains fw; 530 unsigned long flags; 531 532 fw = intel_uncore_forcewake_for_reg(gt->uncore, _MMIO(XEHP_PAT_INDEX(0).reg), 533 FW_REG_WRITE); 534 intel_uncore_forcewake_get(gt->uncore, fw); 535 536 intel_gt_mcr_lock(gt, &flags); 537 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(0), GEN8_PPAT_WB); 538 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(1), GEN8_PPAT_WC); 539 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(2), GEN8_PPAT_WT); 540 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(3), GEN8_PPAT_UC); 541 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(4), GEN8_PPAT_WB); 542 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(5), GEN8_PPAT_WB); 543 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(6), GEN8_PPAT_WB); 544 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(7), GEN8_PPAT_WB); 545 intel_gt_mcr_unlock(gt, flags); 546 547 intel_uncore_forcewake_put(gt->uncore, fw); 548 } 549 550 static void icl_setup_private_ppat(struct intel_uncore *uncore) 551 { 552 intel_uncore_write(uncore, 553 GEN10_PAT_INDEX(0), 554 GEN8_PPAT_WB | GEN8_PPAT_LLC); 555 intel_uncore_write(uncore, 556 GEN10_PAT_INDEX(1), 557 GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); 558 intel_uncore_write(uncore, 559 GEN10_PAT_INDEX(2), 560 GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 561 intel_uncore_write(uncore, 562 GEN10_PAT_INDEX(3), 563 GEN8_PPAT_UC); 564 intel_uncore_write(uncore, 565 GEN10_PAT_INDEX(4), 566 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); 567 intel_uncore_write(uncore, 568 GEN10_PAT_INDEX(5), 569 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); 570 intel_uncore_write(uncore, 571 GEN10_PAT_INDEX(6), 572 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); 573 intel_uncore_write(uncore, 574 GEN10_PAT_INDEX(7), 575 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 576 } 577 578 /* 579 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability 580 * bits. When using advanced contexts each context stores its own PAT, but 581 * writing this data shouldn't be harmful even in those cases. 582 */ 583 static void bdw_setup_private_ppat(struct intel_uncore *uncore) 584 { 585 struct drm_i915_private *i915 = uncore->i915; 586 u64 pat; 587 588 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ 589 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ 590 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ 591 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | 592 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | 593 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | 594 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 595 596 /* for scanout with eLLC */ 597 if (GRAPHICS_VER(i915) >= 9) 598 pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 599 else 600 pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); 601 602 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 603 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 604 } 605 606 static void chv_setup_private_ppat(struct intel_uncore *uncore) 607 { 608 u64 pat; 609 610 /* 611 * Map WB on BDW to snooped on CHV. 612 * 613 * Only the snoop bit has meaning for CHV, the rest is 614 * ignored. 615 * 616 * The hardware will never snoop for certain types of accesses: 617 * - CPU GTT (GMADR->GGTT->no snoop->memory) 618 * - PPGTT page tables 619 * - some other special cycles 620 * 621 * As with BDW, we also need to consider the following for GT accesses: 622 * "For GGTT, there is NO pat_sel[2:0] from the entry, 623 * so RTL will always use the value corresponding to 624 * pat_sel = 000". 625 * Which means we must set the snoop bit in PAT entry 0 626 * in order to keep the global status page working. 627 */ 628 629 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | 630 GEN8_PPAT(1, 0) | 631 GEN8_PPAT(2, 0) | 632 GEN8_PPAT(3, 0) | 633 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 634 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 635 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 636 GEN8_PPAT(7, CHV_PPAT_SNOOP); 637 638 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 639 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 640 } 641 642 void setup_private_pat(struct intel_gt *gt) 643 { 644 struct intel_uncore *uncore = gt->uncore; 645 struct drm_i915_private *i915 = gt->i915; 646 647 GEM_BUG_ON(GRAPHICS_VER(i915) < 8); 648 649 if (gt->type == GT_MEDIA) { 650 xelpmp_setup_private_ppat(gt->uncore); 651 return; 652 } 653 654 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 655 xelpg_setup_private_ppat(gt); 656 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 657 xehp_setup_private_ppat(gt); 658 else if (GRAPHICS_VER(i915) >= 12) 659 tgl_setup_private_ppat(uncore); 660 else if (GRAPHICS_VER(i915) >= 11) 661 icl_setup_private_ppat(uncore); 662 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) 663 chv_setup_private_ppat(uncore); 664 else 665 bdw_setup_private_ppat(uncore); 666 } 667 668 struct i915_vma * 669 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size) 670 { 671 struct drm_i915_gem_object *obj; 672 struct i915_vma *vma; 673 674 obj = i915_gem_object_create_internal(vm->i915, PAGE_ALIGN(size)); 675 if (IS_ERR(obj)) 676 return ERR_CAST(obj); 677 678 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 679 680 vma = i915_vma_instance(obj, vm, NULL); 681 if (IS_ERR(vma)) { 682 i915_gem_object_put(obj); 683 return vma; 684 } 685 686 return vma; 687 } 688 689 struct i915_vma * 690 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size) 691 { 692 struct i915_vma *vma; 693 int err; 694 695 vma = __vm_create_scratch_for_read(vm, size); 696 if (IS_ERR(vma)) 697 return vma; 698 699 err = i915_vma_pin(vma, 0, 0, 700 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 701 if (err) { 702 i915_vma_put(vma); 703 return ERR_PTR(err); 704 } 705 706 return vma; 707 } 708 709 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 710 #include "selftests/mock_gtt.c" 711 #endif 712