1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 #include <net/devlink.h> 12 13 #include "hclge_cmd.h" 14 #include "hclge_ptp.h" 15 #include "hnae3.h" 16 #include "hclge_comm_rss.h" 17 #include "hclge_comm_tqp_stats.h" 18 19 #define HCLGE_MOD_VERSION "1.0" 20 #define HCLGE_DRIVER_NAME "hclge" 21 22 #define HCLGE_MAX_PF_NUM 8 23 24 #define HCLGE_VF_VPORT_START_NUM 1 25 26 #define HCLGE_RD_FIRST_STATS_NUM 2 27 #define HCLGE_RD_OTHER_STATS_NUM 4 28 29 #define HCLGE_INVALID_VPORT 0xffff 30 31 #define HCLGE_PF_CFG_BLOCK_SIZE 32 32 #define HCLGE_PF_CFG_DESC_NUM \ 33 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 34 35 #define HCLGE_VECTOR_REG_BASE 0x20000 36 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 37 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 38 39 #define HCLGE_VECTOR_REG_OFFSET 0x4 40 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 41 #define HCLGE_VECTOR_VF_OFFSET 0x100000 42 43 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 44 45 /* bar registers for common func */ 46 #define HCLGE_GRO_EN_REG 0x28000 47 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 48 49 /* bar registers for rcb */ 50 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 51 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 52 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 53 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 54 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 55 #define HCLGE_RING_RX_TAIL_REG 0x80018 56 #define HCLGE_RING_RX_HEAD_REG 0x8001C 57 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 58 #define HCLGE_RING_RX_OFFSET_REG 0x80024 59 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 60 #define HCLGE_RING_RX_STASH_REG 0x80030 61 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 62 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 63 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 64 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 65 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 66 #define HCLGE_RING_TX_TC_REG 0x80050 67 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 68 #define HCLGE_RING_TX_TAIL_REG 0x80058 69 #define HCLGE_RING_TX_HEAD_REG 0x8005C 70 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 71 #define HCLGE_RING_TX_OFFSET_REG 0x80064 72 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 73 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 74 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 75 #define HCLGE_RING_EN_REG 0x80090 76 77 /* bar registers for tqp interrupt */ 78 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 79 #define HCLGE_TQP_INTR_GL0_REG 0x20100 80 #define HCLGE_TQP_INTR_GL1_REG 0x20200 81 #define HCLGE_TQP_INTR_GL2_REG 0x20300 82 #define HCLGE_TQP_INTR_RL_REG 0x20900 83 84 #define HCLGE_RSS_IND_TBL_SIZE 512 85 86 #define HCLGE_RSS_TC_SIZE_0 1 87 #define HCLGE_RSS_TC_SIZE_1 2 88 #define HCLGE_RSS_TC_SIZE_2 4 89 #define HCLGE_RSS_TC_SIZE_3 8 90 #define HCLGE_RSS_TC_SIZE_4 16 91 #define HCLGE_RSS_TC_SIZE_5 32 92 #define HCLGE_RSS_TC_SIZE_6 64 93 #define HCLGE_RSS_TC_SIZE_7 128 94 95 #define HCLGE_UMV_TBL_SIZE 3072 96 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 97 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 98 99 #define HCLGE_TQP_RESET_TRY_TIMES 200 100 101 #define HCLGE_PHY_PAGE_MDIX 0 102 #define HCLGE_PHY_PAGE_COPPER 0 103 104 /* Page Selection Reg. */ 105 #define HCLGE_PHY_PAGE_REG 22 106 107 /* Copper Specific Control Register */ 108 #define HCLGE_PHY_CSC_REG 16 109 110 /* Copper Specific Status Register */ 111 #define HCLGE_PHY_CSS_REG 17 112 113 #define HCLGE_PHY_MDIX_CTRL_S 5 114 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 115 116 #define HCLGE_PHY_MDIX_STATUS_B 6 117 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 118 119 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 120 121 /* Factor used to calculate offset and bitmap of VF num */ 122 #define HCLGE_VF_NUM_PER_CMD 64 123 124 #define HCLGE_MAX_QSET_NUM 1024 125 126 #define HCLGE_DBG_RESET_INFO_LEN 1024 127 128 enum HLCGE_PORT_TYPE { 129 HOST_PORT, 130 NETWORK_PORT 131 }; 132 133 #define PF_VPORT_ID 0 134 135 #define HCLGE_PF_ID_S 0 136 #define HCLGE_PF_ID_M GENMASK(2, 0) 137 #define HCLGE_VF_ID_S 3 138 #define HCLGE_VF_ID_M GENMASK(10, 3) 139 #define HCLGE_PORT_TYPE_B 11 140 #define HCLGE_NETWORK_PORT_ID_S 0 141 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 142 143 /* Reset related Registers */ 144 #define HCLGE_PF_OTHER_INT_REG 0x20600 145 #define HCLGE_MISC_RESET_STS_REG 0x20700 146 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 147 #define HCLGE_GLOBAL_RESET_REG 0x20A00 148 #define HCLGE_GLOBAL_RESET_BIT 0 149 #define HCLGE_CORE_RESET_BIT 1 150 #define HCLGE_IMP_RESET_BIT 2 151 #define HCLGE_RESET_INT_M GENMASK(7, 5) 152 #define HCLGE_FUN_RST_ING 0x20C00 153 #define HCLGE_FUN_RST_ING_B 0 154 155 /* Vector0 register bits define */ 156 #define HCLGE_VECTOR0_REG_PTP_INT_B 0 157 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 158 #define HCLGE_VECTOR0_CORERESET_INT_B 6 159 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 160 161 /* Vector0 interrupt CMDQ event source register(RW) */ 162 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 163 /* CMDQ register bits for RX event(=MBX event) */ 164 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 165 166 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 167 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 168 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 169 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 170 #define HCLGE_TRIGGER_IMP_RESET_B 7U 171 172 #define HCLGE_TQP_MEM_SIZE 0x10000 173 #define HCLGE_MEM_BAR 4 174 /* in the bar4, the first half is for roce, and the second half is for nic */ 175 #define HCLGE_NIC_MEM_OFFSET(hdev) \ 176 (pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1) 177 #define HCLGE_TQP_MEM_OFFSET(hdev, i) \ 178 (HCLGE_NIC_MEM_OFFSET(hdev) + HCLGE_TQP_MEM_SIZE * (i)) 179 180 #define HCLGE_MAC_DEFAULT_FRAME \ 181 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 182 #define HCLGE_MAC_MIN_FRAME 64 183 #define HCLGE_MAC_MAX_FRAME 9728 184 185 #define HCLGE_SUPPORT_1G_BIT BIT(0) 186 #define HCLGE_SUPPORT_10G_BIT BIT(1) 187 #define HCLGE_SUPPORT_25G_BIT BIT(2) 188 #define HCLGE_SUPPORT_50G_R2_BIT BIT(3) 189 #define HCLGE_SUPPORT_100G_R4_BIT BIT(4) 190 /* to be compatible with exsit board */ 191 #define HCLGE_SUPPORT_40G_BIT BIT(5) 192 #define HCLGE_SUPPORT_100M_BIT BIT(6) 193 #define HCLGE_SUPPORT_10M_BIT BIT(7) 194 #define HCLGE_SUPPORT_200G_BIT BIT(8) 195 #define HCLGE_SUPPORT_50G_R1_BIT BIT(9) 196 #define HCLGE_SUPPORT_100G_R2_BIT BIT(10) 197 198 #define HCLGE_SUPPORT_GE \ 199 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 200 #define HCLGE_SUPPORT_50G_BITS \ 201 (HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT) 202 #define HCLGE_SUPPORT_100G_BITS \ 203 (HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT) 204 205 enum HCLGE_DEV_STATE { 206 HCLGE_STATE_REINITING, 207 HCLGE_STATE_DOWN, 208 HCLGE_STATE_DISABLED, 209 HCLGE_STATE_REMOVING, 210 HCLGE_STATE_NIC_REGISTERED, 211 HCLGE_STATE_ROCE_REGISTERED, 212 HCLGE_STATE_SERVICE_INITED, 213 HCLGE_STATE_RST_SERVICE_SCHED, 214 HCLGE_STATE_RST_HANDLING, 215 HCLGE_STATE_MBX_SERVICE_SCHED, 216 HCLGE_STATE_MBX_HANDLING, 217 HCLGE_STATE_ERR_SERVICE_SCHED, 218 HCLGE_STATE_STATISTICS_UPDATING, 219 HCLGE_STATE_LINK_UPDATING, 220 HCLGE_STATE_RST_FAIL, 221 HCLGE_STATE_FD_TBL_CHANGED, 222 HCLGE_STATE_FD_CLEAR_ALL, 223 HCLGE_STATE_FD_USER_DEF_CHANGED, 224 HCLGE_STATE_PTP_EN, 225 HCLGE_STATE_PTP_TX_HANDLING, 226 HCLGE_STATE_FEC_STATS_UPDATING, 227 HCLGE_STATE_MAX 228 }; 229 230 enum hclge_evt_cause { 231 HCLGE_VECTOR0_EVENT_RST, 232 HCLGE_VECTOR0_EVENT_MBX, 233 HCLGE_VECTOR0_EVENT_ERR, 234 HCLGE_VECTOR0_EVENT_PTP, 235 HCLGE_VECTOR0_EVENT_OTHER, 236 }; 237 238 enum HCLGE_MAC_SPEED { 239 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 240 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 241 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 242 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 243 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 244 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 245 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 246 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 247 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 248 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 249 }; 250 251 enum HCLGE_MAC_DUPLEX { 252 HCLGE_MAC_HALF, 253 HCLGE_MAC_FULL 254 }; 255 256 #define QUERY_SFP_SPEED 0 257 #define QUERY_ACTIVE_SPEED 1 258 259 struct hclge_wol_info { 260 u32 wol_support_mode; /* store the wake on lan info */ 261 u32 wol_current_mode; 262 u8 wol_sopass[SOPASS_MAX]; 263 u8 wol_sopass_size; 264 }; 265 266 struct hclge_mac { 267 u8 mac_id; 268 u8 phy_addr; 269 u8 flag; 270 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 271 u8 mac_addr[ETH_ALEN]; 272 u8 autoneg; 273 u8 duplex; 274 u8 support_autoneg; 275 u8 speed_type; /* 0: sfp speed, 1: active speed */ 276 u8 lane_num; 277 u32 speed; 278 u32 max_speed; 279 u32 speed_ability; /* speed ability supported by current media */ 280 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 281 u32 fec_mode; /* active fec mode */ 282 u32 user_fec_mode; 283 u32 fec_ability; 284 int link; /* store the link status of mac & phy (if phy exists) */ 285 struct hclge_wol_info wol; 286 struct phy_device *phydev; 287 struct mii_bus *mdio_bus; 288 phy_interface_t phy_if; 289 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 290 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 291 }; 292 293 struct hclge_hw { 294 struct hclge_comm_hw hw; 295 struct hclge_mac mac; 296 int num_vec; 297 }; 298 299 enum hclge_fc_mode { 300 HCLGE_FC_NONE, 301 HCLGE_FC_RX_PAUSE, 302 HCLGE_FC_TX_PAUSE, 303 HCLGE_FC_FULL, 304 HCLGE_FC_PFC, 305 HCLGE_FC_DEFAULT 306 }; 307 308 #define HCLGE_FILTER_TYPE_VF 0 309 #define HCLGE_FILTER_TYPE_PORT 1 310 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 311 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 312 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 313 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 314 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 315 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 316 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 317 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 318 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 319 320 enum hclge_vlan_fltr_cap { 321 HCLGE_VLAN_FLTR_DEF, 322 HCLGE_VLAN_FLTR_CAN_MDF, 323 }; 324 enum hclge_link_fail_code { 325 HCLGE_LF_NORMAL, 326 HCLGE_LF_REF_CLOCK_LOST, 327 HCLGE_LF_XSFP_TX_DISABLE, 328 HCLGE_LF_XSFP_ABSENT, 329 }; 330 331 #define HCLGE_LINK_STATUS_DOWN 0 332 #define HCLGE_LINK_STATUS_UP 1 333 334 #define HCLGE_PG_NUM 4 335 #define HCLGE_SCH_MODE_SP 0 336 #define HCLGE_SCH_MODE_DWRR 1 337 struct hclge_pg_info { 338 u8 pg_id; 339 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 340 u8 tc_bit_map; 341 u32 bw_limit; 342 u8 tc_dwrr[HNAE3_MAX_TC]; 343 }; 344 345 struct hclge_tc_info { 346 u8 tc_id; 347 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 348 u8 pgid; 349 u32 bw_limit; 350 }; 351 352 struct hclge_cfg { 353 u8 tc_num; 354 u8 vlan_fliter_cap; 355 u16 tqp_desc_num; 356 u16 rx_buf_len; 357 u16 vf_rss_size_max; 358 u16 pf_rss_size_max; 359 u8 phy_addr; 360 u8 media_type; 361 u8 mac_addr[ETH_ALEN]; 362 u8 default_speed; 363 u32 numa_node_map; 364 u32 tx_spare_buf_size; 365 u16 speed_ability; 366 u16 umv_space; 367 }; 368 369 struct hclge_tm_info { 370 u8 num_tc; 371 u8 num_pg; /* It must be 1 if vNET-Base schd */ 372 u8 pg_dwrr[HCLGE_PG_NUM]; 373 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 374 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 375 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 376 enum hclge_fc_mode fc_mode; 377 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 378 u8 pfc_en; /* PFC enabled or not for user priority */ 379 }; 380 381 /* max number of mac statistics on each version */ 382 #define HCLGE_MAC_STATS_MAX_NUM_V1 87 383 #define HCLGE_MAC_STATS_MAX_NUM_V2 105 384 385 struct hclge_comm_stats_str { 386 char desc[ETH_GSTRING_LEN]; 387 u32 stats_num; 388 unsigned long offset; 389 }; 390 391 /* mac stats ,opcode id: 0x0032 */ 392 struct hclge_mac_stats { 393 u64 mac_tx_mac_pause_num; 394 u64 mac_rx_mac_pause_num; 395 u64 rsv0; 396 u64 mac_tx_pfc_pri0_pkt_num; 397 u64 mac_tx_pfc_pri1_pkt_num; 398 u64 mac_tx_pfc_pri2_pkt_num; 399 u64 mac_tx_pfc_pri3_pkt_num; 400 u64 mac_tx_pfc_pri4_pkt_num; 401 u64 mac_tx_pfc_pri5_pkt_num; 402 u64 mac_tx_pfc_pri6_pkt_num; 403 u64 mac_tx_pfc_pri7_pkt_num; 404 u64 mac_rx_pfc_pri0_pkt_num; 405 u64 mac_rx_pfc_pri1_pkt_num; 406 u64 mac_rx_pfc_pri2_pkt_num; 407 u64 mac_rx_pfc_pri3_pkt_num; 408 u64 mac_rx_pfc_pri4_pkt_num; 409 u64 mac_rx_pfc_pri5_pkt_num; 410 u64 mac_rx_pfc_pri6_pkt_num; 411 u64 mac_rx_pfc_pri7_pkt_num; 412 u64 mac_tx_total_pkt_num; 413 u64 mac_tx_total_oct_num; 414 u64 mac_tx_good_pkt_num; 415 u64 mac_tx_bad_pkt_num; 416 u64 mac_tx_good_oct_num; 417 u64 mac_tx_bad_oct_num; 418 u64 mac_tx_uni_pkt_num; 419 u64 mac_tx_multi_pkt_num; 420 u64 mac_tx_broad_pkt_num; 421 u64 mac_tx_undersize_pkt_num; 422 u64 mac_tx_oversize_pkt_num; 423 u64 mac_tx_64_oct_pkt_num; 424 u64 mac_tx_65_127_oct_pkt_num; 425 u64 mac_tx_128_255_oct_pkt_num; 426 u64 mac_tx_256_511_oct_pkt_num; 427 u64 mac_tx_512_1023_oct_pkt_num; 428 u64 mac_tx_1024_1518_oct_pkt_num; 429 u64 mac_tx_1519_2047_oct_pkt_num; 430 u64 mac_tx_2048_4095_oct_pkt_num; 431 u64 mac_tx_4096_8191_oct_pkt_num; 432 u64 rsv1; 433 u64 mac_tx_8192_9216_oct_pkt_num; 434 u64 mac_tx_9217_12287_oct_pkt_num; 435 u64 mac_tx_12288_16383_oct_pkt_num; 436 u64 mac_tx_1519_max_good_oct_pkt_num; 437 u64 mac_tx_1519_max_bad_oct_pkt_num; 438 439 u64 mac_rx_total_pkt_num; 440 u64 mac_rx_total_oct_num; 441 u64 mac_rx_good_pkt_num; 442 u64 mac_rx_bad_pkt_num; 443 u64 mac_rx_good_oct_num; 444 u64 mac_rx_bad_oct_num; 445 u64 mac_rx_uni_pkt_num; 446 u64 mac_rx_multi_pkt_num; 447 u64 mac_rx_broad_pkt_num; 448 u64 mac_rx_undersize_pkt_num; 449 u64 mac_rx_oversize_pkt_num; 450 u64 mac_rx_64_oct_pkt_num; 451 u64 mac_rx_65_127_oct_pkt_num; 452 u64 mac_rx_128_255_oct_pkt_num; 453 u64 mac_rx_256_511_oct_pkt_num; 454 u64 mac_rx_512_1023_oct_pkt_num; 455 u64 mac_rx_1024_1518_oct_pkt_num; 456 u64 mac_rx_1519_2047_oct_pkt_num; 457 u64 mac_rx_2048_4095_oct_pkt_num; 458 u64 mac_rx_4096_8191_oct_pkt_num; 459 u64 rsv2; 460 u64 mac_rx_8192_9216_oct_pkt_num; 461 u64 mac_rx_9217_12287_oct_pkt_num; 462 u64 mac_rx_12288_16383_oct_pkt_num; 463 u64 mac_rx_1519_max_good_oct_pkt_num; 464 u64 mac_rx_1519_max_bad_oct_pkt_num; 465 466 u64 mac_tx_fragment_pkt_num; 467 u64 mac_tx_undermin_pkt_num; 468 u64 mac_tx_jabber_pkt_num; 469 u64 mac_tx_err_all_pkt_num; 470 u64 mac_tx_from_app_good_pkt_num; 471 u64 mac_tx_from_app_bad_pkt_num; 472 u64 mac_rx_fragment_pkt_num; 473 u64 mac_rx_undermin_pkt_num; 474 u64 mac_rx_jabber_pkt_num; 475 u64 mac_rx_fcs_err_pkt_num; 476 u64 mac_rx_send_app_good_pkt_num; 477 u64 mac_rx_send_app_bad_pkt_num; 478 u64 mac_tx_pfc_pause_pkt_num; 479 u64 mac_rx_pfc_pause_pkt_num; 480 u64 mac_tx_ctrl_pkt_num; 481 u64 mac_rx_ctrl_pkt_num; 482 483 /* duration of pfc */ 484 u64 mac_tx_pfc_pri0_xoff_time; 485 u64 mac_tx_pfc_pri1_xoff_time; 486 u64 mac_tx_pfc_pri2_xoff_time; 487 u64 mac_tx_pfc_pri3_xoff_time; 488 u64 mac_tx_pfc_pri4_xoff_time; 489 u64 mac_tx_pfc_pri5_xoff_time; 490 u64 mac_tx_pfc_pri6_xoff_time; 491 u64 mac_tx_pfc_pri7_xoff_time; 492 u64 mac_rx_pfc_pri0_xoff_time; 493 u64 mac_rx_pfc_pri1_xoff_time; 494 u64 mac_rx_pfc_pri2_xoff_time; 495 u64 mac_rx_pfc_pri3_xoff_time; 496 u64 mac_rx_pfc_pri4_xoff_time; 497 u64 mac_rx_pfc_pri5_xoff_time; 498 u64 mac_rx_pfc_pri6_xoff_time; 499 u64 mac_rx_pfc_pri7_xoff_time; 500 501 /* duration of pause */ 502 u64 mac_tx_pause_xoff_time; 503 u64 mac_rx_pause_xoff_time; 504 }; 505 506 #define HCLGE_STATS_TIMER_INTERVAL 300UL 507 508 /* fec stats ,opcode id: 0x0316 */ 509 #define HCLGE_FEC_STATS_MAX_LANES 8 510 struct hclge_fec_stats { 511 /* fec rs mode total stats */ 512 u64 rs_corr_blocks; 513 u64 rs_uncorr_blocks; 514 u64 rs_error_blocks; 515 /* fec base-r mode per lanes stats */ 516 u64 base_r_lane_num; 517 u64 base_r_corr_blocks; 518 u64 base_r_uncorr_blocks; 519 union { 520 struct { 521 u64 base_r_corr_per_lanes[HCLGE_FEC_STATS_MAX_LANES]; 522 u64 base_r_uncorr_per_lanes[HCLGE_FEC_STATS_MAX_LANES]; 523 }; 524 u64 per_lanes[HCLGE_FEC_STATS_MAX_LANES * 2]; 525 }; 526 }; 527 528 struct hclge_vlan_type_cfg { 529 u16 rx_ot_fst_vlan_type; 530 u16 rx_ot_sec_vlan_type; 531 u16 rx_in_fst_vlan_type; 532 u16 rx_in_sec_vlan_type; 533 u16 tx_ot_vlan_type; 534 u16 tx_in_vlan_type; 535 }; 536 537 enum HCLGE_FD_MODE { 538 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 539 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 540 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 541 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 542 }; 543 544 enum HCLGE_FD_KEY_TYPE { 545 HCLGE_FD_KEY_BASE_ON_PTYPE, 546 HCLGE_FD_KEY_BASE_ON_TUPLE, 547 }; 548 549 enum HCLGE_FD_STAGE { 550 HCLGE_FD_STAGE_1, 551 HCLGE_FD_STAGE_2, 552 MAX_STAGE_NUM, 553 }; 554 555 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 556 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 557 * tuples of non-tunnel packet 558 */ 559 enum HCLGE_FD_TUPLE { 560 OUTER_DST_MAC, 561 OUTER_SRC_MAC, 562 OUTER_VLAN_TAG_FST, 563 OUTER_VLAN_TAG_SEC, 564 OUTER_ETH_TYPE, 565 OUTER_L2_RSV, 566 OUTER_IP_TOS, 567 OUTER_IP_PROTO, 568 OUTER_SRC_IP, 569 OUTER_DST_IP, 570 OUTER_L3_RSV, 571 OUTER_SRC_PORT, 572 OUTER_DST_PORT, 573 OUTER_L4_RSV, 574 OUTER_TUN_VNI, 575 OUTER_TUN_FLOW_ID, 576 INNER_DST_MAC, 577 INNER_SRC_MAC, 578 INNER_VLAN_TAG_FST, 579 INNER_VLAN_TAG_SEC, 580 INNER_ETH_TYPE, 581 INNER_L2_RSV, 582 INNER_IP_TOS, 583 INNER_IP_PROTO, 584 INNER_SRC_IP, 585 INNER_DST_IP, 586 INNER_L3_RSV, 587 INNER_SRC_PORT, 588 INNER_DST_PORT, 589 INNER_L4_RSV, 590 MAX_TUPLE, 591 }; 592 593 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 594 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 595 596 enum HCLGE_FD_META_DATA { 597 PACKET_TYPE_ID, 598 IP_FRAGEMENT, 599 ROCE_TYPE, 600 NEXT_KEY, 601 VLAN_NUMBER, 602 SRC_VPORT, 603 DST_VPORT, 604 TUNNEL_PACKET, 605 MAX_META_DATA, 606 }; 607 608 enum HCLGE_FD_KEY_OPT { 609 KEY_OPT_U8, 610 KEY_OPT_LE16, 611 KEY_OPT_LE32, 612 KEY_OPT_MAC, 613 KEY_OPT_IP, 614 KEY_OPT_VNI, 615 }; 616 617 struct key_info { 618 u8 key_type; 619 u8 key_length; /* use bit as unit */ 620 enum HCLGE_FD_KEY_OPT key_opt; 621 int offset; 622 int moffset; 623 }; 624 625 #define MAX_KEY_LENGTH 400 626 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 627 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 628 #define MAX_META_DATA_LENGTH 32 629 630 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 631 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 632 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 633 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 634 635 /* assigned by firmware, the real filter number for each pf may be less */ 636 #define MAX_FD_FILTER_NUM 4096 637 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 638 639 #define hclge_read_dev(a, reg) \ 640 hclge_comm_read_reg((a)->hw.io_base, reg) 641 #define hclge_write_dev(a, reg, value) \ 642 hclge_comm_write_reg((a)->hw.io_base, reg, value) 643 644 enum HCLGE_FD_ACTIVE_RULE_TYPE { 645 HCLGE_FD_RULE_NONE, 646 HCLGE_FD_ARFS_ACTIVE, 647 HCLGE_FD_EP_ACTIVE, 648 HCLGE_FD_TC_FLOWER_ACTIVE, 649 }; 650 651 enum HCLGE_FD_PACKET_TYPE { 652 NIC_PACKET, 653 ROCE_PACKET, 654 }; 655 656 enum HCLGE_FD_ACTION { 657 HCLGE_FD_ACTION_SELECT_QUEUE, 658 HCLGE_FD_ACTION_DROP_PACKET, 659 HCLGE_FD_ACTION_SELECT_TC, 660 }; 661 662 enum HCLGE_FD_NODE_STATE { 663 HCLGE_FD_TO_ADD, 664 HCLGE_FD_TO_DEL, 665 HCLGE_FD_ACTIVE, 666 HCLGE_FD_DELETED, 667 }; 668 669 enum HCLGE_FD_USER_DEF_LAYER { 670 HCLGE_FD_USER_DEF_NONE, 671 HCLGE_FD_USER_DEF_L2, 672 HCLGE_FD_USER_DEF_L3, 673 HCLGE_FD_USER_DEF_L4, 674 }; 675 676 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 677 struct hclge_fd_user_def_cfg { 678 u16 ref_cnt; 679 u16 offset; 680 }; 681 682 struct hclge_fd_user_def_info { 683 enum HCLGE_FD_USER_DEF_LAYER layer; 684 u16 data; 685 u16 data_mask; 686 u16 offset; 687 }; 688 689 struct hclge_fd_key_cfg { 690 u8 key_sel; 691 u8 inner_sipv6_word_en; 692 u8 inner_dipv6_word_en; 693 u8 outer_sipv6_word_en; 694 u8 outer_dipv6_word_en; 695 u32 tuple_active; 696 u32 meta_data_active; 697 }; 698 699 struct hclge_fd_cfg { 700 u8 fd_mode; 701 u16 max_key_length; /* use bit as unit */ 702 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 703 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 704 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 705 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 706 }; 707 708 #define IPV4_INDEX 3 709 #define IPV6_SIZE 4 710 struct hclge_fd_rule_tuples { 711 u8 src_mac[ETH_ALEN]; 712 u8 dst_mac[ETH_ALEN]; 713 /* Be compatible for ip address of both ipv4 and ipv6. 714 * For ipv4 address, we store it in src/dst_ip[3]. 715 */ 716 u32 src_ip[IPV6_SIZE]; 717 u32 dst_ip[IPV6_SIZE]; 718 u16 src_port; 719 u16 dst_port; 720 u16 vlan_tag1; 721 u16 ether_proto; 722 u16 l2_user_def; 723 u16 l3_user_def; 724 u32 l4_user_def; 725 u8 ip_tos; 726 u8 ip_proto; 727 }; 728 729 struct hclge_fd_rule { 730 struct hlist_node rule_node; 731 struct hclge_fd_rule_tuples tuples; 732 struct hclge_fd_rule_tuples tuples_mask; 733 u32 unused_tuple; 734 u32 flow_type; 735 union { 736 struct { 737 unsigned long cookie; 738 u8 tc; 739 } cls_flower; 740 struct { 741 u16 flow_id; /* only used for arfs */ 742 } arfs; 743 struct { 744 struct hclge_fd_user_def_info user_def; 745 } ep; 746 }; 747 u16 queue_id; 748 u16 vf_id; 749 u16 location; 750 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 751 enum HCLGE_FD_NODE_STATE state; 752 u8 action; 753 }; 754 755 struct hclge_fd_ad_data { 756 u16 ad_id; 757 u8 drop_packet; 758 u8 forward_to_direct_queue; 759 u16 queue_id; 760 u8 use_counter; 761 u8 counter_id; 762 u8 use_next_stage; 763 u8 write_rule_id_to_bd; 764 u8 next_input_key; 765 u16 rule_id; 766 u16 tc_size; 767 u8 override_tc; 768 }; 769 770 enum HCLGE_MAC_NODE_STATE { 771 HCLGE_MAC_TO_ADD, 772 HCLGE_MAC_TO_DEL, 773 HCLGE_MAC_ACTIVE 774 }; 775 776 struct hclge_mac_node { 777 struct list_head node; 778 enum HCLGE_MAC_NODE_STATE state; 779 u8 mac_addr[ETH_ALEN]; 780 }; 781 782 enum HCLGE_MAC_ADDR_TYPE { 783 HCLGE_MAC_ADDR_UC, 784 HCLGE_MAC_ADDR_MC 785 }; 786 787 struct hclge_vport_vlan_cfg { 788 struct list_head node; 789 int hd_tbl_status; 790 u16 vlan_id; 791 }; 792 793 struct hclge_rst_stats { 794 u32 reset_done_cnt; /* the number of reset has completed */ 795 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 796 u32 pf_rst_cnt; /* the number of PF reset */ 797 u32 flr_rst_cnt; /* the number of FLR */ 798 u32 global_rst_cnt; /* the number of GLOBAL */ 799 u32 imp_rst_cnt; /* the number of IMP reset */ 800 u32 reset_cnt; /* the number of reset */ 801 u32 reset_fail_cnt; /* the number of reset fail */ 802 }; 803 804 /* time and register status when mac tunnel interruption occur */ 805 struct hclge_mac_tnl_stats { 806 u64 time; 807 u32 status; 808 }; 809 810 #define HCLGE_RESET_INTERVAL (10 * HZ) 811 #define HCLGE_WAIT_RESET_DONE 100 812 813 #pragma pack(1) 814 struct hclge_vf_vlan_cfg { 815 u8 mbx_cmd; 816 u8 subcode; 817 union { 818 struct { 819 u8 is_kill; 820 __le16 vlan; 821 __le16 proto; 822 }; 823 u8 enable; 824 }; 825 }; 826 827 #pragma pack() 828 829 /* For each bit of TCAM entry, it uses a pair of 'x' and 830 * 'y' to indicate which value to match, like below: 831 * ---------------------------------- 832 * | bit x | bit y | search value | 833 * ---------------------------------- 834 * | 0 | 0 | always hit | 835 * ---------------------------------- 836 * | 1 | 0 | match '0' | 837 * ---------------------------------- 838 * | 0 | 1 | match '1' | 839 * ---------------------------------- 840 * | 1 | 1 | invalid | 841 * ---------------------------------- 842 * Then for input key(k) and mask(v), we can calculate the value by 843 * the formulae: 844 * x = (~k) & v 845 * y = k & v 846 */ 847 #define calc_x(x, k, v) ((x) = ~(k) & (v)) 848 #define calc_y(y, k, v) ((y) = (k) & (v)) 849 850 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 851 #define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset))) 852 853 #define HCLGE_MAC_TNL_LOG_SIZE 8 854 #define HCLGE_VPORT_NUM 256 855 struct hclge_dev { 856 struct pci_dev *pdev; 857 struct hnae3_ae_dev *ae_dev; 858 struct hclge_hw hw; 859 struct hclge_misc_vector misc_vector; 860 struct hclge_mac_stats mac_stats; 861 struct hclge_fec_stats fec_stats; 862 unsigned long state; 863 unsigned long flr_state; 864 unsigned long last_reset_time; 865 866 enum hnae3_reset_type reset_type; 867 enum hnae3_reset_type reset_level; 868 unsigned long default_reset_request; 869 unsigned long reset_request; /* reset has been requested */ 870 unsigned long reset_pending; /* client rst is pending to be served */ 871 struct hclge_rst_stats rst_stats; 872 struct semaphore reset_sem; /* protect reset process */ 873 u32 fw_version; 874 u16 num_tqps; /* Num task queue pairs of this PF */ 875 u16 num_req_vfs; /* Num VFs requested for this PF */ 876 877 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 878 u16 alloc_rss_size; /* Allocated RSS task queue */ 879 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 880 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 881 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */ 882 883 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 884 u16 num_alloc_vport; /* Num vports this driver supports */ 885 u32 numa_node_mask; 886 u16 rx_buf_len; 887 u16 num_tx_desc; /* desc num of per tx queue */ 888 u16 num_rx_desc; /* desc num of per rx queue */ 889 u8 hw_tc_map; 890 enum hclge_fc_mode fc_mode_last_time; 891 u8 support_sfp_query; 892 893 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 894 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 895 u8 tx_sch_mode; 896 u8 tc_max; 897 u8 pfc_max; 898 899 u8 default_up; 900 u8 dcbx_cap; 901 struct hclge_tm_info tm_info; 902 903 u16 num_msi; 904 u16 num_msi_left; 905 u16 num_msi_used; 906 u16 *vector_status; 907 int *vector_irq; 908 u16 num_nic_msi; /* Num of nic vectors for this PF */ 909 u16 num_roce_msi; /* Num of roce vectors for this PF */ 910 911 unsigned long service_timer_period; 912 unsigned long service_timer_previous; 913 struct timer_list reset_timer; 914 struct delayed_work service_task; 915 916 bool cur_promisc; 917 int num_alloc_vfs; /* Actual number of VFs allocated */ 918 919 struct hclge_comm_tqp *htqp; 920 struct hclge_vport *vport; 921 922 struct dentry *hclge_dbgfs; 923 924 struct hnae3_client *nic_client; 925 struct hnae3_client *roce_client; 926 927 #define HCLGE_FLAG_MAIN BIT(0) 928 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 929 u32 flag; 930 931 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 932 u32 tx_buf_size; /* Tx buffer size for each TC */ 933 u32 dv_buf_size; /* Dv buffer size for each TC */ 934 935 u32 mps; /* Max packet size */ 936 /* vport_lock protect resource shared by vports */ 937 struct mutex vport_lock; 938 939 struct hclge_vlan_type_cfg vlan_type_cfg; 940 941 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 942 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 943 944 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 945 946 struct hclge_fd_cfg fd_cfg; 947 struct hlist_head fd_rule_list; 948 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 949 u16 hclge_fd_rule_num; 950 unsigned long serv_processed_cnt; 951 unsigned long last_serv_processed; 952 unsigned long last_rst_scheduled; 953 unsigned long last_mbx_scheduled; 954 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 955 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 956 u8 fd_en; 957 bool gro_en; 958 959 u16 wanted_umv_size; 960 /* max available unicast mac vlan space */ 961 u16 max_umv_size; 962 /* private unicast mac vlan space, it's same for PF and its VFs */ 963 u16 priv_umv_size; 964 /* unicast mac vlan space shared by PF and its VFs */ 965 u16 share_umv_size; 966 /* multicast mac address number used by PF and its VFs */ 967 u16 used_mc_mac_num; 968 969 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 970 HCLGE_MAC_TNL_LOG_SIZE); 971 972 struct hclge_ptp *ptp; 973 struct devlink *devlink; 974 struct hclge_comm_rss_cfg rss_cfg; 975 }; 976 977 /* VPort level vlan tag configuration for TX direction */ 978 struct hclge_tx_vtag_cfg { 979 bool accept_tag1; /* Whether accept tag1 packet from host */ 980 bool accept_untag1; /* Whether accept untag1 packet from host */ 981 bool accept_tag2; 982 bool accept_untag2; 983 bool insert_tag1_en; /* Whether insert inner vlan tag */ 984 bool insert_tag2_en; /* Whether insert outer vlan tag */ 985 u16 default_tag1; /* The default inner vlan tag to insert */ 986 u16 default_tag2; /* The default outer vlan tag to insert */ 987 bool tag_shift_mode_en; 988 }; 989 990 /* VPort level vlan tag configuration for RX direction */ 991 struct hclge_rx_vtag_cfg { 992 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 993 bool strip_tag1_en; /* Whether strip inner vlan tag */ 994 bool strip_tag2_en; /* Whether strip outer vlan tag */ 995 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 996 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 997 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 998 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 999 }; 1000 1001 enum HCLGE_VPORT_STATE { 1002 HCLGE_VPORT_STATE_ALIVE, 1003 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 1004 HCLGE_VPORT_STATE_PROMISC_CHANGE, 1005 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 1006 HCLGE_VPORT_STATE_INITED, 1007 HCLGE_VPORT_STATE_MAX 1008 }; 1009 1010 enum HCLGE_VPORT_NEED_NOTIFY { 1011 HCLGE_VPORT_NEED_NOTIFY_RESET, 1012 HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 1013 }; 1014 1015 struct hclge_vlan_info { 1016 u16 vlan_proto; /* so far support 802.1Q only */ 1017 u16 qos; 1018 u16 vlan_tag; 1019 }; 1020 1021 struct hclge_port_base_vlan_config { 1022 u16 state; 1023 bool tbl_sta; 1024 struct hclge_vlan_info vlan_info; 1025 struct hclge_vlan_info old_vlan_info; 1026 }; 1027 1028 struct hclge_vf_info { 1029 int link_state; 1030 u8 mac[ETH_ALEN]; 1031 u32 spoofchk; 1032 u32 max_tx_rate; 1033 u32 trusted; 1034 u8 request_uc_en; 1035 u8 request_mc_en; 1036 u8 request_bc_en; 1037 }; 1038 1039 struct hclge_vport { 1040 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 1041 1042 u16 qs_offset; 1043 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 1044 u8 dwrr; 1045 1046 bool req_vlan_fltr_en; 1047 bool cur_vlan_fltr_en; 1048 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1049 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1050 struct hclge_tx_vtag_cfg txvlan_cfg; 1051 struct hclge_rx_vtag_cfg rxvlan_cfg; 1052 1053 u16 used_umv_num; 1054 1055 u16 vport_id; 1056 struct hclge_dev *back; /* Back reference to associated dev */ 1057 struct hnae3_handle nic; 1058 struct hnae3_handle roce; 1059 1060 unsigned long state; 1061 unsigned long need_notify; 1062 unsigned long last_active_jiffies; 1063 u32 mps; /* Max packet size */ 1064 struct hclge_vf_info vf_info; 1065 1066 u8 overflow_promisc_flags; 1067 u8 last_promisc_flags; 1068 1069 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1070 struct list_head uc_mac_list; /* Store VF unicast table */ 1071 struct list_head mc_mac_list; /* Store VF multicast table */ 1072 1073 struct list_head vlan_list; /* Store VF vlan table */ 1074 }; 1075 1076 struct hclge_speed_bit_map { 1077 u32 speed; 1078 u32 speed_bit; 1079 }; 1080 1081 struct hclge_mac_speed_map { 1082 u32 speed_drv; /* speed defined in driver */ 1083 u32 speed_fw; /* speed defined in firmware */ 1084 }; 1085 1086 struct hclge_link_mode_bmap { 1087 u16 support_bit; 1088 enum ethtool_link_mode_bit_indices link_mode; 1089 }; 1090 1091 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1092 bool en_mc_pmc, bool en_bc_pmc); 1093 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1094 const unsigned char *addr); 1095 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1096 const unsigned char *addr); 1097 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1098 const unsigned char *addr); 1099 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1100 const unsigned char *addr); 1101 1102 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1103 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1104 int vector_id, bool en, 1105 struct hnae3_ring_chain_node *ring_chain); 1106 1107 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1108 { 1109 struct hclge_comm_tqp *tqp = 1110 container_of(queue, struct hclge_comm_tqp, q); 1111 1112 return tqp->index; 1113 } 1114 1115 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1116 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num); 1117 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1118 u16 vlan_id, bool is_kill); 1119 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1120 1121 int hclge_buffer_alloc(struct hclge_dev *hdev); 1122 int hclge_rss_init_hw(struct hclge_dev *hdev); 1123 1124 void hclge_mbx_handler(struct hclge_dev *hdev); 1125 int hclge_reset_tqp(struct hnae3_handle *handle); 1126 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1127 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1128 int hclge_vport_start(struct hclge_vport *vport); 1129 void hclge_vport_stop(struct hclge_vport *vport); 1130 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1131 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1132 char *buf, int len); 1133 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1134 int hclge_notify_client(struct hclge_dev *hdev, 1135 enum hnae3_reset_notify_type type); 1136 int hclge_update_mac_list(struct hclge_vport *vport, 1137 enum HCLGE_MAC_NODE_STATE state, 1138 enum HCLGE_MAC_ADDR_TYPE mac_type, 1139 const unsigned char *addr); 1140 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1141 const u8 *old_addr, const u8 *new_addr); 1142 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1143 enum HCLGE_MAC_ADDR_TYPE mac_type); 1144 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1145 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1146 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1147 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev); 1148 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1149 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1150 struct hclge_vlan_info *vlan_info); 1151 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1152 u16 state, 1153 struct hclge_vlan_info *vlan_info); 1154 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1155 void hclge_report_hw_error(struct hclge_dev *hdev, 1156 enum hnae3_hw_error_type type); 1157 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1158 int hclge_push_vf_link_status(struct hclge_vport *vport); 1159 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1160 int hclge_mac_update_stats(struct hclge_dev *hdev); 1161 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf); 1162 int hclge_inform_vf_reset(struct hclge_vport *vport, u16 reset_type); 1163 #endif 1164