xref: /linux/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi (revision 3d0fe49454652117522f60bfbefb978ba0e5300b)
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Device Tree Source for Sierra Wireless WP8548 Module
4 *
5 * Copyright (C) 2016 BayLibre, SAS.
6 * Author : Neil Armstrong <narmstrong@baylibre.com>
7 */
8
9#include "qcom-mdm9615.dtsi"
10
11/ {
12	model = "Sierra Wireless WP8548 Module";
13	compatible = "swir,wp8548", "qcom,mdm9615";
14
15	memory@48000000 {
16		device_type = "memory";
17		reg = <0x48000000 0x7F00000>;
18	};
19};
20
21&msmgpio {
22	pinctrl-0 = <&reset_out_pins>;
23	pinctrl-names = "default";
24
25	gsbi3_pins: gsbi3-state {
26		gsbi3-pins {
27			pins = "gpio8", "gpio9", "gpio10", "gpio11";
28			function = "gsbi3";
29			drive-strength = <8>;
30			bias-disable;
31		};
32	};
33
34	gsbi4_pins: gsbi4-state {
35		gsbi4-pins {
36			pins = "gpio12", "gpio13", "gpio14", "gpio15";
37			function = "gsbi4";
38			drive-strength = <8>;
39			bias-disable;
40		};
41	};
42
43	gsbi5_i2c_pins: gsbi5-i2c-state {
44		sda-pins {
45			pins = "gpio16";
46			function = "gsbi5_i2c";
47			drive-strength = <8>;
48			bias-disable;
49		};
50
51		scl-pins {
52			pins = "gpio17";
53			function = "gsbi5_i2c";
54			drive-strength = <2>;
55			bias-disable;
56		};
57	};
58
59	gsbi5_uart_pins: gsbi5-uart-state {
60		gsbi5-uart-pins {
61			pins = "gpio18", "gpio19";
62			function = "gsbi5_uart";
63			drive-strength = <8>;
64			bias-disable;
65		};
66	};
67
68	reset_out_pins: reset-out-state {
69		reset-out-pins {
70			pins = "gpio66";
71			function = "gpio";
72			drive-strength = <2>;
73			bias-pull-up;
74			output-high;
75		};
76	};
77};
78
79&pmicgpio {
80	usb_vbus_5v_pins: usb-vbus-5v-state {
81		pins = "gpio4";
82		function = "normal";
83		output-high;
84		bias-disable;
85		qcom,drive-strength = <1>;
86		power-source = <2>;
87	};
88};
89
90&gsbi3 {
91	status = "okay";
92	qcom,mode = <GSBI_PROT_SPI>;
93};
94
95&gsbi3_spi {
96	status = "okay";
97	pinctrl-0 = <&gsbi3_pins>;
98	pinctrl-names = "default";
99	assigned-clocks = <&gcc GSBI3_QUP_CLK>;
100	assigned-clock-rates = <24000000>;
101};
102
103&gsbi4 {
104	status = "okay";
105	qcom,mode = <GSBI_PROT_UART_W_FC>;
106};
107
108&gsbi4_serial {
109	status = "okay";
110	pinctrl-0 = <&gsbi4_pins>;
111	pinctrl-names = "default";
112};
113
114&gsbi5 {
115	status = "okay";
116	qcom,mode = <GSBI_PROT_I2C_UART>;
117};
118
119&gsbi5_i2c {
120	status = "okay";
121	clock-frequency = <200000>;
122	pinctrl-0 = <&gsbi5_i2c_pins>;
123	pinctrl-names = "default";
124};
125
126&gsbi5_serial {
127	status = "okay";
128	pinctrl-0 = <&gsbi5_uart_pins>;
129	pinctrl-names = "default";
130};
131
132&sdcc1 {
133	status = "okay";
134};
135