1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SoM: https://www.ti.com/lit/zip/sprr439 4 * 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/dts-v1/; 9 10#include "k3-j721s2.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 memory@80000000 { 15 device_type = "memory"; 16 /* 16 GB RAM */ 17 reg = <0x00 0x80000000 0x00 0x80000000>, 18 <0x08 0x80000000 0x03 0x80000000>; 19 }; 20 21 /* Reserving memory regions still pending */ 22 reserved_memory: reserved-memory { 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 27 secure_ddr: optee@9e800000 { 28 reg = <0x00 0x9e800000 0x00 0x01800000>; 29 alignment = <0x1000>; 30 no-map; 31 }; 32 33 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 34 compatible = "shared-dma-pool"; 35 reg = <0x00 0xa0000000 0x00 0x100000>; 36 no-map; 37 }; 38 39 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 40 compatible = "shared-dma-pool"; 41 reg = <0x00 0xa0100000 0x00 0xf00000>; 42 no-map; 43 }; 44 45 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 46 compatible = "shared-dma-pool"; 47 reg = <0x00 0xa1000000 0x00 0x100000>; 48 no-map; 49 }; 50 51 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 52 compatible = "shared-dma-pool"; 53 reg = <0x00 0xa1100000 0x00 0xf00000>; 54 no-map; 55 }; 56 57 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 58 compatible = "shared-dma-pool"; 59 reg = <0x00 0xa2000000 0x00 0x100000>; 60 no-map; 61 }; 62 63 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 64 compatible = "shared-dma-pool"; 65 reg = <0x00 0xa2100000 0x00 0xf00000>; 66 no-map; 67 }; 68 69 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 70 compatible = "shared-dma-pool"; 71 reg = <0x00 0xa3000000 0x00 0x100000>; 72 no-map; 73 }; 74 75 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 76 compatible = "shared-dma-pool"; 77 reg = <0x00 0xa3100000 0x00 0xf00000>; 78 no-map; 79 }; 80 81 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 82 compatible = "shared-dma-pool"; 83 reg = <0x00 0xa4000000 0x00 0x100000>; 84 no-map; 85 }; 86 87 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 88 compatible = "shared-dma-pool"; 89 reg = <0x00 0xa4100000 0x00 0xf00000>; 90 no-map; 91 }; 92 93 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 94 compatible = "shared-dma-pool"; 95 reg = <0x00 0xa5000000 0x00 0x100000>; 96 no-map; 97 }; 98 99 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 100 compatible = "shared-dma-pool"; 101 reg = <0x00 0xa5100000 0x00 0xf00000>; 102 no-map; 103 }; 104 105 c71_0_dma_memory_region: c71-dma-memory@a6000000 { 106 compatible = "shared-dma-pool"; 107 reg = <0x00 0xa6000000 0x00 0x100000>; 108 no-map; 109 }; 110 111 c71_0_memory_region: c71-memory@a6100000 { 112 compatible = "shared-dma-pool"; 113 reg = <0x00 0xa6100000 0x00 0xf00000>; 114 no-map; 115 }; 116 117 c71_1_dma_memory_region: c71-dma-memory@a7000000 { 118 compatible = "shared-dma-pool"; 119 reg = <0x00 0xa7000000 0x00 0x100000>; 120 no-map; 121 }; 122 123 c71_1_memory_region: c71-memory@a7100000 { 124 compatible = "shared-dma-pool"; 125 reg = <0x00 0xa7100000 0x00 0xf00000>; 126 no-map; 127 }; 128 129 rtos_ipc_memory_region: ipc-memories@a8000000 { 130 reg = <0x00 0xa8000000 0x00 0x01c00000>; 131 alignment = <0x1000>; 132 no-map; 133 }; 134 }; 135 136 mux0: mux-controller { 137 compatible = "gpio-mux"; 138 #mux-state-cells = <1>; 139 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; 140 }; 141 142 mux1: mux-controller { 143 compatible = "gpio-mux"; 144 #mux-state-cells = <1>; 145 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; 146 }; 147 148 transceiver0: can-phy0 { 149 /* standby pin has been grounded by default */ 150 compatible = "ti,tcan1042"; 151 #phy-cells = <0>; 152 max-bitrate = <5000000>; 153 }; 154}; 155 156&wkup_pmx0 { 157 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 158 pinctrl-single,pins = < 159 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ 160 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ 161 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ 162 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ 163 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ 164 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ 165 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ 166 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ 167 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ 168 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ 169 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ 170 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ 171 >; 172 }; 173}; 174 175&wkup_pmx2 { 176 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 177 pinctrl-single,pins = < 178 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ 179 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ 180 >; 181 }; 182}; 183 184&main_pmx0 { 185 main_i2c0_pins_default: main-i2c0-default-pins { 186 pinctrl-single,pins = < 187 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ 188 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ 189 >; 190 }; 191 192 main_mcan16_pins_default: main-mcan16-default-pins { 193 pinctrl-single,pins = < 194 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ 195 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ 196 >; 197 }; 198}; 199 200&wkup_i2c0 { 201 status = "okay"; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&wkup_i2c0_pins_default>; 204 clock-frequency = <400000>; 205 206 eeprom@50 { 207 /* CAV24C256WE-GT3 */ 208 compatible = "atmel,24c256"; 209 reg = <0x50>; 210 }; 211}; 212 213&main_i2c0 { 214 status = "okay"; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&main_i2c0_pins_default>; 217 clock-frequency = <400000>; 218 219 exp_som: gpio@21 { 220 compatible = "ti,tca6408"; 221 reg = <0x21>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", 225 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", 226 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE", 227 "GPIO_LIN_EN", "CAN_STB"; 228 }; 229}; 230 231&main_mcan16 { 232 status = "okay"; 233 pinctrl-0 = <&main_mcan16_pins_default>; 234 pinctrl-names = "default"; 235 phys = <&transceiver0>; 236}; 237 238&ospi0 { 239 status = "okay"; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 242 243 flash@0 { 244 compatible = "jedec,spi-nor"; 245 reg = <0x0>; 246 spi-tx-bus-width = <8>; 247 spi-rx-bus-width = <8>; 248 spi-max-frequency = <25000000>; 249 cdns,tshsl-ns = <60>; 250 cdns,tsd2d-ns = <60>; 251 cdns,tchsh-ns = <60>; 252 cdns,tslch-ns = <60>; 253 cdns,read-delay = <4>; 254 }; 255}; 256 257&mailbox0_cluster0 { 258 status = "okay"; 259 interrupts = <436>; 260 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 261 ti,mbox-rx = <0 0 0>; 262 ti,mbox-tx = <1 0 0>; 263 }; 264 265 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 266 ti,mbox-rx = <2 0 0>; 267 ti,mbox-tx = <3 0 0>; 268 }; 269}; 270 271&mailbox0_cluster1 { 272 status = "okay"; 273 interrupts = <432>; 274 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 275 ti,mbox-rx = <0 0 0>; 276 ti,mbox-tx = <1 0 0>; 277 }; 278 279 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 280 ti,mbox-rx = <2 0 0>; 281 ti,mbox-tx = <3 0 0>; 282 }; 283}; 284 285&mailbox0_cluster2 { 286 status = "okay"; 287 interrupts = <428>; 288 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 289 ti,mbox-rx = <0 0 0>; 290 ti,mbox-tx = <1 0 0>; 291 }; 292 293 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 294 ti,mbox-rx = <2 0 0>; 295 ti,mbox-tx = <3 0 0>; 296 }; 297}; 298 299&mailbox0_cluster4 { 300 status = "okay"; 301 interrupts = <420>; 302 mbox_c71_0: mbox-c71-0 { 303 ti,mbox-rx = <0 0 0>; 304 ti,mbox-tx = <1 0 0>; 305 }; 306 307 mbox_c71_1: mbox-c71-1 { 308 ti,mbox-rx = <2 0 0>; 309 ti,mbox-tx = <3 0 0>; 310 }; 311}; 312 313&mcu_r5fss0_core0 { 314 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; 315 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 316 <&mcu_r5fss0_core0_memory_region>; 317}; 318 319&mcu_r5fss0_core1 { 320 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; 321 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 322 <&mcu_r5fss0_core1_memory_region>; 323}; 324 325&main_r5fss0_core0 { 326 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; 327 memory-region = <&main_r5fss0_core0_dma_memory_region>, 328 <&main_r5fss0_core0_memory_region>; 329}; 330 331&main_r5fss0_core1 { 332 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; 333 memory-region = <&main_r5fss0_core1_dma_memory_region>, 334 <&main_r5fss0_core1_memory_region>; 335}; 336 337&main_r5fss1_core0 { 338 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; 339 memory-region = <&main_r5fss1_core0_dma_memory_region>, 340 <&main_r5fss1_core0_memory_region>; 341}; 342 343&main_r5fss1_core1 { 344 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; 345 memory-region = <&main_r5fss1_core1_dma_memory_region>, 346 <&main_r5fss1_core1_memory_region>; 347}; 348 349&c71_0 { 350 status = "okay"; 351 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; 352 memory-region = <&c71_0_dma_memory_region>, 353 <&c71_0_memory_region>; 354}; 355 356&c71_1 { 357 status = "okay"; 358 mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; 359 memory-region = <&c71_1_dma_memory_region>, 360 <&c71_1_memory_region>; 361}; 362