xref: /linux/arch/arm/include/asm/pgtable.h (revision 3d0fe49454652117522f60bfbefb978ba0e5300b) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  arch/arm/include/asm/pgtable.h
4  *
5  *  Copyright (C) 1995-2002 Russell King
6  */
7 #ifndef _ASMARM_PGTABLE_H
8 #define _ASMARM_PGTABLE_H
9 
10 #include <linux/const.h>
11 #include <asm/proc-fns.h>
12 
13 #ifndef __ASSEMBLY__
14 /*
15  * ZERO_PAGE is a global shared page that is always zero: used
16  * for zero-mapped memory areas etc..
17  */
18 extern struct page *empty_zero_page;
19 #define ZERO_PAGE(vaddr)	(empty_zero_page)
20 #endif
21 
22 #ifndef CONFIG_MMU
23 
24 #include <asm-generic/pgtable-nopud.h>
25 #include <asm/pgtable-nommu.h>
26 
27 #else
28 
29 #include <asm-generic/pgtable-nopud.h>
30 #include <asm/page.h>
31 #include <asm/pgtable-hwdef.h>
32 
33 
34 #include <asm/tlbflush.h>
35 
36 #ifdef CONFIG_ARM_LPAE
37 #include <asm/pgtable-3level.h>
38 #else
39 #include <asm/pgtable-2level.h>
40 #endif
41 
42 /*
43  * Just any arbitrary offset to the start of the vmalloc VM area: the
44  * current 8MB value just means that there will be a 8MB "hole" after the
45  * physical memory until the kernel virtual memory starts.  That means that
46  * any out-of-bounds memory accesses will hopefully be caught.
47  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
48  * area for the same reason. ;)
49  */
50 #define VMALLOC_OFFSET		(8*1024*1024)
51 #define VMALLOC_START		(((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
52 #define VMALLOC_END		0xff800000UL
53 
54 #define LIBRARY_TEXT_START	0x0c000000
55 
56 #ifndef __ASSEMBLY__
57 extern void __pte_error(const char *file, int line, pte_t);
58 extern void __pmd_error(const char *file, int line, pmd_t);
59 extern void __pgd_error(const char *file, int line, pgd_t);
60 
61 #define pte_ERROR(pte)		__pte_error(__FILE__, __LINE__, pte)
62 #define pmd_ERROR(pmd)		__pmd_error(__FILE__, __LINE__, pmd)
63 #define pgd_ERROR(pgd)		__pgd_error(__FILE__, __LINE__, pgd)
64 
65 /*
66  * This is the lowest virtual address we can permit any user space
67  * mapping to be mapped at.  This is particularly important for
68  * non-high vector CPUs.
69  */
70 #define FIRST_USER_ADDRESS	(PAGE_SIZE * 2)
71 
72 /*
73  * Use TASK_SIZE as the ceiling argument for free_pgtables() and
74  * free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
75  * page shared between user and kernel).
76  */
77 #ifdef CONFIG_ARM_LPAE
78 #define USER_PGTABLES_CEILING	TASK_SIZE
79 #endif
80 
81 /*
82  * The pgprot_* and protection_map entries will be fixed up in runtime
83  * to include the cachable and bufferable bits based on memory policy,
84  * as well as any architecture dependent bits like global/ASID and SMP
85  * shared mapping bits.
86  */
87 #define _L_PTE_DEFAULT	L_PTE_PRESENT | L_PTE_YOUNG
88 
89 extern pgprot_t		pgprot_user;
90 extern pgprot_t		pgprot_kernel;
91 
92 #define _MOD_PROT(p, b)	__pgprot(pgprot_val(p) | (b))
93 
94 #define PAGE_NONE		_MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY | L_PTE_NONE)
95 #define PAGE_SHARED		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
96 #define PAGE_SHARED_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER)
97 #define PAGE_COPY		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
98 #define PAGE_COPY_EXEC		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
99 #define PAGE_READONLY		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
100 #define PAGE_READONLY_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
101 #define PAGE_KERNEL		_MOD_PROT(pgprot_kernel, L_PTE_XN)
102 #define PAGE_KERNEL_EXEC	pgprot_kernel
103 
104 #define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
105 #define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
106 #define __PAGE_SHARED_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER)
107 #define __PAGE_COPY		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
108 #define __PAGE_COPY_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
109 #define __PAGE_READONLY		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
110 #define __PAGE_READONLY_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
111 
112 #define __pgprot_modify(prot,mask,bits)		\
113 	__pgprot((pgprot_val(prot) & ~(mask)) | (bits))
114 
115 #define pgprot_noncached(prot) \
116 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
117 
118 #define pgprot_writecombine(prot) \
119 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
120 
121 #define pgprot_stronglyordered(prot) \
122 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
123 
124 #define pgprot_device(prot) \
125 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)
126 
127 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
128 #define pgprot_dmacoherent(prot) \
129 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
130 #define __HAVE_PHYS_MEM_ACCESS_PROT
131 struct file;
132 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
133 				     unsigned long size, pgprot_t vma_prot);
134 #else
135 #define pgprot_dmacoherent(prot) \
136 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
137 #endif
138 
139 #endif /* __ASSEMBLY__ */
140 
141 /*
142  * The table below defines the page protection levels that we insert into our
143  * Linux page table version.  These get translated into the best that the
144  * architecture can perform.  Note that on most ARM hardware:
145  *  1) We cannot do execute protection
146  *  2) If we could do execute protection, then read is implied
147  *  3) write implies read permissions
148  */
149 
150 #ifndef __ASSEMBLY__
151 
152 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
153 
154 #define pud_page(pud)		pmd_page(__pmd(pud_val(pud)))
155 #define pud_write(pud)		pmd_write(__pmd(pud_val(pud)))
156 
157 #define pmd_none(pmd)		(!pmd_val(pmd))
158 
159 static inline pte_t *pmd_page_vaddr(pmd_t pmd)
160 {
161 	return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
162 }
163 
164 #define pmd_page(pmd)		pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
165 
166 #define pte_pfn(pte)		((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
167 #define pfn_pte(pfn,prot)	__pte(__pfn_to_phys(pfn) | pgprot_val(prot))
168 
169 #define pte_page(pte)		pfn_to_page(pte_pfn(pte))
170 #define mk_pte(page,prot)	pfn_pte(page_to_pfn(page), prot)
171 
172 #define pte_clear(mm,addr,ptep)	set_pte_ext(ptep, __pte(0), 0)
173 
174 #define pte_isset(pte, val)	((u32)(val) == (val) ? pte_val(pte) & (val) \
175 						: !!(pte_val(pte) & (val)))
176 #define pte_isclear(pte, val)	(!(pte_val(pte) & (val)))
177 
178 #define pte_none(pte)		(!pte_val(pte))
179 #define pte_present(pte)	(pte_isset((pte), L_PTE_PRESENT))
180 #define pte_valid(pte)		(pte_isset((pte), L_PTE_VALID))
181 #define pte_accessible(mm, pte)	(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
182 #define pte_write(pte)		(pte_isclear((pte), L_PTE_RDONLY))
183 #define pte_dirty(pte)		(pte_isset((pte), L_PTE_DIRTY))
184 #define pte_young(pte)		(pte_isset((pte), L_PTE_YOUNG))
185 #define pte_exec(pte)		(pte_isclear((pte), L_PTE_XN))
186 
187 #define pte_valid_user(pte)	\
188 	(pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
189 
190 static inline bool pte_access_permitted(pte_t pte, bool write)
191 {
192 	pteval_t mask = L_PTE_PRESENT | L_PTE_USER;
193 	pteval_t needed = mask;
194 
195 	if (write)
196 		mask |= L_PTE_RDONLY;
197 
198 	return (pte_val(pte) & mask) == needed;
199 }
200 #define pte_access_permitted pte_access_permitted
201 
202 #if __LINUX_ARM_ARCH__ < 6
203 static inline void __sync_icache_dcache(pte_t pteval)
204 {
205 }
206 #else
207 extern void __sync_icache_dcache(pte_t pteval);
208 #endif
209 
210 void set_ptes(struct mm_struct *mm, unsigned long addr,
211 		      pte_t *ptep, pte_t pteval, unsigned int nr);
212 #define set_ptes set_ptes
213 
214 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
215 {
216 	pte_val(pte) &= ~pgprot_val(prot);
217 	return pte;
218 }
219 
220 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
221 {
222 	pte_val(pte) |= pgprot_val(prot);
223 	return pte;
224 }
225 
226 static inline pte_t pte_wrprotect(pte_t pte)
227 {
228 	return set_pte_bit(pte, __pgprot(L_PTE_RDONLY));
229 }
230 
231 static inline pte_t pte_mkwrite_novma(pte_t pte)
232 {
233 	return clear_pte_bit(pte, __pgprot(L_PTE_RDONLY));
234 }
235 
236 static inline pte_t pte_mkclean(pte_t pte)
237 {
238 	return clear_pte_bit(pte, __pgprot(L_PTE_DIRTY));
239 }
240 
241 static inline pte_t pte_mkdirty(pte_t pte)
242 {
243 	return set_pte_bit(pte, __pgprot(L_PTE_DIRTY));
244 }
245 
246 static inline pte_t pte_mkold(pte_t pte)
247 {
248 	return clear_pte_bit(pte, __pgprot(L_PTE_YOUNG));
249 }
250 
251 static inline pte_t pte_mkyoung(pte_t pte)
252 {
253 	return set_pte_bit(pte, __pgprot(L_PTE_YOUNG));
254 }
255 
256 static inline pte_t pte_mkexec(pte_t pte)
257 {
258 	return clear_pte_bit(pte, __pgprot(L_PTE_XN));
259 }
260 
261 static inline pte_t pte_mknexec(pte_t pte)
262 {
263 	return set_pte_bit(pte, __pgprot(L_PTE_XN));
264 }
265 
266 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
267 {
268 	const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
269 		L_PTE_NONE | L_PTE_VALID;
270 	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
271 	return pte;
272 }
273 
274 /*
275  * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
276  * are !pte_none() && !pte_present().
277  *
278  * Format of swap PTEs:
279  *
280  *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
281  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
282  *   <------------------- offset ------------------> E < type -> 0 0
283  *
284  *   E is the exclusive marker that is not stored in swap entries.
285  *
286  * This gives us up to 31 swap files and 64GB per swap file.  Note that
287  * the offset field is always non-zero.
288  */
289 #define __SWP_TYPE_SHIFT	2
290 #define __SWP_TYPE_BITS		5
291 #define __SWP_TYPE_MASK		((1 << __SWP_TYPE_BITS) - 1)
292 #define __SWP_OFFSET_SHIFT	(__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1)
293 
294 #define __swp_type(x)		(((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
295 #define __swp_offset(x)		((x).val >> __SWP_OFFSET_SHIFT)
296 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
297 						   ((offset) << __SWP_OFFSET_SHIFT) })
298 
299 #define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
300 #define __swp_entry_to_pte(swp)	__pte((swp).val)
301 
302 static inline int pte_swp_exclusive(pte_t pte)
303 {
304 	return pte_isset(pte, L_PTE_SWP_EXCLUSIVE);
305 }
306 
307 static inline pte_t pte_swp_mkexclusive(pte_t pte)
308 {
309 	return set_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
310 }
311 
312 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
313 {
314 	return clear_pte_bit(pte, __pgprot(L_PTE_SWP_EXCLUSIVE));
315 }
316 
317 /*
318  * It is an error for the kernel to have more swap files than we can
319  * encode in the PTEs.  This ensures that we know when MAX_SWAPFILES
320  * is increased beyond what we presently support.
321  */
322 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
323 
324 /*
325  * We provide our own arch_get_unmapped_area to cope with VIPT caches.
326  */
327 #define HAVE_ARCH_UNMAPPED_AREA
328 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
329 
330 #endif /* !__ASSEMBLY__ */
331 
332 #endif /* CONFIG_MMU */
333 
334 #endif /* _ASMARM_PGTABLE_H */
335