xref: /linux/Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g5-eic.yaml (revision 3d0fe49454652117522f60bfbefb978ba0e5300b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip External Interrupt Controller
8
9maintainers:
10  - Claudiu Beznea <claudiu.beznea@microchip.com>
11
12description:
13  This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
14  support for handling up to 2 external interrupt lines.
15
16properties:
17  compatible:
18    enum:
19      - microchip,sama7g5-eic
20
21  reg:
22    maxItems: 1
23
24  interrupt-controller: true
25
26  '#interrupt-cells':
27    const: 2
28    description:
29      The first cell is the input IRQ number (between 0 and 1), the second cell
30      is the trigger type as defined in interrupt.txt present in this directory.
31
32  interrupts:
33    description: |
34      Contains the GIC SPI IRQs mapped to the external interrupt lines. They
35      should be specified sequentially from output 0 to output 1.
36    minItems: 2
37    maxItems: 2
38
39  clocks:
40    maxItems: 1
41
42  clock-names:
43    const: pclk
44
45required:
46  - compatible
47  - reg
48  - interrupt-controller
49  - '#interrupt-cells'
50  - interrupts
51  - clocks
52  - clock-names
53
54additionalProperties: false
55
56examples:
57  - |
58    #include <dt-bindings/clock/at91.h>
59    #include <dt-bindings/interrupt-controller/arm-gic.h>
60
61    eic: interrupt-controller@e1628000 {
62      compatible = "microchip,sama7g5-eic";
63      reg = <0xe1628000 0x100>;
64      interrupt-parent = <&gic>;
65      interrupt-controller;
66      #interrupt-cells = <2>;
67      interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
68                   <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
69      clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
70      clock-names = "pclk";
71    };
72
73...
74