1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH11K_CORE_H 8 #define ATH11K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/rhashtable.h> 17 #include <linux/average.h> 18 #include <linux/firmware.h> 19 20 #include "qmi.h" 21 #include "htc.h" 22 #include "wmi.h" 23 #include "hal.h" 24 #include "dp.h" 25 #include "ce.h" 26 #include "mac.h" 27 #include "hw.h" 28 #include "hal_rx.h" 29 #include "reg.h" 30 #include "thermal.h" 31 #include "dbring.h" 32 #include "spectral.h" 33 #include "wow.h" 34 #include "fw.h" 35 36 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 37 38 #define ATH11K_TX_MGMT_NUM_PENDING_MAX 512 39 40 #define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 41 42 /* Pending management packets threshold for dropping probe responses */ 43 #define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 44 45 #define ATH11K_INVALID_HW_MAC_ID 0xFF 46 #define ATH11K_CONNECTION_LOSS_HZ (3 * HZ) 47 48 /* SMBIOS type containing Board Data File Name Extension */ 49 #define ATH11K_SMBIOS_BDF_EXT_TYPE 0xF8 50 51 /* SMBIOS type structure length (excluding strings-set) */ 52 #define ATH11K_SMBIOS_BDF_EXT_LENGTH 0x9 53 54 /* The magic used by QCA spec */ 55 #define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_" 56 57 extern unsigned int ath11k_frame_mode; 58 extern bool ath11k_ftm_mode; 59 60 #define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ) 61 62 #define ATH11K_MON_TIMER_INTERVAL 10 63 #define ATH11K_RESET_TIMEOUT_HZ (20 * HZ) 64 #define ATH11K_RESET_MAX_FAIL_COUNT_FIRST 3 65 #define ATH11K_RESET_MAX_FAIL_COUNT_FINAL 5 66 #define ATH11K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 67 #define ATH11K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 68 #define ATH11K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 69 70 enum ath11k_supported_bw { 71 ATH11K_BW_20 = 0, 72 ATH11K_BW_40 = 1, 73 ATH11K_BW_80 = 2, 74 ATH11K_BW_160 = 3, 75 }; 76 77 enum ath11k_bdf_search { 78 ATH11K_BDF_SEARCH_DEFAULT, 79 ATH11K_BDF_SEARCH_BUS_AND_BOARD, 80 }; 81 82 enum wme_ac { 83 WME_AC_BE, 84 WME_AC_BK, 85 WME_AC_VI, 86 WME_AC_VO, 87 WME_NUM_AC 88 }; 89 90 #define ATH11K_HT_MCS_MAX 7 91 #define ATH11K_VHT_MCS_MAX 9 92 #define ATH11K_HE_MCS_MAX 11 93 94 enum ath11k_crypt_mode { 95 /* Only use hardware crypto engine */ 96 ATH11K_CRYPT_MODE_HW, 97 /* Only use software crypto */ 98 ATH11K_CRYPT_MODE_SW, 99 }; 100 101 static inline enum wme_ac ath11k_tid_to_ac(u32 tid) 102 { 103 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 104 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 105 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 106 WME_AC_VO); 107 } 108 109 enum ath11k_skb_flags { 110 ATH11K_SKB_HW_80211_ENCAP = BIT(0), 111 ATH11K_SKB_CIPHER_SET = BIT(1), 112 }; 113 114 struct ath11k_skb_cb { 115 dma_addr_t paddr; 116 u8 eid; 117 u8 flags; 118 u32 cipher; 119 struct ath11k *ar; 120 struct ieee80211_vif *vif; 121 } __packed; 122 123 struct ath11k_skb_rxcb { 124 dma_addr_t paddr; 125 bool is_first_msdu; 126 bool is_last_msdu; 127 bool is_continuation; 128 bool is_mcbc; 129 bool is_eapol; 130 struct hal_rx_desc *rx_desc; 131 u8 err_rel_src; 132 u8 err_code; 133 u8 mac_id; 134 u8 unmapped; 135 u8 is_frag; 136 u8 tid; 137 u16 peer_id; 138 u16 seq_no; 139 }; 140 141 enum ath11k_hw_rev { 142 ATH11K_HW_IPQ8074, 143 ATH11K_HW_QCA6390_HW20, 144 ATH11K_HW_IPQ6018_HW10, 145 ATH11K_HW_QCN9074_HW10, 146 ATH11K_HW_WCN6855_HW20, 147 ATH11K_HW_WCN6855_HW21, 148 ATH11K_HW_WCN6750_HW10, 149 ATH11K_HW_IPQ5018_HW10, 150 }; 151 152 enum ath11k_firmware_mode { 153 /* the default mode, standard 802.11 functionality */ 154 ATH11K_FIRMWARE_MODE_NORMAL, 155 156 /* factory tests etc */ 157 ATH11K_FIRMWARE_MODE_FTM, 158 159 /* Cold boot calibration */ 160 ATH11K_FIRMWARE_MODE_COLD_BOOT = 7, 161 }; 162 163 extern bool ath11k_cold_boot_cal; 164 165 #define ATH11K_IRQ_NUM_MAX 52 166 #define ATH11K_EXT_IRQ_NUM_MAX 16 167 168 struct ath11k_ext_irq_grp { 169 struct ath11k_base *ab; 170 u32 irqs[ATH11K_EXT_IRQ_NUM_MAX]; 171 u32 num_irq; 172 u32 grp_id; 173 u64 timestamp; 174 bool napi_enabled; 175 struct napi_struct napi; 176 struct net_device napi_ndev; 177 }; 178 179 enum ath11k_smbios_cc_type { 180 /* disable country code setting from SMBIOS */ 181 ATH11K_SMBIOS_CC_DISABLE = 0, 182 183 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */ 184 ATH11K_SMBIOS_CC_ISO = 1, 185 186 /* worldwide regdomain */ 187 ATH11K_SMBIOS_CC_WW = 2, 188 }; 189 190 struct ath11k_smbios_bdf { 191 struct dmi_header hdr; 192 193 u8 features_disabled; 194 195 /* enum ath11k_smbios_cc_type */ 196 u8 country_code_flag; 197 198 /* To set specific country, you need to set country code 199 * flag=ATH11K_SMBIOS_CC_ISO first, then if country is United 200 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'= 201 * 0x53). To set country to INDONESIA, then country code value = 202 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag = 203 * ATH11K_SMBIOS_CC_WW, then you can use worldwide regulatory 204 * setting. 205 */ 206 u16 cc_code; 207 208 u8 bdf_enabled; 209 u8 bdf_ext[]; 210 } __packed; 211 212 #define HEHANDLE_CAP_PHYINFO_SIZE 3 213 #define HECAP_PHYINFO_SIZE 9 214 #define HECAP_MACINFO_SIZE 5 215 #define HECAP_TXRX_MCS_NSS_SIZE 2 216 #define HECAP_PPET16_PPET8_MAX_SIZE 25 217 218 #define HE_PPET16_PPET8_SIZE 8 219 220 /* 802.11ax PPE (PPDU packet Extension) threshold */ 221 struct he_ppe_threshold { 222 u32 numss_m1; 223 u32 ru_mask; 224 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 225 }; 226 227 struct ath11k_he { 228 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 229 u32 hecap_rxmcsnssmap; 230 u32 hecap_txmcsnssmap; 231 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 232 struct he_ppe_threshold hecap_ppet; 233 u32 heop_param; 234 }; 235 236 #define MAX_RADIOS 3 237 238 /* ipq5018 hw param macros */ 239 #define MAX_RADIOS_5018 1 240 #define CE_CNT_5018 6 241 #define TARGET_CE_CNT_5018 9 242 #define SVC_CE_MAP_LEN_5018 17 243 #define RXDMA_PER_PDEV_5018 1 244 245 enum { 246 WMI_HOST_TP_SCALE_MAX = 0, 247 WMI_HOST_TP_SCALE_50 = 1, 248 WMI_HOST_TP_SCALE_25 = 2, 249 WMI_HOST_TP_SCALE_12 = 3, 250 WMI_HOST_TP_SCALE_MIN = 4, 251 WMI_HOST_TP_SCALE_SIZE = 5, 252 }; 253 254 enum ath11k_scan_state { 255 ATH11K_SCAN_IDLE, 256 ATH11K_SCAN_STARTING, 257 ATH11K_SCAN_RUNNING, 258 ATH11K_SCAN_ABORTING, 259 }; 260 261 enum ath11k_11d_state { 262 ATH11K_11D_IDLE, 263 ATH11K_11D_PREPARING, 264 ATH11K_11D_RUNNING, 265 }; 266 267 enum ath11k_dev_flags { 268 ATH11K_CAC_RUNNING, 269 ATH11K_FLAG_CORE_REGISTERED, 270 ATH11K_FLAG_CRASH_FLUSH, 271 ATH11K_FLAG_RAW_MODE, 272 ATH11K_FLAG_HW_CRYPTO_DISABLED, 273 ATH11K_FLAG_BTCOEX, 274 ATH11K_FLAG_RECOVERY, 275 ATH11K_FLAG_UNREGISTERING, 276 ATH11K_FLAG_REGISTERED, 277 ATH11K_FLAG_QMI_FAIL, 278 ATH11K_FLAG_HTC_SUSPEND_COMPLETE, 279 ATH11K_FLAG_CE_IRQ_ENABLED, 280 ATH11K_FLAG_EXT_IRQ_ENABLED, 281 ATH11K_FLAG_FIXED_MEM_RGN, 282 ATH11K_FLAG_DEVICE_INIT_DONE, 283 ATH11K_FLAG_MULTI_MSI_VECTORS, 284 ATH11K_FLAG_FTM_SEGMENTED, 285 }; 286 287 enum ath11k_monitor_flags { 288 ATH11K_FLAG_MONITOR_CONF_ENABLED, 289 ATH11K_FLAG_MONITOR_STARTED, 290 ATH11K_FLAG_MONITOR_VDEV_CREATED, 291 }; 292 293 #define ATH11K_IPV6_UC_TYPE 0 294 #define ATH11K_IPV6_AC_TYPE 1 295 296 #define ATH11K_IPV6_MAX_COUNT 16 297 #define ATH11K_IPV4_MAX_COUNT 2 298 299 struct ath11k_arp_ns_offload { 300 u8 ipv4_addr[ATH11K_IPV4_MAX_COUNT][4]; 301 u32 ipv4_count; 302 u32 ipv6_count; 303 u8 ipv6_addr[ATH11K_IPV6_MAX_COUNT][16]; 304 u8 self_ipv6_addr[ATH11K_IPV6_MAX_COUNT][16]; 305 u8 ipv6_type[ATH11K_IPV6_MAX_COUNT]; 306 bool ipv6_valid[ATH11K_IPV6_MAX_COUNT]; 307 u8 mac_addr[ETH_ALEN]; 308 }; 309 310 struct ath11k_rekey_data { 311 u8 kck[NL80211_KCK_LEN]; 312 u8 kek[NL80211_KCK_LEN]; 313 u64 replay_ctr; 314 bool enable_offload; 315 }; 316 317 struct ath11k_vif { 318 u32 vdev_id; 319 enum wmi_vdev_type vdev_type; 320 enum wmi_vdev_subtype vdev_subtype; 321 u32 beacon_interval; 322 u32 dtim_period; 323 u16 ast_hash; 324 u16 ast_idx; 325 u16 tcl_metadata; 326 u8 hal_addr_search_flags; 327 u8 search_type; 328 329 struct ath11k *ar; 330 struct ieee80211_vif *vif; 331 332 u16 tx_seq_no; 333 struct wmi_wmm_params_all_arg wmm_params; 334 struct list_head list; 335 union { 336 struct { 337 u32 uapsd; 338 } sta; 339 struct { 340 /* 127 stations; wmi limit */ 341 u8 tim_bitmap[16]; 342 u8 tim_len; 343 u32 ssid_len; 344 u8 ssid[IEEE80211_MAX_SSID_LEN]; 345 bool hidden_ssid; 346 /* P2P_IE with NoA attribute for P2P_GO case */ 347 u32 noa_len; 348 u8 *noa_data; 349 } ap; 350 } u; 351 352 bool is_started; 353 bool is_up; 354 bool ftm_responder; 355 bool spectral_enabled; 356 bool ps; 357 u32 aid; 358 u8 bssid[ETH_ALEN]; 359 struct cfg80211_bitrate_mask bitrate_mask; 360 struct delayed_work connection_loss_work; 361 int num_legacy_stations; 362 int rtscts_prot_mode; 363 int txpower; 364 bool rsnie_present; 365 bool wpaie_present; 366 bool bcca_zero_sent; 367 bool do_not_send_tmpl; 368 struct ieee80211_chanctx_conf chanctx; 369 struct ath11k_arp_ns_offload arp_ns_offload; 370 struct ath11k_rekey_data rekey_data; 371 372 #ifdef CONFIG_ATH11K_DEBUGFS 373 struct dentry *debugfs_twt; 374 #endif /* CONFIG_ATH11K_DEBUGFS */ 375 }; 376 377 struct ath11k_vif_iter { 378 u32 vdev_id; 379 struct ath11k_vif *arvif; 380 }; 381 382 struct ath11k_rx_peer_stats { 383 u64 num_msdu; 384 u64 num_mpdu_fcs_ok; 385 u64 num_mpdu_fcs_err; 386 u64 tcp_msdu_count; 387 u64 udp_msdu_count; 388 u64 other_msdu_count; 389 u64 ampdu_msdu_count; 390 u64 non_ampdu_msdu_count; 391 u64 stbc_count; 392 u64 beamformed_count; 393 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 394 u64 nss_count[HAL_RX_MAX_NSS]; 395 u64 bw_count[HAL_RX_BW_MAX]; 396 u64 gi_count[HAL_RX_GI_MAX]; 397 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 398 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 399 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 400 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 401 u64 rx_duration; 402 u64 dcm_count; 403 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 404 }; 405 406 #define ATH11K_HE_MCS_NUM 12 407 #define ATH11K_VHT_MCS_NUM 10 408 #define ATH11K_BW_NUM 4 409 #define ATH11K_NSS_NUM 4 410 #define ATH11K_LEGACY_NUM 12 411 #define ATH11K_GI_NUM 4 412 #define ATH11K_HT_MCS_NUM 32 413 414 enum ath11k_pkt_rx_err { 415 ATH11K_PKT_RX_ERR_FCS, 416 ATH11K_PKT_RX_ERR_TKIP, 417 ATH11K_PKT_RX_ERR_CRYPT, 418 ATH11K_PKT_RX_ERR_PEER_IDX_INVAL, 419 ATH11K_PKT_RX_ERR_MAX, 420 }; 421 422 enum ath11k_ampdu_subfrm_num { 423 ATH11K_AMPDU_SUBFRM_NUM_10, 424 ATH11K_AMPDU_SUBFRM_NUM_20, 425 ATH11K_AMPDU_SUBFRM_NUM_30, 426 ATH11K_AMPDU_SUBFRM_NUM_40, 427 ATH11K_AMPDU_SUBFRM_NUM_50, 428 ATH11K_AMPDU_SUBFRM_NUM_60, 429 ATH11K_AMPDU_SUBFRM_NUM_MORE, 430 ATH11K_AMPDU_SUBFRM_NUM_MAX, 431 }; 432 433 enum ath11k_amsdu_subfrm_num { 434 ATH11K_AMSDU_SUBFRM_NUM_1, 435 ATH11K_AMSDU_SUBFRM_NUM_2, 436 ATH11K_AMSDU_SUBFRM_NUM_3, 437 ATH11K_AMSDU_SUBFRM_NUM_4, 438 ATH11K_AMSDU_SUBFRM_NUM_MORE, 439 ATH11K_AMSDU_SUBFRM_NUM_MAX, 440 }; 441 442 enum ath11k_counter_type { 443 ATH11K_COUNTER_TYPE_BYTES, 444 ATH11K_COUNTER_TYPE_PKTS, 445 ATH11K_COUNTER_TYPE_MAX, 446 }; 447 448 enum ath11k_stats_type { 449 ATH11K_STATS_TYPE_SUCC, 450 ATH11K_STATS_TYPE_FAIL, 451 ATH11K_STATS_TYPE_RETRY, 452 ATH11K_STATS_TYPE_AMPDU, 453 ATH11K_STATS_TYPE_MAX, 454 }; 455 456 struct ath11k_htt_data_stats { 457 u64 legacy[ATH11K_COUNTER_TYPE_MAX][ATH11K_LEGACY_NUM]; 458 u64 ht[ATH11K_COUNTER_TYPE_MAX][ATH11K_HT_MCS_NUM]; 459 u64 vht[ATH11K_COUNTER_TYPE_MAX][ATH11K_VHT_MCS_NUM]; 460 u64 he[ATH11K_COUNTER_TYPE_MAX][ATH11K_HE_MCS_NUM]; 461 u64 bw[ATH11K_COUNTER_TYPE_MAX][ATH11K_BW_NUM]; 462 u64 nss[ATH11K_COUNTER_TYPE_MAX][ATH11K_NSS_NUM]; 463 u64 gi[ATH11K_COUNTER_TYPE_MAX][ATH11K_GI_NUM]; 464 }; 465 466 struct ath11k_htt_tx_stats { 467 struct ath11k_htt_data_stats stats[ATH11K_STATS_TYPE_MAX]; 468 u64 tx_duration; 469 u64 ba_fails; 470 u64 ack_fails; 471 }; 472 473 struct ath11k_per_ppdu_tx_stats { 474 u16 succ_pkts; 475 u16 failed_pkts; 476 u16 retry_pkts; 477 u32 succ_bytes; 478 u32 failed_bytes; 479 u32 retry_bytes; 480 }; 481 482 DECLARE_EWMA(avg_rssi, 10, 8) 483 484 struct ath11k_sta { 485 struct ath11k_vif *arvif; 486 487 /* the following are protected by ar->data_lock */ 488 u32 changed; /* IEEE80211_RC_* */ 489 u32 bw; 490 u32 nss; 491 u32 smps; 492 enum hal_pn_type pn_type; 493 494 struct work_struct update_wk; 495 struct work_struct set_4addr_wk; 496 struct rate_info txrate; 497 u32 peer_nss; 498 struct rate_info last_txrate; 499 u64 rx_duration; 500 u64 tx_duration; 501 u8 rssi_comb; 502 struct ewma_avg_rssi avg_rssi; 503 s8 rssi_beacon; 504 s8 chain_signal[IEEE80211_MAX_CHAINS]; 505 struct ath11k_htt_tx_stats *tx_stats; 506 struct ath11k_rx_peer_stats *rx_stats; 507 508 #ifdef CONFIG_MAC80211_DEBUGFS 509 /* protected by conf_mutex */ 510 bool aggr_mode; 511 #endif 512 513 bool use_4addr_set; 514 u16 tcl_metadata; 515 516 /* Protected with ar->data_lock */ 517 enum ath11k_wmi_peer_ps_state peer_ps_state; 518 u64 ps_start_time; 519 u64 ps_start_jiffies; 520 u64 ps_total_duration; 521 bool peer_current_ps_valid; 522 523 u32 bw_prev; 524 }; 525 526 #define ATH11K_MIN_5G_FREQ 4150 527 #define ATH11K_MIN_6G_FREQ 5925 528 #define ATH11K_MAX_6G_FREQ 7115 529 #define ATH11K_NUM_CHANS 102 530 #define ATH11K_MAX_5G_CHAN 177 531 532 enum ath11k_state { 533 ATH11K_STATE_OFF, 534 ATH11K_STATE_ON, 535 ATH11K_STATE_RESTARTING, 536 ATH11K_STATE_RESTARTED, 537 ATH11K_STATE_WEDGED, 538 ATH11K_STATE_FTM, 539 /* Add other states as required */ 540 }; 541 542 /* Antenna noise floor */ 543 #define ATH11K_DEFAULT_NOISE_FLOOR -95 544 545 #define ATH11K_INVALID_RSSI_FULL -1 546 547 #define ATH11K_INVALID_RSSI_EMPTY -128 548 549 struct ath11k_fw_stats { 550 struct dentry *debugfs_fwstats; 551 u32 pdev_id; 552 u32 stats_id; 553 struct list_head pdevs; 554 struct list_head vdevs; 555 struct list_head bcn; 556 }; 557 558 struct ath11k_dbg_htt_stats { 559 u8 type; 560 u8 reset; 561 struct debug_htt_stats_req *stats_req; 562 /* protects shared stats req buffer */ 563 spinlock_t lock; 564 }; 565 566 #define MAX_MODULE_ID_BITMAP_WORDS 16 567 568 struct ath11k_debug { 569 struct dentry *debugfs_pdev; 570 struct ath11k_dbg_htt_stats htt_stats; 571 u32 extd_tx_stats; 572 u32 extd_rx_stats; 573 u32 pktlog_filter; 574 u32 pktlog_mode; 575 u32 pktlog_peer_valid; 576 u8 pktlog_peer_addr[ETH_ALEN]; 577 u32 rx_filter; 578 u32 mem_offset; 579 u32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS]; 580 struct ath11k_debug_dbr *dbr_debug[WMI_DIRECT_BUF_MAX]; 581 }; 582 583 struct ath11k_per_peer_tx_stats { 584 u32 succ_bytes; 585 u32 retry_bytes; 586 u32 failed_bytes; 587 u16 succ_pkts; 588 u16 retry_pkts; 589 u16 failed_pkts; 590 u32 duration; 591 u8 ba_fails; 592 bool is_ampdu; 593 }; 594 595 #define ATH11K_FLUSH_TIMEOUT (5 * HZ) 596 #define ATH11K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 597 598 struct ath11k { 599 struct ath11k_base *ab; 600 struct ath11k_pdev *pdev; 601 struct ieee80211_hw *hw; 602 struct ieee80211_ops *ops; 603 struct ath11k_pdev_wmi *wmi; 604 struct ath11k_pdev_dp dp; 605 u8 mac_addr[ETH_ALEN]; 606 struct ath11k_he ar_he; 607 enum ath11k_state state; 608 bool supports_6ghz; 609 struct { 610 struct completion started; 611 struct completion completed; 612 struct completion on_channel; 613 struct delayed_work timeout; 614 enum ath11k_scan_state state; 615 bool is_roc; 616 int vdev_id; 617 int roc_freq; 618 bool roc_notify; 619 } scan; 620 621 struct { 622 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 623 struct ieee80211_sband_iftype_data 624 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 625 } mac; 626 627 unsigned long dev_flags; 628 unsigned int filter_flags; 629 unsigned long monitor_flags; 630 u32 min_tx_power; 631 u32 max_tx_power; 632 u32 txpower_limit_2g; 633 u32 txpower_limit_5g; 634 u32 txpower_scale; 635 u32 power_scale; 636 u32 chan_tx_pwr; 637 u32 num_stations; 638 u32 max_num_stations; 639 /* To synchronize concurrent synchronous mac80211 callback operations, 640 * concurrent debugfs configuration and concurrent FW statistics events. 641 */ 642 struct mutex conf_mutex; 643 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 644 * vdev_stop_status info, scan data, ath11k_sta info, ath11k_vif info, 645 * channel context data, survey info, test mode data. 646 */ 647 spinlock_t data_lock; 648 649 struct list_head arvifs; 650 /* should never be NULL; needed for regular htt rx */ 651 struct ieee80211_channel *rx_channel; 652 653 /* valid during scan; needed for mgmt rx during scan */ 654 struct ieee80211_channel *scan_channel; 655 656 u8 cfg_tx_chainmask; 657 u8 cfg_rx_chainmask; 658 u8 num_rx_chains; 659 u8 num_tx_chains; 660 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 661 u8 pdev_idx; 662 u8 lmac_id; 663 664 struct completion peer_assoc_done; 665 struct completion peer_delete_done; 666 667 int install_key_status; 668 struct completion install_key_done; 669 670 int last_wmi_vdev_start_status; 671 struct completion vdev_setup_done; 672 struct completion vdev_delete_done; 673 674 int num_peers; 675 int max_num_peers; 676 u32 num_started_vdevs; 677 u32 num_created_vdevs; 678 unsigned long long allocated_vdev_map; 679 680 struct idr txmgmt_idr; 681 /* protects txmgmt_idr data */ 682 spinlock_t txmgmt_idr_lock; 683 atomic_t num_pending_mgmt_tx; 684 wait_queue_head_t txmgmt_empty_waitq; 685 686 /* cycle count is reported twice for each visited channel during scan. 687 * access protected by data_lock 688 */ 689 u32 survey_last_rx_clear_count; 690 u32 survey_last_cycle_count; 691 692 /* Channel info events are expected to come in pairs without and with 693 * COMPLETE flag set respectively for each channel visit during scan. 694 * 695 * However there are deviations from this rule. This flag is used to 696 * avoid reporting garbage data. 697 */ 698 bool ch_info_can_report_survey; 699 struct survey_info survey[ATH11K_NUM_CHANS]; 700 struct completion bss_survey_done; 701 702 struct work_struct regd_update_work; 703 704 struct work_struct wmi_mgmt_tx_work; 705 struct sk_buff_head wmi_mgmt_tx_queue; 706 707 struct ath11k_wow wow; 708 struct completion target_suspend; 709 bool target_suspend_ack; 710 struct ath11k_per_peer_tx_stats peer_tx_stats; 711 struct list_head ppdu_stats_info; 712 u32 ppdu_stat_list_depth; 713 714 struct ath11k_per_peer_tx_stats cached_stats; 715 u32 last_ppdu_id; 716 u32 cached_ppdu_id; 717 int monitor_vdev_id; 718 struct completion fw_mode_reset; 719 u8 ftm_msgref; 720 #ifdef CONFIG_ATH11K_DEBUGFS 721 struct ath11k_debug debug; 722 #endif 723 #ifdef CONFIG_ATH11K_SPECTRAL 724 struct ath11k_spectral spectral; 725 #endif 726 bool dfs_block_radar_events; 727 struct ath11k_thermal thermal; 728 u32 vdev_id_11d_scan; 729 struct completion completed_11d_scan; 730 enum ath11k_11d_state state_11d; 731 bool regdom_set_by_user; 732 int hw_rate_code; 733 u8 twt_enabled; 734 bool nlo_enabled; 735 u8 alpha2[REG_ALPHA2_LEN + 1]; 736 struct ath11k_fw_stats fw_stats; 737 struct completion fw_stats_complete; 738 bool fw_stats_done; 739 740 /* protected by conf_mutex */ 741 bool ps_state_enable; 742 bool ps_timekeeper_enable; 743 }; 744 745 struct ath11k_band_cap { 746 u32 phy_id; 747 u32 max_bw_supported; 748 u32 ht_cap_info; 749 u32 he_cap_info[2]; 750 u32 he_mcs; 751 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 752 struct ath11k_ppe_threshold he_ppet; 753 u16 he_6ghz_capa; 754 }; 755 756 struct ath11k_pdev_cap { 757 u32 supported_bands; 758 u32 ampdu_density; 759 u32 vht_cap; 760 u32 vht_mcs; 761 u32 he_mcs; 762 u32 tx_chain_mask; 763 u32 rx_chain_mask; 764 u32 tx_chain_mask_shift; 765 u32 rx_chain_mask_shift; 766 struct ath11k_band_cap band[NUM_NL80211_BANDS]; 767 bool nss_ratio_enabled; 768 u8 nss_ratio_info; 769 }; 770 771 struct ath11k_pdev { 772 struct ath11k *ar; 773 u32 pdev_id; 774 struct ath11k_pdev_cap cap; 775 u8 mac_addr[ETH_ALEN]; 776 }; 777 778 struct ath11k_board_data { 779 const struct firmware *fw; 780 const void *data; 781 size_t len; 782 }; 783 784 struct ath11k_pci_ops { 785 int (*wakeup)(struct ath11k_base *ab); 786 void (*release)(struct ath11k_base *ab); 787 int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector); 788 void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value); 789 u32 (*window_read32)(struct ath11k_base *ab, u32 offset); 790 }; 791 792 /* IPQ8074 HW channel counters frequency value in hertz */ 793 #define IPQ8074_CC_FREQ_HERTZ 320000 794 795 struct ath11k_bp_stats { 796 /* Head Pointer reported by the last HTT Backpressure event for the ring */ 797 u16 hp; 798 799 /* Tail Pointer reported by the last HTT Backpressure event for the ring */ 800 u16 tp; 801 802 /* Number of Backpressure events received for the ring */ 803 u32 count; 804 805 /* Last recorded event timestamp */ 806 unsigned long jiffies; 807 }; 808 809 struct ath11k_dp_ring_bp_stats { 810 struct ath11k_bp_stats umac_ring_bp_stats[HTT_SW_UMAC_RING_IDX_MAX]; 811 struct ath11k_bp_stats lmac_ring_bp_stats[HTT_SW_LMAC_RING_IDX_MAX][MAX_RADIOS]; 812 }; 813 814 struct ath11k_soc_dp_tx_err_stats { 815 /* TCL Ring Descriptor unavailable */ 816 u32 desc_na[DP_TCL_NUM_RING_MAX]; 817 /* Other failures during dp_tx due to mem allocation failure 818 * idr unavailable etc. 819 */ 820 atomic_t misc_fail; 821 }; 822 823 struct ath11k_soc_dp_stats { 824 u32 err_ring_pkts; 825 u32 invalid_rbm; 826 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 827 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 828 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 829 struct ath11k_soc_dp_tx_err_stats tx_err; 830 struct ath11k_dp_ring_bp_stats bp_stats; 831 }; 832 833 struct ath11k_msi_user { 834 char *name; 835 int num_vectors; 836 u32 base_vector; 837 }; 838 839 struct ath11k_msi_config { 840 int total_vectors; 841 int total_users; 842 struct ath11k_msi_user *users; 843 u16 hw_rev; 844 }; 845 846 /* Master structure to hold the hw data which may be used in core module */ 847 struct ath11k_base { 848 enum ath11k_hw_rev hw_rev; 849 enum ath11k_firmware_mode fw_mode; 850 struct platform_device *pdev; 851 struct device *dev; 852 struct ath11k_qmi qmi; 853 struct ath11k_wmi_base wmi_ab; 854 struct completion fw_ready; 855 int num_radios; 856 /* HW channel counters frequency value in hertz common to all MACs */ 857 u32 cc_freq_hz; 858 859 struct ath11k_htc htc; 860 861 struct ath11k_dp dp; 862 863 void __iomem *mem; 864 void __iomem *mem_ce; 865 unsigned long mem_len; 866 867 struct { 868 enum ath11k_bus bus; 869 const struct ath11k_hif_ops *ops; 870 } hif; 871 872 struct { 873 struct completion wakeup_completed; 874 } wow; 875 876 struct ath11k_ce ce; 877 struct timer_list rx_replenish_retry; 878 struct ath11k_hal hal; 879 /* To synchronize core_start/core_stop */ 880 struct mutex core_lock; 881 /* Protects data like peers */ 882 spinlock_t base_lock; 883 struct ath11k_pdev pdevs[MAX_RADIOS]; 884 struct { 885 enum WMI_HOST_WLAN_BAND supported_bands; 886 u32 pdev_id; 887 } target_pdev_ids[MAX_RADIOS]; 888 u8 target_pdev_count; 889 struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS]; 890 struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS]; 891 unsigned long long free_vdev_map; 892 893 /* To synchronize rhash tbl write operation */ 894 struct mutex tbl_mtx_lock; 895 896 /* The rhashtable containing struct ath11k_peer keyed by mac addr */ 897 struct rhashtable *rhead_peer_addr; 898 struct rhashtable_params rhash_peer_addr_param; 899 900 /* The rhashtable containing struct ath11k_peer keyed by id */ 901 struct rhashtable *rhead_peer_id; 902 struct rhashtable_params rhash_peer_id_param; 903 904 struct list_head peers; 905 wait_queue_head_t peer_mapping_wq; 906 u8 mac_addr[ETH_ALEN]; 907 int irq_num[ATH11K_IRQ_NUM_MAX]; 908 struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX]; 909 struct ath11k_targ_cap target_caps; 910 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 911 bool pdevs_macaddr_valid; 912 913 struct ath11k_hw_params hw_params; 914 915 const struct firmware *cal_file; 916 917 /* Below regd's are protected by ab->data_lock */ 918 /* This is the regd set for every radio 919 * by the firmware during initialization 920 */ 921 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 922 /* This regd is set during dynamic country setting 923 * This may or may not be used during the runtime 924 */ 925 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 926 927 /* Current DFS Regulatory */ 928 enum ath11k_dfs_region dfs_region; 929 #ifdef CONFIG_ATH11K_DEBUGFS 930 struct dentry *debugfs_soc; 931 #endif 932 struct ath11k_soc_dp_stats soc_stats; 933 934 unsigned long dev_flags; 935 struct completion driver_recovery; 936 struct workqueue_struct *workqueue; 937 struct work_struct restart_work; 938 struct work_struct update_11d_work; 939 u8 new_alpha2[3]; 940 struct workqueue_struct *workqueue_aux; 941 struct work_struct reset_work; 942 atomic_t reset_count; 943 atomic_t recovery_count; 944 atomic_t recovery_start_count; 945 bool is_reset; 946 struct completion reset_complete; 947 struct completion reconfigure_complete; 948 struct completion recovery_start; 949 /* continuous recovery fail count */ 950 atomic_t fail_cont_count; 951 unsigned long reset_fail_timeout; 952 struct { 953 /* protected by data_lock */ 954 u32 fw_crash_counter; 955 } stats; 956 u32 pktlog_defs_checksum; 957 958 struct ath11k_dbring_cap *db_caps; 959 u32 num_db_cap; 960 961 /* To synchronize 11d scan vdev id */ 962 struct mutex vdev_id_11d_lock; 963 struct timer_list mon_reap_timer; 964 965 struct completion htc_suspend; 966 967 struct { 968 enum ath11k_bdf_search bdf_search; 969 u32 vendor; 970 u32 device; 971 u32 subsystem_vendor; 972 u32 subsystem_device; 973 } id; 974 975 struct { 976 struct { 977 const struct ath11k_msi_config *config; 978 u32 ep_base_data; 979 u32 irqs[32]; 980 u32 addr_lo; 981 u32 addr_hi; 982 } msi; 983 984 const struct ath11k_pci_ops *ops; 985 } pci; 986 987 struct { 988 u32 api_version; 989 990 const struct firmware *fw; 991 const u8 *amss_data; 992 size_t amss_len; 993 const u8 *m3_data; 994 size_t m3_len; 995 996 DECLARE_BITMAP(fw_features, ATH11K_FW_FEATURE_COUNT); 997 } fw; 998 999 #ifdef CONFIG_NL80211_TESTMODE 1000 struct { 1001 u32 data_pos; 1002 u32 expected_seq; 1003 u8 *eventdata; 1004 } testmode; 1005 #endif 1006 1007 /* must be last */ 1008 u8 drv_priv[] __aligned(sizeof(void *)); 1009 }; 1010 1011 struct ath11k_fw_stats_pdev { 1012 struct list_head list; 1013 1014 /* PDEV stats */ 1015 s32 ch_noise_floor; 1016 /* Cycles spent transmitting frames */ 1017 u32 tx_frame_count; 1018 /* Cycles spent receiving frames */ 1019 u32 rx_frame_count; 1020 /* Total channel busy time, evidently */ 1021 u32 rx_clear_count; 1022 /* Total on-channel time */ 1023 u32 cycle_count; 1024 u32 phy_err_count; 1025 u32 chan_tx_power; 1026 u32 ack_rx_bad; 1027 u32 rts_bad; 1028 u32 rts_good; 1029 u32 fcs_bad; 1030 u32 no_beacons; 1031 u32 mib_int_count; 1032 1033 /* PDEV TX stats */ 1034 /* Num HTT cookies queued to dispatch list */ 1035 s32 comp_queued; 1036 /* Num HTT cookies dispatched */ 1037 s32 comp_delivered; 1038 /* Num MSDU queued to WAL */ 1039 s32 msdu_enqued; 1040 /* Num MPDU queue to WAL */ 1041 s32 mpdu_enqued; 1042 /* Num MSDUs dropped by WMM limit */ 1043 s32 wmm_drop; 1044 /* Num Local frames queued */ 1045 s32 local_enqued; 1046 /* Num Local frames done */ 1047 s32 local_freed; 1048 /* Num queued to HW */ 1049 s32 hw_queued; 1050 /* Num PPDU reaped from HW */ 1051 s32 hw_reaped; 1052 /* Num underruns */ 1053 s32 underrun; 1054 /* Num hw paused */ 1055 u32 hw_paused; 1056 /* Num PPDUs cleaned up in TX abort */ 1057 s32 tx_abort; 1058 /* Num MPDUs requeued by SW */ 1059 s32 mpdus_requeued; 1060 /* excessive retries */ 1061 u32 tx_ko; 1062 u32 tx_xretry; 1063 /* data hw rate code */ 1064 u32 data_rc; 1065 /* Scheduler self triggers */ 1066 u32 self_triggers; 1067 /* frames dropped due to excessive sw retries */ 1068 u32 sw_retry_failure; 1069 /* illegal rate phy errors */ 1070 u32 illgl_rate_phy_err; 1071 /* wal pdev continuous xretry */ 1072 u32 pdev_cont_xretry; 1073 /* wal pdev tx timeouts */ 1074 u32 pdev_tx_timeout; 1075 /* wal pdev resets */ 1076 u32 pdev_resets; 1077 /* frames dropped due to non-availability of stateless TIDs */ 1078 u32 stateless_tid_alloc_failure; 1079 /* PhY/BB underrun */ 1080 u32 phy_underrun; 1081 /* MPDU is more than txop limit */ 1082 u32 txop_ovf; 1083 /* Num sequences posted */ 1084 u32 seq_posted; 1085 /* Num sequences failed in queueing */ 1086 u32 seq_failed_queueing; 1087 /* Num sequences completed */ 1088 u32 seq_completed; 1089 /* Num sequences restarted */ 1090 u32 seq_restarted; 1091 /* Num of MU sequences posted */ 1092 u32 mu_seq_posted; 1093 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT 1094 * (Reset,channel change) 1095 */ 1096 s32 mpdus_sw_flush; 1097 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 1098 s32 mpdus_hw_filter; 1099 /* Num MPDUs truncated by PDG (TXOP, TBTT, 1100 * PPDU_duration based on rate, dyn_bw) 1101 */ 1102 s32 mpdus_truncated; 1103 /* Num MPDUs that was tried but didn't receive ACK or BA */ 1104 s32 mpdus_ack_failed; 1105 /* Num MPDUs that was dropped du to expiry. */ 1106 s32 mpdus_expired; 1107 1108 /* PDEV RX stats */ 1109 /* Cnts any change in ring routing mid-ppdu */ 1110 s32 mid_ppdu_route_change; 1111 /* Total number of statuses processed */ 1112 s32 status_rcvd; 1113 /* Extra frags on rings 0-3 */ 1114 s32 r0_frags; 1115 s32 r1_frags; 1116 s32 r2_frags; 1117 s32 r3_frags; 1118 /* MSDUs / MPDUs delivered to HTT */ 1119 s32 htt_msdus; 1120 s32 htt_mpdus; 1121 /* MSDUs / MPDUs delivered to local stack */ 1122 s32 loc_msdus; 1123 s32 loc_mpdus; 1124 /* AMSDUs that have more MSDUs than the status ring size */ 1125 s32 oversize_amsdu; 1126 /* Number of PHY errors */ 1127 s32 phy_errs; 1128 /* Number of PHY errors drops */ 1129 s32 phy_err_drop; 1130 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 1131 s32 mpdu_errs; 1132 /* Num overflow errors */ 1133 s32 rx_ovfl_errs; 1134 }; 1135 1136 struct ath11k_fw_stats_vdev { 1137 struct list_head list; 1138 1139 u32 vdev_id; 1140 u32 beacon_snr; 1141 u32 data_snr; 1142 u32 num_tx_frames[WLAN_MAX_AC]; 1143 u32 num_rx_frames; 1144 u32 num_tx_frames_retries[WLAN_MAX_AC]; 1145 u32 num_tx_frames_failures[WLAN_MAX_AC]; 1146 u32 num_rts_fail; 1147 u32 num_rts_success; 1148 u32 num_rx_err; 1149 u32 num_rx_discard; 1150 u32 num_tx_not_acked; 1151 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 1152 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 1153 }; 1154 1155 struct ath11k_fw_stats_bcn { 1156 struct list_head list; 1157 1158 u32 vdev_id; 1159 u32 tx_bcn_succ_cnt; 1160 u32 tx_bcn_outage_cnt; 1161 }; 1162 1163 void ath11k_fw_stats_init(struct ath11k *ar); 1164 void ath11k_fw_stats_pdevs_free(struct list_head *head); 1165 void ath11k_fw_stats_vdevs_free(struct list_head *head); 1166 void ath11k_fw_stats_bcn_free(struct list_head *head); 1167 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats); 1168 1169 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[]; 1170 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[]; 1171 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[]; 1172 1173 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[]; 1174 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[]; 1175 1176 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[]; 1177 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[]; 1178 1179 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[]; 1180 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[]; 1181 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab); 1182 int ath11k_core_pre_init(struct ath11k_base *ab); 1183 int ath11k_core_init(struct ath11k_base *ath11k); 1184 void ath11k_core_deinit(struct ath11k_base *ath11k); 1185 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 1186 enum ath11k_bus bus); 1187 void ath11k_core_free(struct ath11k_base *ath11k); 1188 int ath11k_core_fetch_bdf(struct ath11k_base *ath11k, 1189 struct ath11k_board_data *bd); 1190 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd); 1191 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1192 struct ath11k_board_data *bd, 1193 const char *name); 1194 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd); 1195 int ath11k_core_check_dt(struct ath11k_base *ath11k); 1196 int ath11k_core_check_smbios(struct ath11k_base *ab); 1197 void ath11k_core_halt(struct ath11k *ar); 1198 int ath11k_core_resume(struct ath11k_base *ab); 1199 int ath11k_core_suspend(struct ath11k_base *ab); 1200 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab); 1201 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab); 1202 1203 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1204 const char *filename); 1205 1206 static inline const char *ath11k_scan_state_str(enum ath11k_scan_state state) 1207 { 1208 switch (state) { 1209 case ATH11K_SCAN_IDLE: 1210 return "idle"; 1211 case ATH11K_SCAN_STARTING: 1212 return "starting"; 1213 case ATH11K_SCAN_RUNNING: 1214 return "running"; 1215 case ATH11K_SCAN_ABORTING: 1216 return "aborting"; 1217 } 1218 1219 return "unknown"; 1220 } 1221 1222 static inline struct ath11k_skb_cb *ATH11K_SKB_CB(struct sk_buff *skb) 1223 { 1224 BUILD_BUG_ON(sizeof(struct ath11k_skb_cb) > 1225 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 1226 return (struct ath11k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 1227 } 1228 1229 static inline struct ath11k_skb_rxcb *ATH11K_SKB_RXCB(struct sk_buff *skb) 1230 { 1231 BUILD_BUG_ON(sizeof(struct ath11k_skb_rxcb) > sizeof(skb->cb)); 1232 return (struct ath11k_skb_rxcb *)skb->cb; 1233 } 1234 1235 static inline struct ath11k_vif *ath11k_vif_to_arvif(struct ieee80211_vif *vif) 1236 { 1237 return (struct ath11k_vif *)vif->drv_priv; 1238 } 1239 1240 static inline struct ath11k_sta *ath11k_sta_to_arsta(struct ieee80211_sta *sta) 1241 { 1242 return (struct ath11k_sta *)sta->drv_priv; 1243 } 1244 1245 static inline struct ath11k *ath11k_ab_to_ar(struct ath11k_base *ab, 1246 int mac_id) 1247 { 1248 return ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 1249 } 1250 1251 static inline void ath11k_core_create_firmware_path(struct ath11k_base *ab, 1252 const char *filename, 1253 void *buf, size_t buf_len) 1254 { 1255 snprintf(buf, buf_len, "%s/%s/%s", ATH11K_FW_DIR, 1256 ab->hw_params.fw.dir, filename); 1257 } 1258 1259 static inline const char *ath11k_bus_str(enum ath11k_bus bus) 1260 { 1261 switch (bus) { 1262 case ATH11K_BUS_PCI: 1263 return "pci"; 1264 case ATH11K_BUS_AHB: 1265 return "ahb"; 1266 } 1267 1268 return "unknown"; 1269 } 1270 1271 #endif /* _CORE_H_ */ 1272