1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * smscufx.c -- Framebuffer driver for SMSC UFX USB controller 4 * 5 * Copyright (C) 2011 Steve Glendinning <steve.glendinning@shawell.net> 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 * 10 * Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen, 11 * and others. 12 * 13 * Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev 14 * available from http://git.plugable.com 15 * 16 * Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven, 17 * usb-skeleton by GregKH. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/usb.h> 26 #include <linux/uaccess.h> 27 #include <linux/mm.h> 28 #include <linux/fb.h> 29 #include <linux/vmalloc.h> 30 #include <linux/slab.h> 31 #include <linux/delay.h> 32 #include "edid.h" 33 34 #define check_warn(status, fmt, args...) \ 35 ({ if (status < 0) pr_warn(fmt, ##args); }) 36 37 #define check_warn_return(status, fmt, args...) \ 38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } }) 39 40 #define check_warn_goto_error(status, fmt, args...) \ 41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } }) 42 43 #define all_bits_set(x, bits) (((x) & (bits)) == (bits)) 44 45 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 46 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 47 48 /* 49 * TODO: Propose standard fb.h ioctl for reporting damage, 50 * using _IOWR() and one of the existing area structs from fb.h 51 * Consider these ioctls deprecated, but they're still used by the 52 * DisplayLink X server as yet - need both to be modified in tandem 53 * when new ioctl(s) are ready. 54 */ 55 #define UFX_IOCTL_RETURN_EDID (0xAD) 56 #define UFX_IOCTL_REPORT_DAMAGE (0xAA) 57 58 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */ 59 #define BULK_SIZE (512) 60 #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE) 61 #define WRITES_IN_FLIGHT (4) 62 63 #define GET_URB_TIMEOUT (HZ) 64 #define FREE_URB_TIMEOUT (HZ*2) 65 66 #define BPP 2 67 68 #define UFX_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */ 69 #define UFX_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */ 70 71 struct dloarea { 72 int x, y; 73 int w, h; 74 }; 75 76 struct urb_node { 77 struct list_head entry; 78 struct ufx_data *dev; 79 struct delayed_work release_urb_work; 80 struct urb *urb; 81 }; 82 83 struct urb_list { 84 struct list_head list; 85 spinlock_t lock; 86 struct semaphore limit_sem; 87 int available; 88 int count; 89 size_t size; 90 }; 91 92 struct ufx_data { 93 struct usb_device *udev; 94 struct device *gdev; /* &udev->dev */ 95 struct fb_info *info; 96 struct urb_list urbs; 97 struct kref kref; 98 int fb_count; 99 bool virtualized; /* true when physical usb device not present */ 100 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ 101 atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ 102 u8 *edid; /* null until we read edid from hw or get from sysfs */ 103 size_t edid_size; 104 u32 pseudo_palette[256]; 105 }; 106 107 static struct fb_fix_screeninfo ufx_fix = { 108 .id = "smscufx", 109 .type = FB_TYPE_PACKED_PIXELS, 110 .visual = FB_VISUAL_TRUECOLOR, 111 .xpanstep = 0, 112 .ypanstep = 0, 113 .ywrapstep = 0, 114 .accel = FB_ACCEL_NONE, 115 }; 116 117 static const u32 smscufx_info_flags = FBINFO_READS_FAST | 118 FBINFO_VIRTFB | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT | 119 FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR; 120 121 static const struct usb_device_id id_table[] = { 122 {USB_DEVICE(0x0424, 0x9d00),}, 123 {USB_DEVICE(0x0424, 0x9d01),}, 124 {}, 125 }; 126 MODULE_DEVICE_TABLE(usb, id_table); 127 128 /* module options */ 129 static bool console; /* Optionally allow fbcon to consume first framebuffer */ 130 static bool fb_defio = true; /* Optionally enable fb_defio mmap support */ 131 132 /* ufx keeps a list of urbs for efficient bulk transfers */ 133 static void ufx_urb_completion(struct urb *urb); 134 static struct urb *ufx_get_urb(struct ufx_data *dev); 135 static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len); 136 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size); 137 static void ufx_free_urb_list(struct ufx_data *dev); 138 139 static DEFINE_MUTEX(disconnect_mutex); 140 141 /* reads a control register */ 142 static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data) 143 { 144 u32 *buf = kmalloc(4, GFP_KERNEL); 145 int ret; 146 147 BUG_ON(!dev); 148 149 if (!buf) 150 return -ENOMEM; 151 152 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), 153 USB_VENDOR_REQUEST_READ_REGISTER, 154 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 155 00, index, buf, 4, USB_CTRL_GET_TIMEOUT); 156 157 le32_to_cpus(buf); 158 *data = *buf; 159 kfree(buf); 160 161 if (unlikely(ret < 0)) 162 pr_warn("Failed to read register index 0x%08x\n", index); 163 164 return ret; 165 } 166 167 /* writes a control register */ 168 static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data) 169 { 170 u32 *buf = kmalloc(4, GFP_KERNEL); 171 int ret; 172 173 BUG_ON(!dev); 174 175 if (!buf) 176 return -ENOMEM; 177 178 *buf = data; 179 cpu_to_le32s(buf); 180 181 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), 182 USB_VENDOR_REQUEST_WRITE_REGISTER, 183 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 184 00, index, buf, 4, USB_CTRL_SET_TIMEOUT); 185 186 kfree(buf); 187 188 if (unlikely(ret < 0)) 189 pr_warn("Failed to write register index 0x%08x with value " 190 "0x%08x\n", index, data); 191 192 return ret; 193 } 194 195 static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index, 196 u32 bits_to_clear, u32 bits_to_set) 197 { 198 u32 data; 199 int status = ufx_reg_read(dev, index, &data); 200 check_warn_return(status, "ufx_reg_clear_and_set_bits error reading " 201 "0x%x", index); 202 203 data &= (~bits_to_clear); 204 data |= bits_to_set; 205 206 status = ufx_reg_write(dev, index, data); 207 check_warn_return(status, "ufx_reg_clear_and_set_bits error writing " 208 "0x%x", index); 209 210 return 0; 211 } 212 213 static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits) 214 { 215 return ufx_reg_clear_and_set_bits(dev, index, 0, bits); 216 } 217 218 static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits) 219 { 220 return ufx_reg_clear_and_set_bits(dev, index, bits, 0); 221 } 222 223 static int ufx_lite_reset(struct ufx_data *dev) 224 { 225 int status; 226 u32 value; 227 228 status = ufx_reg_write(dev, 0x3008, 0x00000001); 229 check_warn_return(status, "ufx_lite_reset error writing 0x3008"); 230 231 status = ufx_reg_read(dev, 0x3008, &value); 232 check_warn_return(status, "ufx_lite_reset error reading 0x3008"); 233 234 return (value == 0) ? 0 : -EIO; 235 } 236 237 /* If display is unblanked, then blank it */ 238 static int ufx_blank(struct ufx_data *dev, bool wait) 239 { 240 u32 dc_ctrl, dc_sts; 241 int i; 242 243 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 244 check_warn_return(status, "ufx_blank error reading 0x2004"); 245 246 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 247 check_warn_return(status, "ufx_blank error reading 0x2000"); 248 249 /* return success if display is already blanked */ 250 if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100)) 251 return 0; 252 253 /* request the DC to blank the display */ 254 dc_ctrl |= 0x00000100; 255 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 256 check_warn_return(status, "ufx_blank error writing 0x2000"); 257 258 /* return success immediately if we don't have to wait */ 259 if (!wait) 260 return 0; 261 262 for (i = 0; i < 250; i++) { 263 status = ufx_reg_read(dev, 0x2004, &dc_sts); 264 check_warn_return(status, "ufx_blank error reading 0x2004"); 265 266 if (dc_sts & 0x00000100) 267 return 0; 268 } 269 270 /* timed out waiting for display to blank */ 271 return -EIO; 272 } 273 274 /* If display is blanked, then unblank it */ 275 static int ufx_unblank(struct ufx_data *dev, bool wait) 276 { 277 u32 dc_ctrl, dc_sts; 278 int i; 279 280 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 281 check_warn_return(status, "ufx_unblank error reading 0x2004"); 282 283 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 284 check_warn_return(status, "ufx_unblank error reading 0x2000"); 285 286 /* return success if display is already unblanked */ 287 if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0)) 288 return 0; 289 290 /* request the DC to unblank the display */ 291 dc_ctrl &= ~0x00000100; 292 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 293 check_warn_return(status, "ufx_unblank error writing 0x2000"); 294 295 /* return success immediately if we don't have to wait */ 296 if (!wait) 297 return 0; 298 299 for (i = 0; i < 250; i++) { 300 status = ufx_reg_read(dev, 0x2004, &dc_sts); 301 check_warn_return(status, "ufx_unblank error reading 0x2004"); 302 303 if ((dc_sts & 0x00000100) == 0) 304 return 0; 305 } 306 307 /* timed out waiting for display to unblank */ 308 return -EIO; 309 } 310 311 /* If display is enabled, then disable it */ 312 static int ufx_disable(struct ufx_data *dev, bool wait) 313 { 314 u32 dc_ctrl, dc_sts; 315 int i; 316 317 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 318 check_warn_return(status, "ufx_disable error reading 0x2004"); 319 320 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 321 check_warn_return(status, "ufx_disable error reading 0x2000"); 322 323 /* return success if display is already disabled */ 324 if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0)) 325 return 0; 326 327 /* request the DC to disable the display */ 328 dc_ctrl &= ~(0x00000001); 329 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 330 check_warn_return(status, "ufx_disable error writing 0x2000"); 331 332 /* return success immediately if we don't have to wait */ 333 if (!wait) 334 return 0; 335 336 for (i = 0; i < 250; i++) { 337 status = ufx_reg_read(dev, 0x2004, &dc_sts); 338 check_warn_return(status, "ufx_disable error reading 0x2004"); 339 340 if ((dc_sts & 0x00000001) == 0) 341 return 0; 342 } 343 344 /* timed out waiting for display to disable */ 345 return -EIO; 346 } 347 348 /* If display is disabled, then enable it */ 349 static int ufx_enable(struct ufx_data *dev, bool wait) 350 { 351 u32 dc_ctrl, dc_sts; 352 int i; 353 354 int status = ufx_reg_read(dev, 0x2004, &dc_sts); 355 check_warn_return(status, "ufx_enable error reading 0x2004"); 356 357 status = ufx_reg_read(dev, 0x2000, &dc_ctrl); 358 check_warn_return(status, "ufx_enable error reading 0x2000"); 359 360 /* return success if display is already enabled */ 361 if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001)) 362 return 0; 363 364 /* request the DC to enable the display */ 365 dc_ctrl |= 0x00000001; 366 status = ufx_reg_write(dev, 0x2000, dc_ctrl); 367 check_warn_return(status, "ufx_enable error writing 0x2000"); 368 369 /* return success immediately if we don't have to wait */ 370 if (!wait) 371 return 0; 372 373 for (i = 0; i < 250; i++) { 374 status = ufx_reg_read(dev, 0x2004, &dc_sts); 375 check_warn_return(status, "ufx_enable error reading 0x2004"); 376 377 if (dc_sts & 0x00000001) 378 return 0; 379 } 380 381 /* timed out waiting for display to enable */ 382 return -EIO; 383 } 384 385 static int ufx_config_sys_clk(struct ufx_data *dev) 386 { 387 int status = ufx_reg_write(dev, 0x700C, 0x8000000F); 388 check_warn_return(status, "error writing 0x700C"); 389 390 status = ufx_reg_write(dev, 0x7014, 0x0010024F); 391 check_warn_return(status, "error writing 0x7014"); 392 393 status = ufx_reg_write(dev, 0x7010, 0x00000000); 394 check_warn_return(status, "error writing 0x7010"); 395 396 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A); 397 check_warn_return(status, "error clearing PLL1 bypass in 0x700C"); 398 msleep(1); 399 400 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000); 401 check_warn_return(status, "error clearing output gate in 0x700C"); 402 403 return 0; 404 } 405 406 static int ufx_config_ddr2(struct ufx_data *dev) 407 { 408 int status, i = 0; 409 u32 tmp; 410 411 status = ufx_reg_write(dev, 0x0004, 0x001F0F77); 412 check_warn_return(status, "error writing 0x0004"); 413 414 status = ufx_reg_write(dev, 0x0008, 0xFFF00000); 415 check_warn_return(status, "error writing 0x0008"); 416 417 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222); 418 check_warn_return(status, "error writing 0x000C"); 419 420 status = ufx_reg_write(dev, 0x0010, 0x00030814); 421 check_warn_return(status, "error writing 0x0010"); 422 423 status = ufx_reg_write(dev, 0x0014, 0x00500019); 424 check_warn_return(status, "error writing 0x0014"); 425 426 status = ufx_reg_write(dev, 0x0018, 0x020D0F15); 427 check_warn_return(status, "error writing 0x0018"); 428 429 status = ufx_reg_write(dev, 0x001C, 0x02532305); 430 check_warn_return(status, "error writing 0x001C"); 431 432 status = ufx_reg_write(dev, 0x0020, 0x0B030905); 433 check_warn_return(status, "error writing 0x0020"); 434 435 status = ufx_reg_write(dev, 0x0024, 0x00000827); 436 check_warn_return(status, "error writing 0x0024"); 437 438 status = ufx_reg_write(dev, 0x0028, 0x00000000); 439 check_warn_return(status, "error writing 0x0028"); 440 441 status = ufx_reg_write(dev, 0x002C, 0x00000042); 442 check_warn_return(status, "error writing 0x002C"); 443 444 status = ufx_reg_write(dev, 0x0030, 0x09520000); 445 check_warn_return(status, "error writing 0x0030"); 446 447 status = ufx_reg_write(dev, 0x0034, 0x02223314); 448 check_warn_return(status, "error writing 0x0034"); 449 450 status = ufx_reg_write(dev, 0x0038, 0x00430043); 451 check_warn_return(status, "error writing 0x0038"); 452 453 status = ufx_reg_write(dev, 0x003C, 0xF00F000F); 454 check_warn_return(status, "error writing 0x003C"); 455 456 status = ufx_reg_write(dev, 0x0040, 0xF380F00F); 457 check_warn_return(status, "error writing 0x0040"); 458 459 status = ufx_reg_write(dev, 0x0044, 0xF00F0496); 460 check_warn_return(status, "error writing 0x0044"); 461 462 status = ufx_reg_write(dev, 0x0048, 0x03080406); 463 check_warn_return(status, "error writing 0x0048"); 464 465 status = ufx_reg_write(dev, 0x004C, 0x00001000); 466 check_warn_return(status, "error writing 0x004C"); 467 468 status = ufx_reg_write(dev, 0x005C, 0x00000007); 469 check_warn_return(status, "error writing 0x005C"); 470 471 status = ufx_reg_write(dev, 0x0100, 0x54F00012); 472 check_warn_return(status, "error writing 0x0100"); 473 474 status = ufx_reg_write(dev, 0x0104, 0x00004012); 475 check_warn_return(status, "error writing 0x0104"); 476 477 status = ufx_reg_write(dev, 0x0118, 0x40404040); 478 check_warn_return(status, "error writing 0x0118"); 479 480 status = ufx_reg_write(dev, 0x0000, 0x00000001); 481 check_warn_return(status, "error writing 0x0000"); 482 483 while (i++ < 500) { 484 status = ufx_reg_read(dev, 0x0000, &tmp); 485 check_warn_return(status, "error reading 0x0000"); 486 487 if (all_bits_set(tmp, 0xC0000000)) 488 return 0; 489 } 490 491 pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp); 492 return -ETIMEDOUT; 493 } 494 495 struct pll_values { 496 u32 div_r0; 497 u32 div_f0; 498 u32 div_q0; 499 u32 range0; 500 u32 div_r1; 501 u32 div_f1; 502 u32 div_q1; 503 u32 range1; 504 }; 505 506 static u32 ufx_calc_range(u32 ref_freq) 507 { 508 if (ref_freq >= 88000000) 509 return 7; 510 511 if (ref_freq >= 54000000) 512 return 6; 513 514 if (ref_freq >= 34000000) 515 return 5; 516 517 if (ref_freq >= 21000000) 518 return 4; 519 520 if (ref_freq >= 13000000) 521 return 3; 522 523 if (ref_freq >= 8000000) 524 return 2; 525 526 return 1; 527 } 528 529 /* calculates PLL divider settings for a desired target frequency */ 530 static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll) 531 { 532 const u32 ref_clk = 25000000; 533 u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1; 534 u32 min_error = clk_pixel_pll; 535 536 for (div_r0 = 1; div_r0 <= 32; div_r0++) { 537 u32 ref_freq0 = ref_clk / div_r0; 538 if (ref_freq0 < 5000000) 539 break; 540 541 if (ref_freq0 > 200000000) 542 continue; 543 544 for (div_f0 = 1; div_f0 <= 256; div_f0++) { 545 u32 vco_freq0 = ref_freq0 * div_f0; 546 547 if (vco_freq0 < 350000000) 548 continue; 549 550 if (vco_freq0 > 700000000) 551 break; 552 553 for (div_q0 = 0; div_q0 < 7; div_q0++) { 554 u32 pllout_freq0 = vco_freq0 / (1 << div_q0); 555 556 if (pllout_freq0 < 5000000) 557 break; 558 559 if (pllout_freq0 > 200000000) 560 continue; 561 562 for (div_r1 = 1; div_r1 <= 32; div_r1++) { 563 u32 ref_freq1 = pllout_freq0 / div_r1; 564 565 if (ref_freq1 < 5000000) 566 break; 567 568 for (div_f1 = 1; div_f1 <= 256; div_f1++) { 569 u32 vco_freq1 = ref_freq1 * div_f1; 570 571 if (vco_freq1 < 350000000) 572 continue; 573 574 if (vco_freq1 > 700000000) 575 break; 576 577 for (div_q1 = 0; div_q1 < 7; div_q1++) { 578 u32 pllout_freq1 = vco_freq1 / (1 << div_q1); 579 int error = abs(pllout_freq1 - clk_pixel_pll); 580 581 if (pllout_freq1 < 5000000) 582 break; 583 584 if (pllout_freq1 > 700000000) 585 continue; 586 587 if (error < min_error) { 588 min_error = error; 589 590 /* final returned value is equal to calculated value - 1 591 * because a value of 0 = divide by 1 */ 592 asic_pll->div_r0 = div_r0 - 1; 593 asic_pll->div_f0 = div_f0 - 1; 594 asic_pll->div_q0 = div_q0; 595 asic_pll->div_r1 = div_r1 - 1; 596 asic_pll->div_f1 = div_f1 - 1; 597 asic_pll->div_q1 = div_q1; 598 599 asic_pll->range0 = ufx_calc_range(ref_freq0); 600 asic_pll->range1 = ufx_calc_range(ref_freq1); 601 602 if (min_error == 0) 603 return; 604 } 605 } 606 } 607 } 608 } 609 } 610 } 611 } 612 613 /* sets analog bit PLL configuration values */ 614 static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock) 615 { 616 struct pll_values asic_pll = {0}; 617 u32 value, clk_pixel, clk_pixel_pll; 618 int status; 619 620 /* convert pixclock (in ps) to frequency (in Hz) */ 621 clk_pixel = PICOS2KHZ(pixclock) * 1000; 622 pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel); 623 624 /* clk_pixel = 1/2 clk_pixel_pll */ 625 clk_pixel_pll = clk_pixel * 2; 626 627 ufx_calc_pll_values(clk_pixel_pll, &asic_pll); 628 629 /* Keep BYPASS and RESET signals asserted until configured */ 630 status = ufx_reg_write(dev, 0x7000, 0x8000000F); 631 check_warn_return(status, "error writing 0x7000"); 632 633 value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) | 634 (asic_pll.div_q1 << 16) | (asic_pll.range1 << 20)); 635 status = ufx_reg_write(dev, 0x7008, value); 636 check_warn_return(status, "error writing 0x7008"); 637 638 value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) | 639 (asic_pll.div_q0 << 16) | (asic_pll.range0 << 20)); 640 status = ufx_reg_write(dev, 0x7004, value); 641 check_warn_return(status, "error writing 0x7004"); 642 643 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005); 644 check_warn_return(status, 645 "error clearing PLL0 bypass bits in 0x7000"); 646 msleep(1); 647 648 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A); 649 check_warn_return(status, 650 "error clearing PLL1 bypass bits in 0x7000"); 651 msleep(1); 652 653 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000); 654 check_warn_return(status, "error clearing gate bits in 0x7000"); 655 656 return 0; 657 } 658 659 static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var) 660 { 661 u32 temp; 662 u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end; 663 u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end; 664 665 int status = ufx_reg_write(dev, 0x8028, 0); 666 check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad"); 667 668 status = ufx_reg_write(dev, 0x8024, 0); 669 check_warn_return(status, "ufx_set_vid_mode error disabling VDAC"); 670 671 /* shut everything down before changing timing */ 672 status = ufx_blank(dev, true); 673 check_warn_return(status, "ufx_set_vid_mode error blanking display"); 674 675 status = ufx_disable(dev, true); 676 check_warn_return(status, "ufx_set_vid_mode error disabling display"); 677 678 status = ufx_config_pix_clk(dev, var->pixclock); 679 check_warn_return(status, "ufx_set_vid_mode error configuring pixclock"); 680 681 status = ufx_reg_write(dev, 0x2000, 0x00000104); 682 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000"); 683 684 /* set horizontal timings */ 685 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin; 686 h_active = var->xres; 687 h_blank_start = var->xres + var->right_margin; 688 h_blank_end = var->xres + var->right_margin + var->hsync_len; 689 h_sync_start = var->xres + var->right_margin; 690 h_sync_end = var->xres + var->right_margin + var->hsync_len; 691 692 temp = ((h_total - 1) << 16) | (h_active - 1); 693 status = ufx_reg_write(dev, 0x2008, temp); 694 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008"); 695 696 temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1); 697 status = ufx_reg_write(dev, 0x200C, temp); 698 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C"); 699 700 temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1); 701 status = ufx_reg_write(dev, 0x2010, temp); 702 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010"); 703 704 /* set vertical timings */ 705 v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; 706 v_active = var->yres; 707 v_blank_start = var->yres + var->lower_margin; 708 v_blank_end = var->yres + var->lower_margin + var->vsync_len; 709 v_sync_start = var->yres + var->lower_margin; 710 v_sync_end = var->yres + var->lower_margin + var->vsync_len; 711 712 temp = ((v_total - 1) << 16) | (v_active - 1); 713 status = ufx_reg_write(dev, 0x2014, temp); 714 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014"); 715 716 temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1); 717 status = ufx_reg_write(dev, 0x2018, temp); 718 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018"); 719 720 temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1); 721 status = ufx_reg_write(dev, 0x201C, temp); 722 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C"); 723 724 status = ufx_reg_write(dev, 0x2020, 0x00000000); 725 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020"); 726 727 status = ufx_reg_write(dev, 0x2024, 0x00000000); 728 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024"); 729 730 /* Set the frame length register (#pix * 2 bytes/pixel) */ 731 temp = var->xres * var->yres * 2; 732 temp = (temp + 7) & (~0x7); 733 status = ufx_reg_write(dev, 0x2028, temp); 734 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028"); 735 736 /* enable desired output interface & disable others */ 737 status = ufx_reg_write(dev, 0x2040, 0); 738 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); 739 740 status = ufx_reg_write(dev, 0x2044, 0); 741 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044"); 742 743 status = ufx_reg_write(dev, 0x2048, 0); 744 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048"); 745 746 /* set the sync polarities & enable bit */ 747 temp = 0x00000001; 748 if (var->sync & FB_SYNC_HOR_HIGH_ACT) 749 temp |= 0x00000010; 750 751 if (var->sync & FB_SYNC_VERT_HIGH_ACT) 752 temp |= 0x00000008; 753 754 status = ufx_reg_write(dev, 0x2040, temp); 755 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040"); 756 757 /* start everything back up */ 758 status = ufx_enable(dev, true); 759 check_warn_return(status, "ufx_set_vid_mode error enabling display"); 760 761 /* Unblank the display */ 762 status = ufx_unblank(dev, true); 763 check_warn_return(status, "ufx_set_vid_mode error unblanking display"); 764 765 /* enable RGB pad */ 766 status = ufx_reg_write(dev, 0x8028, 0x00000003); 767 check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad"); 768 769 /* enable VDAC */ 770 status = ufx_reg_write(dev, 0x8024, 0x00000007); 771 check_warn_return(status, "ufx_set_vid_mode error enabling VDAC"); 772 773 return 0; 774 } 775 776 static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma) 777 { 778 unsigned long start = vma->vm_start; 779 unsigned long size = vma->vm_end - vma->vm_start; 780 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 781 unsigned long page, pos; 782 783 if (info->fbdefio) 784 return fb_deferred_io_mmap(info, vma); 785 786 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) 787 return -EINVAL; 788 if (size > info->fix.smem_len) 789 return -EINVAL; 790 if (offset > info->fix.smem_len - size) 791 return -EINVAL; 792 793 pos = (unsigned long)info->fix.smem_start + offset; 794 795 pr_debug("mmap() framebuffer addr:%lu size:%lu\n", 796 pos, size); 797 798 while (size > 0) { 799 page = vmalloc_to_pfn((void *)pos); 800 if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED)) 801 return -EAGAIN; 802 803 start += PAGE_SIZE; 804 pos += PAGE_SIZE; 805 if (size > PAGE_SIZE) 806 size -= PAGE_SIZE; 807 else 808 size = 0; 809 } 810 811 return 0; 812 } 813 814 static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y, 815 int width, int height) 816 { 817 size_t packed_line_len = ALIGN((width * 2), 4); 818 size_t packed_rect_len = packed_line_len * height; 819 int line; 820 821 BUG_ON(!dev); 822 BUG_ON(!dev->info); 823 824 /* command word */ 825 *((u32 *)&cmd[0]) = cpu_to_le32(0x01); 826 827 /* length word */ 828 *((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16); 829 830 cmd[4] = cpu_to_le16(x); 831 cmd[5] = cpu_to_le16(y); 832 cmd[6] = cpu_to_le16(width); 833 cmd[7] = cpu_to_le16(height); 834 835 /* frame base address */ 836 *((u32 *)&cmd[8]) = cpu_to_le32(0); 837 838 /* color mode and horizontal resolution */ 839 cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres); 840 841 /* vertical resolution */ 842 cmd[11] = cpu_to_le16(dev->info->var.yres); 843 844 /* packed data */ 845 for (line = 0; line < height; line++) { 846 const int line_offset = dev->info->fix.line_length * (y + line); 847 const int byte_offset = line_offset + (x * BPP); 848 memcpy(&cmd[(24 + (packed_line_len * line)) / 2], 849 (char *)dev->info->fix.smem_start + byte_offset, width * BPP); 850 } 851 } 852 853 static int ufx_handle_damage(struct ufx_data *dev, int x, int y, 854 int width, int height) 855 { 856 size_t packed_line_len = ALIGN((width * 2), 4); 857 int len, status, urb_lines, start_line = 0; 858 859 if ((width <= 0) || (height <= 0) || 860 (x + width > dev->info->var.xres) || 861 (y + height > dev->info->var.yres)) 862 return -EINVAL; 863 864 if (!atomic_read(&dev->usb_active)) 865 return 0; 866 867 while (start_line < height) { 868 struct urb *urb = ufx_get_urb(dev); 869 if (!urb) { 870 pr_warn("ufx_handle_damage unable to get urb"); 871 return 0; 872 } 873 874 /* assume we have enough space to transfer at least one line */ 875 BUG_ON(urb->transfer_buffer_length < (24 + (width * 2))); 876 877 /* calculate the maximum number of lines we could fit in */ 878 urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len; 879 880 /* but we might not need this many */ 881 urb_lines = min(urb_lines, (height - start_line)); 882 883 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length); 884 885 ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines); 886 len = 24 + (packed_line_len * urb_lines); 887 888 status = ufx_submit_urb(dev, urb, len); 889 check_warn_return(status, "Error submitting URB"); 890 891 start_line += urb_lines; 892 } 893 894 return 0; 895 } 896 897 /* NOTE: fb_defio.c is holding info->fbdefio.mutex 898 * Touching ANY framebuffer memory that triggers a page fault 899 * in fb_defio will cause a deadlock, when it also tries to 900 * grab the same mutex. */ 901 static void ufx_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist) 902 { 903 struct ufx_data *dev = info->par; 904 struct fb_deferred_io_pageref *pageref; 905 906 if (!fb_defio) 907 return; 908 909 if (!atomic_read(&dev->usb_active)) 910 return; 911 912 /* walk the written page list and render each to device */ 913 list_for_each_entry(pageref, pagereflist, list) { 914 /* create a rectangle of full screen width that encloses the 915 * entire dirty framebuffer page */ 916 const int x = 0; 917 const int width = dev->info->var.xres; 918 const int y = pageref->offset / (width * 2); 919 int height = (PAGE_SIZE / (width * 2)) + 1; 920 height = min(height, (int)(dev->info->var.yres - y)); 921 922 BUG_ON(y >= dev->info->var.yres); 923 BUG_ON((y + height) > dev->info->var.yres); 924 925 ufx_handle_damage(dev, x, y, width, height); 926 } 927 } 928 929 static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd, 930 unsigned long arg) 931 { 932 struct ufx_data *dev = info->par; 933 struct dloarea *area = NULL; 934 935 if (!atomic_read(&dev->usb_active)) 936 return 0; 937 938 /* TODO: Update X server to get this from sysfs instead */ 939 if (cmd == UFX_IOCTL_RETURN_EDID) { 940 u8 __user *edid = (u8 __user *)arg; 941 if (copy_to_user(edid, dev->edid, dev->edid_size)) 942 return -EFAULT; 943 return 0; 944 } 945 946 /* TODO: Help propose a standard fb.h ioctl to report mmap damage */ 947 if (cmd == UFX_IOCTL_REPORT_DAMAGE) { 948 /* If we have a damage-aware client, turn fb_defio "off" 949 * To avoid perf imact of unnecessary page fault handling. 950 * Done by resetting the delay for this fb_info to a very 951 * long period. Pages will become writable and stay that way. 952 * Reset to normal value when all clients have closed this fb. 953 */ 954 if (info->fbdefio) 955 info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE; 956 957 area = (struct dloarea *)arg; 958 959 if (area->x < 0) 960 area->x = 0; 961 962 if (area->x > info->var.xres) 963 area->x = info->var.xres; 964 965 if (area->y < 0) 966 area->y = 0; 967 968 if (area->y > info->var.yres) 969 area->y = info->var.yres; 970 971 ufx_handle_damage(dev, area->x, area->y, area->w, area->h); 972 } 973 974 return 0; 975 } 976 977 /* taken from vesafb */ 978 static int 979 ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green, 980 unsigned blue, unsigned transp, struct fb_info *info) 981 { 982 int err = 0; 983 984 if (regno >= info->cmap.len) 985 return 1; 986 987 if (regno < 16) { 988 if (info->var.red.offset == 10) { 989 /* 1:5:5:5 */ 990 ((u32 *) (info->pseudo_palette))[regno] = 991 ((red & 0xf800) >> 1) | 992 ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); 993 } else { 994 /* 0:5:6:5 */ 995 ((u32 *) (info->pseudo_palette))[regno] = 996 ((red & 0xf800)) | 997 ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11); 998 } 999 } 1000 1001 return err; 1002 } 1003 1004 /* It's common for several clients to have framebuffer open simultaneously. 1005 * e.g. both fbcon and X. Makes things interesting. 1006 * Assumes caller is holding info->lock (for open and release at least) */ 1007 static int ufx_ops_open(struct fb_info *info, int user) 1008 { 1009 struct ufx_data *dev = info->par; 1010 1011 /* fbcon aggressively connects to first framebuffer it finds, 1012 * preventing other clients (X) from working properly. Usually 1013 * not what the user wants. Fail by default with option to enable. */ 1014 if (user == 0 && !console) 1015 return -EBUSY; 1016 1017 mutex_lock(&disconnect_mutex); 1018 1019 /* If the USB device is gone, we don't accept new opens */ 1020 if (dev->virtualized) { 1021 mutex_unlock(&disconnect_mutex); 1022 return -ENODEV; 1023 } 1024 1025 dev->fb_count++; 1026 1027 kref_get(&dev->kref); 1028 1029 if (fb_defio && (info->fbdefio == NULL)) { 1030 /* enable defio at last moment if not disabled by client */ 1031 1032 struct fb_deferred_io *fbdefio; 1033 1034 fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL); 1035 if (fbdefio) { 1036 fbdefio->delay = UFX_DEFIO_WRITE_DELAY; 1037 fbdefio->deferred_io = ufx_dpy_deferred_io; 1038 } 1039 1040 info->fbdefio = fbdefio; 1041 fb_deferred_io_init(info); 1042 } 1043 1044 pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d", 1045 info->node, user, info, dev->fb_count); 1046 1047 mutex_unlock(&disconnect_mutex); 1048 1049 return 0; 1050 } 1051 1052 /* 1053 * Called when all client interfaces to start transactions have been disabled, 1054 * and all references to our device instance (ufx_data) are released. 1055 * Every transaction must have a reference, so we know are fully spun down 1056 */ 1057 static void ufx_free(struct kref *kref) 1058 { 1059 struct ufx_data *dev = container_of(kref, struct ufx_data, kref); 1060 1061 kfree(dev); 1062 } 1063 1064 static void ufx_ops_destory(struct fb_info *info) 1065 { 1066 struct ufx_data *dev = info->par; 1067 int node = info->node; 1068 1069 /* Assume info structure is freed after this point */ 1070 framebuffer_release(info); 1071 1072 pr_debug("fb_info for /dev/fb%d has been freed", node); 1073 1074 /* release reference taken by kref_init in probe() */ 1075 kref_put(&dev->kref, ufx_free); 1076 } 1077 1078 1079 static void ufx_release_urb_work(struct work_struct *work) 1080 { 1081 struct urb_node *unode = container_of(work, struct urb_node, 1082 release_urb_work.work); 1083 1084 up(&unode->dev->urbs.limit_sem); 1085 } 1086 1087 static void ufx_free_framebuffer(struct ufx_data *dev) 1088 { 1089 struct fb_info *info = dev->info; 1090 1091 if (info->cmap.len != 0) 1092 fb_dealloc_cmap(&info->cmap); 1093 if (info->monspecs.modedb) 1094 fb_destroy_modedb(info->monspecs.modedb); 1095 vfree(info->screen_buffer); 1096 1097 fb_destroy_modelist(&info->modelist); 1098 1099 dev->info = NULL; 1100 1101 /* ref taken in probe() as part of registering framebfufer */ 1102 kref_put(&dev->kref, ufx_free); 1103 } 1104 1105 /* 1106 * Assumes caller is holding info->lock mutex (for open and release at least) 1107 */ 1108 static int ufx_ops_release(struct fb_info *info, int user) 1109 { 1110 struct ufx_data *dev = info->par; 1111 1112 mutex_lock(&disconnect_mutex); 1113 1114 dev->fb_count--; 1115 1116 /* We can't free fb_info here - fbmem will touch it when we return */ 1117 if (dev->virtualized && (dev->fb_count == 0)) 1118 ufx_free_framebuffer(dev); 1119 1120 if ((dev->fb_count == 0) && (info->fbdefio)) { 1121 fb_deferred_io_cleanup(info); 1122 kfree(info->fbdefio); 1123 info->fbdefio = NULL; 1124 } 1125 1126 pr_debug("released /dev/fb%d user=%d count=%d", 1127 info->node, user, dev->fb_count); 1128 1129 kref_put(&dev->kref, ufx_free); 1130 1131 mutex_unlock(&disconnect_mutex); 1132 1133 return 0; 1134 } 1135 1136 /* Check whether a video mode is supported by the chip 1137 * We start from monitor's modes, so don't need to filter that here */ 1138 static int ufx_is_valid_mode(struct fb_videomode *mode, 1139 struct fb_info *info) 1140 { 1141 if ((mode->xres * mode->yres) > (2048 * 1152)) { 1142 pr_debug("%dx%d too many pixels", 1143 mode->xres, mode->yres); 1144 return 0; 1145 } 1146 1147 if (mode->pixclock < 5000) { 1148 pr_debug("%dx%d %dps pixel clock too fast", 1149 mode->xres, mode->yres, mode->pixclock); 1150 return 0; 1151 } 1152 1153 pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres, 1154 mode->pixclock, (1000000 / mode->pixclock)); 1155 return 1; 1156 } 1157 1158 static void ufx_var_color_format(struct fb_var_screeninfo *var) 1159 { 1160 const struct fb_bitfield red = { 11, 5, 0 }; 1161 const struct fb_bitfield green = { 5, 6, 0 }; 1162 const struct fb_bitfield blue = { 0, 5, 0 }; 1163 1164 var->bits_per_pixel = 16; 1165 var->red = red; 1166 var->green = green; 1167 var->blue = blue; 1168 } 1169 1170 static int ufx_ops_check_var(struct fb_var_screeninfo *var, 1171 struct fb_info *info) 1172 { 1173 struct fb_videomode mode; 1174 1175 /* TODO: support dynamically changing framebuffer size */ 1176 if ((var->xres * var->yres * 2) > info->fix.smem_len) 1177 return -EINVAL; 1178 1179 /* set device-specific elements of var unrelated to mode */ 1180 ufx_var_color_format(var); 1181 1182 fb_var_to_videomode(&mode, var); 1183 1184 if (!ufx_is_valid_mode(&mode, info)) 1185 return -EINVAL; 1186 1187 return 0; 1188 } 1189 1190 static int ufx_ops_set_par(struct fb_info *info) 1191 { 1192 struct ufx_data *dev = info->par; 1193 int result; 1194 u16 *pix_framebuffer; 1195 int i; 1196 1197 pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres); 1198 result = ufx_set_vid_mode(dev, &info->var); 1199 1200 if ((result == 0) && (dev->fb_count == 0)) { 1201 /* paint greenscreen */ 1202 pix_framebuffer = (u16 *)info->screen_buffer; 1203 for (i = 0; i < info->fix.smem_len / 2; i++) 1204 pix_framebuffer[i] = 0x37e6; 1205 1206 ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres); 1207 } 1208 1209 /* re-enable defio if previously disabled by damage tracking */ 1210 if (info->fbdefio) 1211 info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY; 1212 1213 return result; 1214 } 1215 1216 /* In order to come back from full DPMS off, we need to set the mode again */ 1217 static int ufx_ops_blank(int blank_mode, struct fb_info *info) 1218 { 1219 struct ufx_data *dev = info->par; 1220 ufx_set_vid_mode(dev, &info->var); 1221 return 0; 1222 } 1223 1224 static void ufx_ops_damage_range(struct fb_info *info, off_t off, size_t len) 1225 { 1226 struct ufx_data *dev = info->par; 1227 int start = max((int)(off / info->fix.line_length), 0); 1228 int lines = min((u32)((len / info->fix.line_length) + 1), (u32)info->var.yres); 1229 1230 ufx_handle_damage(dev, 0, start, info->var.xres, lines); 1231 } 1232 1233 static void ufx_ops_damage_area(struct fb_info *info, u32 x, u32 y, u32 width, u32 height) 1234 { 1235 struct ufx_data *dev = info->par; 1236 1237 ufx_handle_damage(dev, x, y, width, height); 1238 } 1239 1240 FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(ufx_ops, 1241 ufx_ops_damage_range, 1242 ufx_ops_damage_area) 1243 1244 static const struct fb_ops ufx_ops = { 1245 .owner = THIS_MODULE, 1246 __FB_DEFAULT_DEFERRED_OPS_RDWR(ufx_ops), 1247 .fb_setcolreg = ufx_ops_setcolreg, 1248 __FB_DEFAULT_DEFERRED_OPS_DRAW(ufx_ops), 1249 .fb_mmap = ufx_ops_mmap, 1250 .fb_ioctl = ufx_ops_ioctl, 1251 .fb_open = ufx_ops_open, 1252 .fb_release = ufx_ops_release, 1253 .fb_blank = ufx_ops_blank, 1254 .fb_check_var = ufx_ops_check_var, 1255 .fb_set_par = ufx_ops_set_par, 1256 .fb_destroy = ufx_ops_destory, 1257 }; 1258 1259 /* Assumes &info->lock held by caller 1260 * Assumes no active clients have framebuffer open */ 1261 static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info) 1262 { 1263 int old_len = info->fix.smem_len; 1264 int new_len; 1265 unsigned char *old_fb = info->screen_buffer; 1266 unsigned char *new_fb; 1267 1268 pr_debug("Reallocating framebuffer. Addresses will change!"); 1269 1270 new_len = info->fix.line_length * info->var.yres; 1271 1272 if (PAGE_ALIGN(new_len) > old_len) { 1273 /* 1274 * Alloc system memory for virtual framebuffer 1275 */ 1276 new_fb = vmalloc(new_len); 1277 if (!new_fb) 1278 return -ENOMEM; 1279 1280 if (info->screen_buffer) { 1281 memcpy(new_fb, old_fb, old_len); 1282 vfree(info->screen_buffer); 1283 } 1284 1285 info->screen_buffer = new_fb; 1286 info->fix.smem_len = PAGE_ALIGN(new_len); 1287 info->fix.smem_start = (unsigned long) new_fb; 1288 info->flags = smscufx_info_flags; 1289 } 1290 return 0; 1291 } 1292 1293 /* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master, 1294 * restart enabled, but no start byte, enable controller */ 1295 static int ufx_i2c_init(struct ufx_data *dev) 1296 { 1297 u32 tmp; 1298 1299 /* disable the controller before it can be reprogrammed */ 1300 int status = ufx_reg_write(dev, 0x106C, 0x00); 1301 check_warn_return(status, "failed to disable I2C"); 1302 1303 /* Setup the clock count registers 1304 * (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */ 1305 status = ufx_reg_write(dev, 0x1018, 12); 1306 check_warn_return(status, "error writing 0x1018"); 1307 1308 /* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */ 1309 status = ufx_reg_write(dev, 0x1014, 6); 1310 check_warn_return(status, "error writing 0x1014"); 1311 1312 status = ufx_reg_read(dev, 0x1000, &tmp); 1313 check_warn_return(status, "error reading 0x1000"); 1314 1315 /* set speed to std mode */ 1316 tmp &= ~(0x06); 1317 tmp |= 0x02; 1318 1319 /* 7-bit (not 10-bit) addressing */ 1320 tmp &= ~(0x10); 1321 1322 /* enable restart conditions and master mode */ 1323 tmp |= 0x21; 1324 1325 status = ufx_reg_write(dev, 0x1000, tmp); 1326 check_warn_return(status, "error writing 0x1000"); 1327 1328 /* Set normal tx using target address 0 */ 1329 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000); 1330 check_warn_return(status, "error setting TX mode bits in 0x1004"); 1331 1332 /* Enable the controller */ 1333 status = ufx_reg_write(dev, 0x106C, 0x01); 1334 check_warn_return(status, "failed to enable I2C"); 1335 1336 return 0; 1337 } 1338 1339 /* sets the I2C port mux and target address */ 1340 static int ufx_i2c_configure(struct ufx_data *dev) 1341 { 1342 int status = ufx_reg_write(dev, 0x106C, 0x00); 1343 check_warn_return(status, "failed to disable I2C"); 1344 1345 status = ufx_reg_write(dev, 0x3010, 0x00000000); 1346 check_warn_return(status, "failed to write 0x3010"); 1347 1348 /* A0h is std for any EDID, right shifted by one */ 1349 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1)); 1350 check_warn_return(status, "failed to set TAR bits in 0x1004"); 1351 1352 status = ufx_reg_write(dev, 0x106C, 0x01); 1353 check_warn_return(status, "failed to enable I2C"); 1354 1355 return 0; 1356 } 1357 1358 /* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no 1359 * monitor is connected, there is no error except for timeout */ 1360 static int ufx_i2c_wait_busy(struct ufx_data *dev) 1361 { 1362 u32 tmp; 1363 int i, status; 1364 1365 for (i = 0; i < 15; i++) { 1366 status = ufx_reg_read(dev, 0x1100, &tmp); 1367 check_warn_return(status, "0x1100 read failed"); 1368 1369 /* if BUSY is clear, check for error */ 1370 if ((tmp & 0x80000000) == 0) { 1371 if (tmp & 0x20000000) { 1372 pr_warn("I2C read failed, 0x1100=0x%08x", tmp); 1373 return -EIO; 1374 } 1375 1376 return 0; 1377 } 1378 1379 /* perform the first 10 retries without delay */ 1380 if (i >= 10) 1381 msleep(10); 1382 } 1383 1384 pr_warn("I2C access timed out, resetting I2C hardware"); 1385 status = ufx_reg_write(dev, 0x1100, 0x40000000); 1386 check_warn_return(status, "0x1100 write failed"); 1387 1388 return -ETIMEDOUT; 1389 } 1390 1391 /* reads a 128-byte EDID block from the currently selected port and TAR */ 1392 static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len) 1393 { 1394 int i, j, status; 1395 u32 *edid_u32 = (u32 *)edid; 1396 1397 BUG_ON(edid_len != EDID_LENGTH); 1398 1399 status = ufx_i2c_configure(dev); 1400 if (status < 0) { 1401 pr_err("ufx_i2c_configure failed"); 1402 return status; 1403 } 1404 1405 memset(edid, 0xff, EDID_LENGTH); 1406 1407 /* Read the 128-byte EDID as 2 bursts of 64 bytes */ 1408 for (i = 0; i < 2; i++) { 1409 u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8); 1410 status = ufx_reg_write(dev, 0x1100, temp); 1411 check_warn_return(status, "Failed to write 0x1100"); 1412 1413 temp |= 0x80000000; 1414 status = ufx_reg_write(dev, 0x1100, temp); 1415 check_warn_return(status, "Failed to write 0x1100"); 1416 1417 status = ufx_i2c_wait_busy(dev); 1418 check_warn_return(status, "Timeout waiting for I2C BUSY to clear"); 1419 1420 for (j = 0; j < 16; j++) { 1421 u32 data_reg_addr = 0x1110 + (j * 4); 1422 status = ufx_reg_read(dev, data_reg_addr, edid_u32++); 1423 check_warn_return(status, "Error reading i2c data"); 1424 } 1425 } 1426 1427 /* all FF's in the first 16 bytes indicates nothing is connected */ 1428 for (i = 0; i < 16; i++) { 1429 if (edid[i] != 0xFF) { 1430 pr_debug("edid data read successfully"); 1431 return EDID_LENGTH; 1432 } 1433 } 1434 1435 pr_warn("edid data contains all 0xff"); 1436 return -ETIMEDOUT; 1437 } 1438 1439 /* 1) use sw default 1440 * 2) Parse into various fb_info structs 1441 * 3) Allocate virtual framebuffer memory to back highest res mode 1442 * 1443 * Parses EDID into three places used by various parts of fbdev: 1444 * fb_var_screeninfo contains the timing of the monitor's preferred mode 1445 * fb_info.monspecs is full parsed EDID info, including monspecs.modedb 1446 * fb_info.modelist is a linked list of all monitor & VESA modes which work 1447 * 1448 * If EDID is not readable/valid, then modelist is all VESA modes, 1449 * monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode 1450 * Returns 0 if successful */ 1451 static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info, 1452 char *default_edid, size_t default_edid_size) 1453 { 1454 const struct fb_videomode *default_vmode = NULL; 1455 u8 *edid; 1456 int i, result = 0, tries = 3; 1457 1458 if (refcount_read(&info->count)) /* only use mutex if info has been registered */ 1459 mutex_lock(&info->lock); 1460 1461 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 1462 if (!edid) { 1463 result = -ENOMEM; 1464 goto error; 1465 } 1466 1467 fb_destroy_modelist(&info->modelist); 1468 memset(&info->monspecs, 0, sizeof(info->monspecs)); 1469 1470 /* Try to (re)read EDID from hardware first 1471 * EDID data may return, but not parse as valid 1472 * Try again a few times, in case of e.g. analog cable noise */ 1473 while (tries--) { 1474 i = ufx_read_edid(dev, edid, EDID_LENGTH); 1475 1476 if (i >= EDID_LENGTH) 1477 fb_edid_to_monspecs(edid, &info->monspecs); 1478 1479 if (info->monspecs.modedb_len > 0) { 1480 dev->edid = edid; 1481 dev->edid_size = i; 1482 break; 1483 } 1484 } 1485 1486 /* If that fails, use a previously returned EDID if available */ 1487 if (info->monspecs.modedb_len == 0) { 1488 pr_err("Unable to get valid EDID from device/display\n"); 1489 1490 if (dev->edid) { 1491 fb_edid_to_monspecs(dev->edid, &info->monspecs); 1492 if (info->monspecs.modedb_len > 0) 1493 pr_err("Using previously queried EDID\n"); 1494 } 1495 } 1496 1497 /* If that fails, use the default EDID we were handed */ 1498 if (info->monspecs.modedb_len == 0) { 1499 if (default_edid_size >= EDID_LENGTH) { 1500 fb_edid_to_monspecs(default_edid, &info->monspecs); 1501 if (info->monspecs.modedb_len > 0) { 1502 memcpy(edid, default_edid, default_edid_size); 1503 dev->edid = edid; 1504 dev->edid_size = default_edid_size; 1505 pr_err("Using default/backup EDID\n"); 1506 } 1507 } 1508 } 1509 1510 /* If we've got modes, let's pick a best default mode */ 1511 if (info->monspecs.modedb_len > 0) { 1512 1513 for (i = 0; i < info->monspecs.modedb_len; i++) { 1514 if (ufx_is_valid_mode(&info->monspecs.modedb[i], info)) 1515 fb_add_videomode(&info->monspecs.modedb[i], 1516 &info->modelist); 1517 else /* if we've removed top/best mode */ 1518 info->monspecs.misc &= ~FB_MISC_1ST_DETAIL; 1519 } 1520 1521 default_vmode = fb_find_best_display(&info->monspecs, 1522 &info->modelist); 1523 } 1524 1525 /* If everything else has failed, fall back to safe default mode */ 1526 if (default_vmode == NULL) { 1527 1528 struct fb_videomode fb_vmode = {0}; 1529 1530 /* Add the standard VESA modes to our modelist 1531 * Since we don't have EDID, there may be modes that 1532 * overspec monitor and/or are incorrect aspect ratio, etc. 1533 * But at least the user has a chance to choose 1534 */ 1535 for (i = 0; i < VESA_MODEDB_SIZE; i++) { 1536 if (ufx_is_valid_mode((struct fb_videomode *) 1537 &vesa_modes[i], info)) 1538 fb_add_videomode(&vesa_modes[i], 1539 &info->modelist); 1540 } 1541 1542 /* default to resolution safe for projectors 1543 * (since they are most common case without EDID) 1544 */ 1545 fb_vmode.xres = 800; 1546 fb_vmode.yres = 600; 1547 fb_vmode.refresh = 60; 1548 default_vmode = fb_find_nearest_mode(&fb_vmode, 1549 &info->modelist); 1550 } 1551 1552 /* If we have good mode and no active clients */ 1553 if ((default_vmode != NULL) && (dev->fb_count == 0)) { 1554 1555 fb_videomode_to_var(&info->var, default_vmode); 1556 ufx_var_color_format(&info->var); 1557 1558 /* with mode size info, we can now alloc our framebuffer */ 1559 memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix)); 1560 info->fix.line_length = info->var.xres * 1561 (info->var.bits_per_pixel / 8); 1562 1563 result = ufx_realloc_framebuffer(dev, info); 1564 1565 } else 1566 result = -EINVAL; 1567 1568 error: 1569 if (edid && (dev->edid != edid)) 1570 kfree(edid); 1571 1572 if (refcount_read(&info->count)) 1573 mutex_unlock(&info->lock); 1574 1575 return result; 1576 } 1577 1578 static int ufx_usb_probe(struct usb_interface *interface, 1579 const struct usb_device_id *id) 1580 { 1581 struct usb_device *usbdev; 1582 struct ufx_data *dev; 1583 struct fb_info *info; 1584 int retval = -ENOMEM; 1585 u32 id_rev, fpga_rev; 1586 1587 /* usb initialization */ 1588 usbdev = interface_to_usbdev(interface); 1589 BUG_ON(!usbdev); 1590 1591 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1592 if (dev == NULL) { 1593 dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n"); 1594 return -ENOMEM; 1595 } 1596 1597 /* we need to wait for both usb and fbdev to spin down on disconnect */ 1598 kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */ 1599 kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */ 1600 1601 dev->udev = usbdev; 1602 dev->gdev = &usbdev->dev; /* our generic struct device * */ 1603 usb_set_intfdata(interface, dev); 1604 1605 dev_dbg(dev->gdev, "%s %s - serial #%s\n", 1606 usbdev->manufacturer, usbdev->product, usbdev->serial); 1607 dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n", 1608 le16_to_cpu(usbdev->descriptor.idVendor), 1609 le16_to_cpu(usbdev->descriptor.idProduct), 1610 le16_to_cpu(usbdev->descriptor.bcdDevice), dev); 1611 dev_dbg(dev->gdev, "console enable=%d\n", console); 1612 dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio); 1613 1614 if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) { 1615 dev_err(dev->gdev, "ufx_alloc_urb_list failed\n"); 1616 goto put_ref; 1617 } 1618 1619 /* We don't register a new USB class. Our client interface is fbdev */ 1620 1621 /* allocates framebuffer driver structure, not framebuffer memory */ 1622 info = framebuffer_alloc(0, &usbdev->dev); 1623 if (!info) { 1624 dev_err(dev->gdev, "framebuffer_alloc failed\n"); 1625 goto free_urb_list; 1626 } 1627 1628 dev->info = info; 1629 info->par = dev; 1630 info->pseudo_palette = dev->pseudo_palette; 1631 info->fbops = &ufx_ops; 1632 INIT_LIST_HEAD(&info->modelist); 1633 1634 retval = fb_alloc_cmap(&info->cmap, 256, 0); 1635 if (retval < 0) { 1636 dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval); 1637 goto destroy_modedb; 1638 } 1639 1640 retval = ufx_reg_read(dev, 0x3000, &id_rev); 1641 check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval); 1642 dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev); 1643 1644 retval = ufx_reg_read(dev, 0x3004, &fpga_rev); 1645 check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval); 1646 dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev); 1647 1648 dev_dbg(dev->gdev, "resetting device"); 1649 retval = ufx_lite_reset(dev); 1650 check_warn_goto_error(retval, "error %d resetting device", retval); 1651 1652 dev_dbg(dev->gdev, "configuring system clock"); 1653 retval = ufx_config_sys_clk(dev); 1654 check_warn_goto_error(retval, "error %d configuring system clock", retval); 1655 1656 dev_dbg(dev->gdev, "configuring DDR2 controller"); 1657 retval = ufx_config_ddr2(dev); 1658 check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval); 1659 1660 dev_dbg(dev->gdev, "configuring I2C controller"); 1661 retval = ufx_i2c_init(dev); 1662 check_warn_goto_error(retval, "error %d initialising I2C controller", retval); 1663 1664 dev_dbg(dev->gdev, "selecting display mode"); 1665 retval = ufx_setup_modes(dev, info, NULL, 0); 1666 check_warn_goto_error(retval, "unable to find common mode for display and adapter"); 1667 1668 retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001); 1669 if (retval < 0) { 1670 dev_err(dev->gdev, "error %d enabling graphics engine", retval); 1671 goto setup_modes; 1672 } 1673 1674 /* ready to begin using device */ 1675 atomic_set(&dev->usb_active, 1); 1676 1677 dev_dbg(dev->gdev, "checking var"); 1678 retval = ufx_ops_check_var(&info->var, info); 1679 if (retval < 0) { 1680 dev_err(dev->gdev, "error %d ufx_ops_check_var", retval); 1681 goto reset_active; 1682 } 1683 1684 dev_dbg(dev->gdev, "setting par"); 1685 retval = ufx_ops_set_par(info); 1686 if (retval < 0) { 1687 dev_err(dev->gdev, "error %d ufx_ops_set_par", retval); 1688 goto reset_active; 1689 } 1690 1691 dev_dbg(dev->gdev, "registering framebuffer"); 1692 retval = register_framebuffer(info); 1693 if (retval < 0) { 1694 dev_err(dev->gdev, "error %d register_framebuffer", retval); 1695 goto reset_active; 1696 } 1697 1698 dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution." 1699 " Using %dK framebuffer memory\n", info->node, 1700 info->var.xres, info->var.yres, info->fix.smem_len >> 10); 1701 1702 return 0; 1703 1704 reset_active: 1705 atomic_set(&dev->usb_active, 0); 1706 setup_modes: 1707 fb_destroy_modedb(info->monspecs.modedb); 1708 vfree(info->screen_buffer); 1709 fb_destroy_modelist(&info->modelist); 1710 error: 1711 fb_dealloc_cmap(&info->cmap); 1712 destroy_modedb: 1713 framebuffer_release(info); 1714 free_urb_list: 1715 if (dev->urbs.count > 0) 1716 ufx_free_urb_list(dev); 1717 put_ref: 1718 kref_put(&dev->kref, ufx_free); /* ref for framebuffer */ 1719 kref_put(&dev->kref, ufx_free); /* last ref from kref_init */ 1720 return retval; 1721 } 1722 1723 static void ufx_usb_disconnect(struct usb_interface *interface) 1724 { 1725 struct ufx_data *dev; 1726 struct fb_info *info; 1727 1728 mutex_lock(&disconnect_mutex); 1729 1730 dev = usb_get_intfdata(interface); 1731 info = dev->info; 1732 1733 pr_debug("USB disconnect starting\n"); 1734 1735 /* we virtualize until all fb clients release. Then we free */ 1736 dev->virtualized = true; 1737 1738 /* When non-active we'll update virtual framebuffer, but no new urbs */ 1739 atomic_set(&dev->usb_active, 0); 1740 1741 usb_set_intfdata(interface, NULL); 1742 1743 /* if clients still have us open, will be freed on last close */ 1744 if (dev->fb_count == 0) 1745 ufx_free_framebuffer(dev); 1746 1747 /* this function will wait for all in-flight urbs to complete */ 1748 if (dev->urbs.count > 0) 1749 ufx_free_urb_list(dev); 1750 1751 pr_debug("freeing ufx_data %p", dev); 1752 1753 unregister_framebuffer(info); 1754 1755 mutex_unlock(&disconnect_mutex); 1756 } 1757 1758 static struct usb_driver ufx_driver = { 1759 .name = "smscufx", 1760 .probe = ufx_usb_probe, 1761 .disconnect = ufx_usb_disconnect, 1762 .id_table = id_table, 1763 }; 1764 1765 module_usb_driver(ufx_driver); 1766 1767 static void ufx_urb_completion(struct urb *urb) 1768 { 1769 struct urb_node *unode = urb->context; 1770 struct ufx_data *dev = unode->dev; 1771 unsigned long flags; 1772 1773 /* sync/async unlink faults aren't errors */ 1774 if (urb->status) { 1775 if (!(urb->status == -ENOENT || 1776 urb->status == -ECONNRESET || 1777 urb->status == -ESHUTDOWN)) { 1778 pr_err("%s - nonzero write bulk status received: %d\n", 1779 __func__, urb->status); 1780 atomic_set(&dev->lost_pixels, 1); 1781 } 1782 } 1783 1784 urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */ 1785 1786 spin_lock_irqsave(&dev->urbs.lock, flags); 1787 list_add_tail(&unode->entry, &dev->urbs.list); 1788 dev->urbs.available++; 1789 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1790 1791 /* When using fb_defio, we deadlock if up() is called 1792 * while another is waiting. So queue to another process */ 1793 if (fb_defio) 1794 schedule_delayed_work(&unode->release_urb_work, 0); 1795 else 1796 up(&dev->urbs.limit_sem); 1797 } 1798 1799 static void ufx_free_urb_list(struct ufx_data *dev) 1800 { 1801 int count = dev->urbs.count; 1802 struct list_head *node; 1803 struct urb_node *unode; 1804 struct urb *urb; 1805 int ret; 1806 unsigned long flags; 1807 1808 pr_debug("Waiting for completes and freeing all render urbs\n"); 1809 1810 /* keep waiting and freeing, until we've got 'em all */ 1811 while (count--) { 1812 /* Getting interrupted means a leak, but ok at shutdown*/ 1813 ret = down_interruptible(&dev->urbs.limit_sem); 1814 if (ret) 1815 break; 1816 1817 spin_lock_irqsave(&dev->urbs.lock, flags); 1818 1819 node = dev->urbs.list.next; /* have reserved one with sem */ 1820 list_del_init(node); 1821 1822 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1823 1824 unode = list_entry(node, struct urb_node, entry); 1825 urb = unode->urb; 1826 1827 /* Free each separately allocated piece */ 1828 usb_free_coherent(urb->dev, dev->urbs.size, 1829 urb->transfer_buffer, urb->transfer_dma); 1830 usb_free_urb(urb); 1831 kfree(node); 1832 } 1833 } 1834 1835 static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size) 1836 { 1837 int i = 0; 1838 struct urb *urb; 1839 struct urb_node *unode; 1840 char *buf; 1841 1842 spin_lock_init(&dev->urbs.lock); 1843 1844 dev->urbs.size = size; 1845 INIT_LIST_HEAD(&dev->urbs.list); 1846 1847 while (i < count) { 1848 unode = kzalloc(sizeof(*unode), GFP_KERNEL); 1849 if (!unode) 1850 break; 1851 unode->dev = dev; 1852 1853 INIT_DELAYED_WORK(&unode->release_urb_work, 1854 ufx_release_urb_work); 1855 1856 urb = usb_alloc_urb(0, GFP_KERNEL); 1857 if (!urb) { 1858 kfree(unode); 1859 break; 1860 } 1861 unode->urb = urb; 1862 1863 buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL, 1864 &urb->transfer_dma); 1865 if (!buf) { 1866 kfree(unode); 1867 usb_free_urb(urb); 1868 break; 1869 } 1870 1871 /* urb->transfer_buffer_length set to actual before submit */ 1872 usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1), 1873 buf, size, ufx_urb_completion, unode); 1874 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; 1875 1876 list_add_tail(&unode->entry, &dev->urbs.list); 1877 1878 i++; 1879 } 1880 1881 sema_init(&dev->urbs.limit_sem, i); 1882 dev->urbs.count = i; 1883 dev->urbs.available = i; 1884 1885 pr_debug("allocated %d %d byte urbs\n", i, (int) size); 1886 1887 return i; 1888 } 1889 1890 static struct urb *ufx_get_urb(struct ufx_data *dev) 1891 { 1892 int ret = 0; 1893 struct list_head *entry; 1894 struct urb_node *unode; 1895 struct urb *urb = NULL; 1896 unsigned long flags; 1897 1898 /* Wait for an in-flight buffer to complete and get re-queued */ 1899 ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT); 1900 if (ret) { 1901 atomic_set(&dev->lost_pixels, 1); 1902 pr_warn("wait for urb interrupted: %x available: %d\n", 1903 ret, dev->urbs.available); 1904 goto error; 1905 } 1906 1907 spin_lock_irqsave(&dev->urbs.lock, flags); 1908 1909 BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */ 1910 entry = dev->urbs.list.next; 1911 list_del_init(entry); 1912 dev->urbs.available--; 1913 1914 spin_unlock_irqrestore(&dev->urbs.lock, flags); 1915 1916 unode = list_entry(entry, struct urb_node, entry); 1917 urb = unode->urb; 1918 1919 error: 1920 return urb; 1921 } 1922 1923 static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len) 1924 { 1925 int ret; 1926 1927 BUG_ON(len > dev->urbs.size); 1928 1929 urb->transfer_buffer_length = len; /* set to actual payload len */ 1930 ret = usb_submit_urb(urb, GFP_KERNEL); 1931 if (ret) { 1932 ufx_urb_completion(urb); /* because no one else will */ 1933 atomic_set(&dev->lost_pixels, 1); 1934 pr_err("usb_submit_urb error %x\n", ret); 1935 } 1936 return ret; 1937 } 1938 1939 module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP); 1940 MODULE_PARM_DESC(console, "Allow fbcon to be used on this display"); 1941 1942 module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP); 1943 MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support"); 1944 1945 MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>"); 1946 MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver"); 1947 MODULE_LICENSE("GPL"); 1948