1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (c) 2017 Cadence 3 // Cadence PCIe controller driver. 4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> 5 6 #ifndef _PCIE_CADENCE_H 7 #define _PCIE_CADENCE_H 8 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/pci-epf.h> 12 #include <linux/phy/phy.h> 13 14 /* Parameters for the waiting for link up routine */ 15 #define LINK_WAIT_MAX_RETRIES 10 16 #define LINK_WAIT_USLEEP_MIN 90000 17 #define LINK_WAIT_USLEEP_MAX 100000 18 19 /* 20 * Local Management Registers 21 */ 22 #define CDNS_PCIE_LM_BASE 0x00100000 23 24 /* Vendor ID Register */ 25 #define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) 26 #define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) 27 #define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 28 #define CDNS_PCIE_LM_ID_VENDOR(vid) \ 29 (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) 30 #define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) 31 #define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 32 #define CDNS_PCIE_LM_ID_SUBSYS(sub) \ 33 (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) 34 35 /* Root Port Requester ID Register */ 36 #define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) 37 #define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) 38 #define CDNS_PCIE_LM_RP_RID_SHIFT 0 39 #define CDNS_PCIE_LM_RP_RID_(rid) \ 40 (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) 41 42 /* Endpoint Bus and Device Number Register */ 43 #define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) 44 #define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) 45 #define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 46 #define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) 47 #define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 48 49 /* Endpoint Function f BAR b Configuration Registers */ 50 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ 51 (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) 52 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ 53 (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) 54 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ 55 (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) 56 #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ 57 (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) 58 #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ 59 (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) 60 #define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ 61 (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) 62 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ 63 (GENMASK(4, 0) << ((b) * 8)) 64 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ 65 (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) 66 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ 67 (GENMASK(7, 5) << ((b) * 8)) 68 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ 69 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) 70 71 /* Endpoint Function Configuration Register */ 72 #define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) 73 74 /* Root Complex BAR Configuration Register */ 75 #define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) 76 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) 77 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ 78 (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) 79 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) 80 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ 81 (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) 82 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) 83 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ 84 (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) 85 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) 86 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ 87 (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) 88 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) 89 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 90 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) 91 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) 92 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 93 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) 94 #define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) 95 96 /* BAR control values applicable to both Endpoint Function and Root Complex */ 97 #define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 98 #define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 99 #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 100 #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 101 #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 102 #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 103 104 #define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ 105 (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) 106 #define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ 107 (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) 108 #define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ 109 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) 110 #define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ 111 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) 112 #define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ 113 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) 114 #define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ 115 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) 116 #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ 117 (((aperture) - 2) << ((bar) * 8)) 118 119 /* PTM Control Register */ 120 #define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) 121 #define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) 122 123 /* 124 * Endpoint Function Registers (PCI configuration space for endpoint functions) 125 */ 126 #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) 127 128 #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 129 #define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 130 #define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 131 #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 132 133 /* 134 * Root Port Registers (PCI configuration space for the root port function) 135 */ 136 #define CDNS_PCIE_RP_BASE 0x00200000 137 #define CDNS_PCIE_RP_CAP_OFFSET 0xc0 138 139 /* 140 * Address Translation Registers 141 */ 142 #define CDNS_PCIE_AT_BASE 0x00400000 143 144 /* Region r Outbound AXI to PCIe Address Translation Register 0 */ 145 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ 146 (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) 147 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) 148 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ 149 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) 150 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) 151 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ 152 (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) 153 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) 154 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ 155 (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) 156 157 /* Region r Outbound AXI to PCIe Address Translation Register 1 */ 158 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ 159 (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) 160 161 /* Region r Outbound PCIe Descriptor Register 0 */ 162 #define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ 163 (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) 164 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) 165 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 166 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 167 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa 168 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb 169 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc 170 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd 171 /* Bit 23 MUST be set in RC mode. */ 172 #define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) 173 #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) 174 #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ 175 (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) 176 177 /* Region r Outbound PCIe Descriptor Register 1 */ 178 #define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ 179 (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) 180 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) 181 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ 182 ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) 183 184 /* Region r AXI Region Base Address Register 0 */ 185 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ 186 (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) 187 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) 188 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ 189 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) 190 191 /* Region r AXI Region Base Address Register 1 */ 192 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ 193 (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) 194 195 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */ 196 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ 197 (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) 198 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) 199 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ 200 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) 201 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ 202 (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) 203 204 /* AXI link down register */ 205 #define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) 206 207 /* LTSSM Capabilities register */ 208 #define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) 209 #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) 210 #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 211 #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ 212 (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ 213 CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) 214 215 enum cdns_pcie_rp_bar { 216 RP_BAR_UNDEFINED = -1, 217 RP_BAR0, 218 RP_BAR1, 219 RP_NO_BAR 220 }; 221 222 #define CDNS_PCIE_RP_MAX_IB 0x3 223 #define CDNS_PCIE_MAX_OB 32 224 225 struct cdns_pcie_rp_ib_bar { 226 u64 size; 227 bool free; 228 }; 229 230 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ 231 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ 232 (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) 233 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ 234 (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) 235 236 /* Normal/Vendor specific message access: offset inside some outbound region */ 237 #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) 238 #define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ 239 (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) 240 #define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) 241 #define CDNS_PCIE_NORMAL_MSG_CODE(code) \ 242 (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) 243 #define CDNS_PCIE_MSG_NO_DATA BIT(16) 244 245 struct cdns_pcie; 246 247 enum cdns_pcie_msg_code { 248 MSG_CODE_ASSERT_INTA = 0x20, 249 MSG_CODE_ASSERT_INTB = 0x21, 250 MSG_CODE_ASSERT_INTC = 0x22, 251 MSG_CODE_ASSERT_INTD = 0x23, 252 MSG_CODE_DEASSERT_INTA = 0x24, 253 MSG_CODE_DEASSERT_INTB = 0x25, 254 MSG_CODE_DEASSERT_INTC = 0x26, 255 MSG_CODE_DEASSERT_INTD = 0x27, 256 }; 257 258 enum cdns_pcie_msg_routing { 259 /* Route to Root Complex */ 260 MSG_ROUTING_TO_RC, 261 262 /* Use Address Routing */ 263 MSG_ROUTING_BY_ADDR, 264 265 /* Use ID Routing */ 266 MSG_ROUTING_BY_ID, 267 268 /* Route as Broadcast Message from Root Complex */ 269 MSG_ROUTING_BCAST, 270 271 /* Local message; terminate at receiver (INTx messages) */ 272 MSG_ROUTING_LOCAL, 273 274 /* Gather & route to Root Complex (PME_TO_Ack message) */ 275 MSG_ROUTING_GATHER, 276 }; 277 278 struct cdns_pcie_ops { 279 int (*start_link)(struct cdns_pcie *pcie); 280 void (*stop_link)(struct cdns_pcie *pcie); 281 bool (*link_up)(struct cdns_pcie *pcie); 282 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); 283 }; 284 285 /** 286 * struct cdns_pcie - private data for Cadence PCIe controller drivers 287 * @reg_base: IO mapped register base 288 * @mem_res: start/end offsets in the physical system memory to map PCI accesses 289 * @dev: PCIe controller 290 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. 291 * @phy_count: number of supported PHY devices 292 * @phy: list of pointers to specific PHY control blocks 293 * @link: list of pointers to corresponding device link representations 294 * @ops: Platform-specific ops to control various inputs from Cadence PCIe 295 * wrapper 296 */ 297 struct cdns_pcie { 298 void __iomem *reg_base; 299 struct resource *mem_res; 300 struct device *dev; 301 bool is_rc; 302 int phy_count; 303 struct phy **phy; 304 struct device_link **link; 305 const struct cdns_pcie_ops *ops; 306 }; 307 308 /** 309 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver 310 * @pcie: Cadence PCIe controller 311 * @dev: pointer to PCIe device 312 * @cfg_res: start/end offsets in the physical system memory to map PCI 313 * configuration space accesses 314 * @cfg_base: IO mapped window to access the PCI configuration space of a 315 * single function at a time 316 * @vendor_id: PCI vendor ID 317 * @device_id: PCI device ID 318 * @avail_ib_bar: Status of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or 319 * available 320 * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 321 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk 322 */ 323 struct cdns_pcie_rc { 324 struct cdns_pcie pcie; 325 struct resource *cfg_res; 326 void __iomem *cfg_base; 327 u32 vendor_id; 328 u32 device_id; 329 bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; 330 unsigned int quirk_retrain_flag:1; 331 unsigned int quirk_detect_quiet_flag:1; 332 }; 333 334 /** 335 * struct cdns_pcie_epf - Structure to hold info about endpoint function 336 * @epf: Info about virtual functions attached to the physical function 337 * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers 338 */ 339 struct cdns_pcie_epf { 340 struct cdns_pcie_epf *epf; 341 struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; 342 }; 343 344 /** 345 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver 346 * @pcie: Cadence PCIe controller 347 * @max_regions: maximum number of regions supported by hardware 348 * @ob_region_map: bitmask of mapped outbound regions 349 * @ob_addr: base addresses in the AXI bus where the outbound regions start 350 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ 351 * dedicated outbound regions is mapped. 352 * @irq_cpu_addr: base address in the CPU space where a write access triggers 353 * the sending of a memory write (MSI) / normal message (legacy 354 * IRQ) TLP through the PCIe bus. 355 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ 356 * dedicated outbound region. 357 * @irq_pci_fn: the latest PCI function that has updated the mapping of 358 * the MSI/legacy IRQ dedicated outbound region. 359 * @irq_pending: bitmask of asserted legacy IRQs. 360 * @lock: spin lock to disable interrupts while modifying PCIe controller 361 * registers fields (RMW) accessible by both remote RC and EP to 362 * minimize time between read and write 363 * @epf: Structure to hold info about endpoint function 364 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk 365 * @quirk_disable_flr: Disable FLR (Function Level Reset) quirk flag 366 */ 367 struct cdns_pcie_ep { 368 struct cdns_pcie pcie; 369 u32 max_regions; 370 unsigned long ob_region_map; 371 phys_addr_t *ob_addr; 372 phys_addr_t irq_phys_addr; 373 void __iomem *irq_cpu_addr; 374 u64 irq_pci_addr; 375 u8 irq_pci_fn; 376 u8 irq_pending; 377 /* protect writing to PCI_STATUS while raising legacy interrupts */ 378 spinlock_t lock; 379 struct cdns_pcie_epf *epf; 380 unsigned int quirk_detect_quiet_flag:1; 381 unsigned int quirk_disable_flr:1; 382 }; 383 384 385 /* Register access */ 386 static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) 387 { 388 writel(value, pcie->reg_base + reg); 389 } 390 391 static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) 392 { 393 return readl(pcie->reg_base + reg); 394 } 395 396 static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) 397 { 398 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); 399 unsigned int offset = (unsigned long)addr & 0x3; 400 u32 val = readl(aligned_addr); 401 402 if (!IS_ALIGNED((uintptr_t)addr, size)) { 403 pr_warn("Address %p and size %d are not aligned\n", addr, size); 404 return 0; 405 } 406 407 if (size > 2) 408 return val; 409 410 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); 411 } 412 413 static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value) 414 { 415 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); 416 unsigned int offset = (unsigned long)addr & 0x3; 417 u32 mask; 418 u32 val; 419 420 if (!IS_ALIGNED((uintptr_t)addr, size)) { 421 pr_warn("Address %p and size %d are not aligned\n", addr, size); 422 return; 423 } 424 425 if (size > 2) { 426 writel(value, addr); 427 return; 428 } 429 430 mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); 431 val = readl(aligned_addr) & mask; 432 val |= value << (offset * 8); 433 writel(val, aligned_addr); 434 } 435 436 /* Root Port register access */ 437 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, 438 u32 reg, u8 value) 439 { 440 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 441 442 cdns_pcie_write_sz(addr, 0x1, value); 443 } 444 445 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, 446 u32 reg, u16 value) 447 { 448 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 449 450 cdns_pcie_write_sz(addr, 0x2, value); 451 } 452 453 static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) 454 { 455 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 456 457 return cdns_pcie_read_sz(addr, 0x2); 458 } 459 460 /* Endpoint Function register access */ 461 static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, 462 u32 reg, u8 value) 463 { 464 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 465 466 cdns_pcie_write_sz(addr, 0x1, value); 467 } 468 469 static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, 470 u32 reg, u16 value) 471 { 472 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 473 474 cdns_pcie_write_sz(addr, 0x2, value); 475 } 476 477 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, 478 u32 reg, u32 value) 479 { 480 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); 481 } 482 483 static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) 484 { 485 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 486 487 return cdns_pcie_read_sz(addr, 0x2); 488 } 489 490 static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) 491 { 492 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); 493 } 494 495 static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) 496 { 497 if (pcie->ops->start_link) 498 return pcie->ops->start_link(pcie); 499 500 return 0; 501 } 502 503 static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) 504 { 505 if (pcie->ops->stop_link) 506 pcie->ops->stop_link(pcie); 507 } 508 509 static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) 510 { 511 if (pcie->ops->link_up) 512 return pcie->ops->link_up(pcie); 513 514 return true; 515 } 516 517 #ifdef CONFIG_PCIE_CADENCE_HOST 518 int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); 519 void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 520 int where); 521 #else 522 static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) 523 { 524 return 0; 525 } 526 527 static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 528 int where) 529 { 530 return NULL; 531 } 532 #endif 533 534 #ifdef CONFIG_PCIE_CADENCE_EP 535 int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); 536 #else 537 static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 538 { 539 return 0; 540 } 541 #endif 542 543 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); 544 545 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, 546 u32 r, bool is_io, 547 u64 cpu_addr, u64 pci_addr, size_t size); 548 549 void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, 550 u8 busnr, u8 fn, 551 u32 r, u64 cpu_addr); 552 553 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); 554 void cdns_pcie_disable_phy(struct cdns_pcie *pcie); 555 int cdns_pcie_enable_phy(struct cdns_pcie *pcie); 556 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); 557 extern const struct dev_pm_ops cdns_pcie_pm_ops; 558 559 #endif /* _PCIE_CADENCE_H */ 560