1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2020, MIPI Alliance, Inc. 4 * 5 * Author: Nicolas Pitre <npitre@baylibre.com> 6 * 7 * Core driver code with main interface to the I3C subsystem. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/device.h> 12 #include <linux/errno.h> 13 #include <linux/i3c/master.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/iopoll.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 20 #include "hci.h" 21 #include "ext_caps.h" 22 #include "cmd.h" 23 #include "dat.h" 24 25 26 /* 27 * Host Controller Capabilities and Operation Registers 28 */ 29 30 #define reg_read(r) readl(hci->base_regs + (r)) 31 #define reg_write(r, v) writel(v, hci->base_regs + (r)) 32 #define reg_set(r, v) reg_write(r, reg_read(r) | (v)) 33 #define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v)) 34 35 #define HCI_VERSION 0x00 /* HCI Version (in BCD) */ 36 37 #define HC_CONTROL 0x04 38 #define HC_CONTROL_BUS_ENABLE BIT(31) 39 #define HC_CONTROL_RESUME BIT(30) 40 #define HC_CONTROL_ABORT BIT(29) 41 #define HC_CONTROL_HALT_ON_CMD_TIMEOUT BIT(12) 42 #define HC_CONTROL_HOT_JOIN_CTRL BIT(8) /* Hot-Join ACK/NACK Control */ 43 #define HC_CONTROL_I2C_TARGET_PRESENT BIT(7) 44 #define HC_CONTROL_PIO_MODE BIT(6) /* DMA/PIO Mode Selector */ 45 #define HC_CONTROL_DATA_BIG_ENDIAN BIT(4) 46 #define HC_CONTROL_IBA_INCLUDE BIT(0) /* Include I3C Broadcast Address */ 47 48 #define MASTER_DEVICE_ADDR 0x08 /* Master Device Address */ 49 #define MASTER_DYNAMIC_ADDR_VALID BIT(31) /* Dynamic Address is Valid */ 50 #define MASTER_DYNAMIC_ADDR(v) FIELD_PREP(GENMASK(22, 16), v) 51 52 #define HC_CAPABILITIES 0x0c 53 #define HC_CAP_SG_DC_EN BIT(30) 54 #define HC_CAP_SG_IBI_EN BIT(29) 55 #define HC_CAP_SG_CR_EN BIT(28) 56 #define HC_CAP_MAX_DATA_LENGTH GENMASK(24, 22) 57 #define HC_CAP_CMD_SIZE GENMASK(21, 20) 58 #define HC_CAP_DIRECT_COMMANDS_EN BIT(18) 59 #define HC_CAP_MULTI_LANE_EN BIT(15) 60 #define HC_CAP_CMD_CCC_DEFBYTE BIT(10) 61 #define HC_CAP_HDR_BT_EN BIT(8) 62 #define HC_CAP_HDR_TS_EN BIT(7) 63 #define HC_CAP_HDR_DDR_EN BIT(6) 64 #define HC_CAP_NON_CURRENT_MASTER_CAP BIT(5) /* master handoff capable */ 65 #define HC_CAP_DATA_BYTE_CFG_EN BIT(4) /* endian selection possible */ 66 #define HC_CAP_AUTO_COMMAND BIT(3) 67 #define HC_CAP_COMBO_COMMAND BIT(2) 68 69 #define RESET_CONTROL 0x10 70 #define BUS_RESET BIT(31) 71 #define BUS_RESET_TYPE GENMASK(30, 29) 72 #define IBI_QUEUE_RST BIT(5) 73 #define RX_FIFO_RST BIT(4) 74 #define TX_FIFO_RST BIT(3) 75 #define RESP_QUEUE_RST BIT(2) 76 #define CMD_QUEUE_RST BIT(1) 77 #define SOFT_RST BIT(0) /* Core Reset */ 78 79 #define PRESENT_STATE 0x14 80 #define STATE_CURRENT_MASTER BIT(2) 81 82 #define INTR_STATUS 0x20 83 #define INTR_STATUS_ENABLE 0x24 84 #define INTR_SIGNAL_ENABLE 0x28 85 #define INTR_FORCE 0x2c 86 #define INTR_HC_CMD_SEQ_UFLOW_STAT BIT(12) /* Cmd Sequence Underflow */ 87 #define INTR_HC_RESET_CANCEL BIT(11) /* HC Cancelled Reset */ 88 #define INTR_HC_INTERNAL_ERR BIT(10) /* HC Internal Error */ 89 #define INTR_HC_PIO BIT(8) /* cascaded PIO interrupt */ 90 #define INTR_HC_RINGS GENMASK(7, 0) 91 92 #define DAT_SECTION 0x30 /* Device Address Table */ 93 #define DAT_ENTRY_SIZE GENMASK(31, 28) 94 #define DAT_TABLE_SIZE GENMASK(18, 12) 95 #define DAT_TABLE_OFFSET GENMASK(11, 0) 96 97 #define DCT_SECTION 0x34 /* Device Characteristics Table */ 98 #define DCT_ENTRY_SIZE GENMASK(31, 28) 99 #define DCT_TABLE_INDEX GENMASK(23, 19) 100 #define DCT_TABLE_SIZE GENMASK(18, 12) 101 #define DCT_TABLE_OFFSET GENMASK(11, 0) 102 103 #define RING_HEADERS_SECTION 0x38 104 #define RING_HEADERS_OFFSET GENMASK(15, 0) 105 106 #define PIO_SECTION 0x3c 107 #define PIO_REGS_OFFSET GENMASK(15, 0) /* PIO Offset */ 108 109 #define EXT_CAPS_SECTION 0x40 110 #define EXT_CAPS_OFFSET GENMASK(15, 0) 111 112 #define IBI_NOTIFY_CTRL 0x58 /* IBI Notify Control */ 113 #define IBI_NOTIFY_SIR_REJECTED BIT(3) /* Rejected Target Interrupt Request */ 114 #define IBI_NOTIFY_MR_REJECTED BIT(1) /* Rejected Master Request Control */ 115 #define IBI_NOTIFY_HJ_REJECTED BIT(0) /* Rejected Hot-Join Control */ 116 117 #define DEV_CTX_BASE_LO 0x60 118 #define DEV_CTX_BASE_HI 0x64 119 120 121 static inline struct i3c_hci *to_i3c_hci(struct i3c_master_controller *m) 122 { 123 return container_of(m, struct i3c_hci, master); 124 } 125 126 static int i3c_hci_bus_init(struct i3c_master_controller *m) 127 { 128 struct i3c_hci *hci = to_i3c_hci(m); 129 struct i3c_device_info info; 130 int ret; 131 132 DBG(""); 133 134 if (hci->cmd == &mipi_i3c_hci_cmd_v1) { 135 ret = mipi_i3c_hci_dat_v1.init(hci); 136 if (ret) 137 return ret; 138 } 139 140 ret = i3c_master_get_free_addr(m, 0); 141 if (ret < 0) 142 return ret; 143 reg_write(MASTER_DEVICE_ADDR, 144 MASTER_DYNAMIC_ADDR(ret) | MASTER_DYNAMIC_ADDR_VALID); 145 memset(&info, 0, sizeof(info)); 146 info.dyn_addr = ret; 147 ret = i3c_master_set_info(m, &info); 148 if (ret) 149 return ret; 150 151 ret = hci->io->init(hci); 152 if (ret) 153 return ret; 154 155 reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); 156 DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL)); 157 158 return 0; 159 } 160 161 static void i3c_hci_bus_cleanup(struct i3c_master_controller *m) 162 { 163 struct i3c_hci *hci = to_i3c_hci(m); 164 struct platform_device *pdev = to_platform_device(m->dev.parent); 165 166 DBG(""); 167 168 reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE); 169 synchronize_irq(platform_get_irq(pdev, 0)); 170 hci->io->cleanup(hci); 171 if (hci->cmd == &mipi_i3c_hci_cmd_v1) 172 mipi_i3c_hci_dat_v1.cleanup(hci); 173 } 174 175 void mipi_i3c_hci_resume(struct i3c_hci *hci) 176 { 177 reg_set(HC_CONTROL, HC_CONTROL_RESUME); 178 } 179 180 /* located here rather than pio.c because needed bits are in core reg space */ 181 void mipi_i3c_hci_pio_reset(struct i3c_hci *hci) 182 { 183 reg_write(RESET_CONTROL, RX_FIFO_RST | TX_FIFO_RST | RESP_QUEUE_RST); 184 } 185 186 /* located here rather than dct.c because needed bits are in core reg space */ 187 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci) 188 { 189 reg_write(DCT_SECTION, FIELD_PREP(DCT_TABLE_INDEX, 0)); 190 } 191 192 static int i3c_hci_send_ccc_cmd(struct i3c_master_controller *m, 193 struct i3c_ccc_cmd *ccc) 194 { 195 struct i3c_hci *hci = to_i3c_hci(m); 196 struct hci_xfer *xfer; 197 bool raw = !!(hci->quirks & HCI_QUIRK_RAW_CCC); 198 bool prefixed = raw && !!(ccc->id & I3C_CCC_DIRECT); 199 unsigned int nxfers = ccc->ndests + prefixed; 200 DECLARE_COMPLETION_ONSTACK(done); 201 int i, last, ret = 0; 202 203 DBG("cmd=%#x rnw=%d ndests=%d data[0].len=%d", 204 ccc->id, ccc->rnw, ccc->ndests, ccc->dests[0].payload.len); 205 206 xfer = hci_alloc_xfer(nxfers); 207 if (!xfer) 208 return -ENOMEM; 209 210 if (prefixed) { 211 xfer->data = NULL; 212 xfer->data_len = 0; 213 xfer->rnw = false; 214 hci->cmd->prep_ccc(hci, xfer, I3C_BROADCAST_ADDR, 215 ccc->id, true); 216 xfer++; 217 } 218 219 for (i = 0; i < nxfers - prefixed; i++) { 220 xfer[i].data = ccc->dests[i].payload.data; 221 xfer[i].data_len = ccc->dests[i].payload.len; 222 xfer[i].rnw = ccc->rnw; 223 ret = hci->cmd->prep_ccc(hci, &xfer[i], ccc->dests[i].addr, 224 ccc->id, raw); 225 if (ret) 226 goto out; 227 xfer[i].cmd_desc[0] |= CMD_0_ROC; 228 } 229 last = i - 1; 230 xfer[last].cmd_desc[0] |= CMD_0_TOC; 231 xfer[last].completion = &done; 232 233 if (prefixed) 234 xfer--; 235 236 ret = hci->io->queue_xfer(hci, xfer, nxfers); 237 if (ret) 238 goto out; 239 if (!wait_for_completion_timeout(&done, HZ) && 240 hci->io->dequeue_xfer(hci, xfer, nxfers)) { 241 ret = -ETIME; 242 goto out; 243 } 244 for (i = prefixed; i < nxfers; i++) { 245 if (ccc->rnw) 246 ccc->dests[i - prefixed].payload.len = 247 RESP_DATA_LENGTH(xfer[i].response); 248 if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) { 249 ret = -EIO; 250 goto out; 251 } 252 } 253 254 if (ccc->rnw) 255 DBG("got: %*ph", 256 ccc->dests[0].payload.len, ccc->dests[0].payload.data); 257 258 out: 259 hci_free_xfer(xfer, nxfers); 260 return ret; 261 } 262 263 static int i3c_hci_daa(struct i3c_master_controller *m) 264 { 265 struct i3c_hci *hci = to_i3c_hci(m); 266 267 DBG(""); 268 269 return hci->cmd->perform_daa(hci); 270 } 271 272 static int i3c_hci_priv_xfers(struct i3c_dev_desc *dev, 273 struct i3c_priv_xfer *i3c_xfers, 274 int nxfers) 275 { 276 struct i3c_master_controller *m = i3c_dev_get_master(dev); 277 struct i3c_hci *hci = to_i3c_hci(m); 278 struct hci_xfer *xfer; 279 DECLARE_COMPLETION_ONSTACK(done); 280 unsigned int size_limit; 281 int i, last, ret = 0; 282 283 DBG("nxfers = %d", nxfers); 284 285 xfer = hci_alloc_xfer(nxfers); 286 if (!xfer) 287 return -ENOMEM; 288 289 size_limit = 1U << (16 + FIELD_GET(HC_CAP_MAX_DATA_LENGTH, hci->caps)); 290 291 for (i = 0; i < nxfers; i++) { 292 xfer[i].data_len = i3c_xfers[i].len; 293 ret = -EFBIG; 294 if (xfer[i].data_len >= size_limit) 295 goto out; 296 xfer[i].rnw = i3c_xfers[i].rnw; 297 if (i3c_xfers[i].rnw) { 298 xfer[i].data = i3c_xfers[i].data.in; 299 } else { 300 /* silence the const qualifier warning with a cast */ 301 xfer[i].data = (void *) i3c_xfers[i].data.out; 302 } 303 hci->cmd->prep_i3c_xfer(hci, dev, &xfer[i]); 304 xfer[i].cmd_desc[0] |= CMD_0_ROC; 305 } 306 last = i - 1; 307 xfer[last].cmd_desc[0] |= CMD_0_TOC; 308 xfer[last].completion = &done; 309 310 ret = hci->io->queue_xfer(hci, xfer, nxfers); 311 if (ret) 312 goto out; 313 if (!wait_for_completion_timeout(&done, HZ) && 314 hci->io->dequeue_xfer(hci, xfer, nxfers)) { 315 ret = -ETIME; 316 goto out; 317 } 318 for (i = 0; i < nxfers; i++) { 319 if (i3c_xfers[i].rnw) 320 i3c_xfers[i].len = RESP_DATA_LENGTH(xfer[i].response); 321 if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) { 322 ret = -EIO; 323 goto out; 324 } 325 } 326 327 out: 328 hci_free_xfer(xfer, nxfers); 329 return ret; 330 } 331 332 static int i3c_hci_i2c_xfers(struct i2c_dev_desc *dev, 333 const struct i2c_msg *i2c_xfers, int nxfers) 334 { 335 struct i3c_master_controller *m = i2c_dev_get_master(dev); 336 struct i3c_hci *hci = to_i3c_hci(m); 337 struct hci_xfer *xfer; 338 DECLARE_COMPLETION_ONSTACK(done); 339 int i, last, ret = 0; 340 341 DBG("nxfers = %d", nxfers); 342 343 xfer = hci_alloc_xfer(nxfers); 344 if (!xfer) 345 return -ENOMEM; 346 347 for (i = 0; i < nxfers; i++) { 348 xfer[i].data = i2c_xfers[i].buf; 349 xfer[i].data_len = i2c_xfers[i].len; 350 xfer[i].rnw = i2c_xfers[i].flags & I2C_M_RD; 351 hci->cmd->prep_i2c_xfer(hci, dev, &xfer[i]); 352 xfer[i].cmd_desc[0] |= CMD_0_ROC; 353 } 354 last = i - 1; 355 xfer[last].cmd_desc[0] |= CMD_0_TOC; 356 xfer[last].completion = &done; 357 358 ret = hci->io->queue_xfer(hci, xfer, nxfers); 359 if (ret) 360 goto out; 361 if (!wait_for_completion_timeout(&done, HZ) && 362 hci->io->dequeue_xfer(hci, xfer, nxfers)) { 363 ret = -ETIME; 364 goto out; 365 } 366 for (i = 0; i < nxfers; i++) { 367 if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) { 368 ret = -EIO; 369 goto out; 370 } 371 } 372 373 out: 374 hci_free_xfer(xfer, nxfers); 375 return ret; 376 } 377 378 static int i3c_hci_attach_i3c_dev(struct i3c_dev_desc *dev) 379 { 380 struct i3c_master_controller *m = i3c_dev_get_master(dev); 381 struct i3c_hci *hci = to_i3c_hci(m); 382 struct i3c_hci_dev_data *dev_data; 383 int ret; 384 385 DBG(""); 386 387 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); 388 if (!dev_data) 389 return -ENOMEM; 390 if (hci->cmd == &mipi_i3c_hci_cmd_v1) { 391 ret = mipi_i3c_hci_dat_v1.alloc_entry(hci); 392 if (ret < 0) { 393 kfree(dev_data); 394 return ret; 395 } 396 mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, ret, dev->info.dyn_addr); 397 dev_data->dat_idx = ret; 398 } 399 i3c_dev_set_master_data(dev, dev_data); 400 return 0; 401 } 402 403 static int i3c_hci_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 old_dyn_addr) 404 { 405 struct i3c_master_controller *m = i3c_dev_get_master(dev); 406 struct i3c_hci *hci = to_i3c_hci(m); 407 struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev); 408 409 DBG(""); 410 411 if (hci->cmd == &mipi_i3c_hci_cmd_v1) 412 mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, dev_data->dat_idx, 413 dev->info.dyn_addr); 414 return 0; 415 } 416 417 static void i3c_hci_detach_i3c_dev(struct i3c_dev_desc *dev) 418 { 419 struct i3c_master_controller *m = i3c_dev_get_master(dev); 420 struct i3c_hci *hci = to_i3c_hci(m); 421 struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev); 422 423 DBG(""); 424 425 i3c_dev_set_master_data(dev, NULL); 426 if (hci->cmd == &mipi_i3c_hci_cmd_v1) 427 mipi_i3c_hci_dat_v1.free_entry(hci, dev_data->dat_idx); 428 kfree(dev_data); 429 } 430 431 static int i3c_hci_attach_i2c_dev(struct i2c_dev_desc *dev) 432 { 433 struct i3c_master_controller *m = i2c_dev_get_master(dev); 434 struct i3c_hci *hci = to_i3c_hci(m); 435 struct i3c_hci_dev_data *dev_data; 436 int ret; 437 438 DBG(""); 439 440 if (hci->cmd != &mipi_i3c_hci_cmd_v1) 441 return 0; 442 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); 443 if (!dev_data) 444 return -ENOMEM; 445 ret = mipi_i3c_hci_dat_v1.alloc_entry(hci); 446 if (ret < 0) { 447 kfree(dev_data); 448 return ret; 449 } 450 mipi_i3c_hci_dat_v1.set_static_addr(hci, ret, dev->addr); 451 mipi_i3c_hci_dat_v1.set_flags(hci, ret, DAT_0_I2C_DEVICE, 0); 452 dev_data->dat_idx = ret; 453 i2c_dev_set_master_data(dev, dev_data); 454 return 0; 455 } 456 457 static void i3c_hci_detach_i2c_dev(struct i2c_dev_desc *dev) 458 { 459 struct i3c_master_controller *m = i2c_dev_get_master(dev); 460 struct i3c_hci *hci = to_i3c_hci(m); 461 struct i3c_hci_dev_data *dev_data = i2c_dev_get_master_data(dev); 462 463 DBG(""); 464 465 if (dev_data) { 466 i2c_dev_set_master_data(dev, NULL); 467 if (hci->cmd == &mipi_i3c_hci_cmd_v1) 468 mipi_i3c_hci_dat_v1.free_entry(hci, dev_data->dat_idx); 469 kfree(dev_data); 470 } 471 } 472 473 static int i3c_hci_request_ibi(struct i3c_dev_desc *dev, 474 const struct i3c_ibi_setup *req) 475 { 476 struct i3c_master_controller *m = i3c_dev_get_master(dev); 477 struct i3c_hci *hci = to_i3c_hci(m); 478 struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev); 479 unsigned int dat_idx = dev_data->dat_idx; 480 481 if (req->max_payload_len != 0) 482 mipi_i3c_hci_dat_v1.set_flags(hci, dat_idx, DAT_0_IBI_PAYLOAD, 0); 483 else 484 mipi_i3c_hci_dat_v1.clear_flags(hci, dat_idx, DAT_0_IBI_PAYLOAD, 0); 485 return hci->io->request_ibi(hci, dev, req); 486 } 487 488 static void i3c_hci_free_ibi(struct i3c_dev_desc *dev) 489 { 490 struct i3c_master_controller *m = i3c_dev_get_master(dev); 491 struct i3c_hci *hci = to_i3c_hci(m); 492 493 hci->io->free_ibi(hci, dev); 494 } 495 496 static int i3c_hci_enable_ibi(struct i3c_dev_desc *dev) 497 { 498 struct i3c_master_controller *m = i3c_dev_get_master(dev); 499 struct i3c_hci *hci = to_i3c_hci(m); 500 struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev); 501 502 mipi_i3c_hci_dat_v1.clear_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT, 0); 503 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 504 } 505 506 static int i3c_hci_disable_ibi(struct i3c_dev_desc *dev) 507 { 508 struct i3c_master_controller *m = i3c_dev_get_master(dev); 509 struct i3c_hci *hci = to_i3c_hci(m); 510 struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev); 511 512 mipi_i3c_hci_dat_v1.set_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT, 0); 513 return i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); 514 } 515 516 static void i3c_hci_recycle_ibi_slot(struct i3c_dev_desc *dev, 517 struct i3c_ibi_slot *slot) 518 { 519 struct i3c_master_controller *m = i3c_dev_get_master(dev); 520 struct i3c_hci *hci = to_i3c_hci(m); 521 522 hci->io->recycle_ibi_slot(hci, dev, slot); 523 } 524 525 static const struct i3c_master_controller_ops i3c_hci_ops = { 526 .bus_init = i3c_hci_bus_init, 527 .bus_cleanup = i3c_hci_bus_cleanup, 528 .do_daa = i3c_hci_daa, 529 .send_ccc_cmd = i3c_hci_send_ccc_cmd, 530 .priv_xfers = i3c_hci_priv_xfers, 531 .i2c_xfers = i3c_hci_i2c_xfers, 532 .attach_i3c_dev = i3c_hci_attach_i3c_dev, 533 .reattach_i3c_dev = i3c_hci_reattach_i3c_dev, 534 .detach_i3c_dev = i3c_hci_detach_i3c_dev, 535 .attach_i2c_dev = i3c_hci_attach_i2c_dev, 536 .detach_i2c_dev = i3c_hci_detach_i2c_dev, 537 .request_ibi = i3c_hci_request_ibi, 538 .free_ibi = i3c_hci_free_ibi, 539 .enable_ibi = i3c_hci_enable_ibi, 540 .disable_ibi = i3c_hci_disable_ibi, 541 .recycle_ibi_slot = i3c_hci_recycle_ibi_slot, 542 }; 543 544 static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id) 545 { 546 struct i3c_hci *hci = dev_id; 547 irqreturn_t result = IRQ_NONE; 548 u32 val; 549 550 val = reg_read(INTR_STATUS); 551 DBG("INTR_STATUS = %#x", val); 552 553 if (val) { 554 reg_write(INTR_STATUS, val); 555 } else { 556 /* v1.0 does not have PIO cascaded notification bits */ 557 val |= INTR_HC_PIO; 558 } 559 560 if (val & INTR_HC_RESET_CANCEL) { 561 DBG("cancelled reset"); 562 val &= ~INTR_HC_RESET_CANCEL; 563 } 564 if (val & INTR_HC_INTERNAL_ERR) { 565 dev_err(&hci->master.dev, "Host Controller Internal Error\n"); 566 val &= ~INTR_HC_INTERNAL_ERR; 567 } 568 if (val & INTR_HC_PIO) { 569 hci->io->irq_handler(hci, 0); 570 val &= ~INTR_HC_PIO; 571 } 572 if (val & INTR_HC_RINGS) { 573 hci->io->irq_handler(hci, val & INTR_HC_RINGS); 574 val &= ~INTR_HC_RINGS; 575 } 576 if (val) 577 dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val); 578 else 579 result = IRQ_HANDLED; 580 581 return result; 582 } 583 584 static int i3c_hci_init(struct i3c_hci *hci) 585 { 586 u32 regval, offset; 587 int ret; 588 589 /* Validate HCI hardware version */ 590 regval = reg_read(HCI_VERSION); 591 hci->version_major = (regval >> 8) & 0xf; 592 hci->version_minor = (regval >> 4) & 0xf; 593 hci->revision = regval & 0xf; 594 dev_notice(&hci->master.dev, "MIPI I3C HCI v%u.%u r%02u\n", 595 hci->version_major, hci->version_minor, hci->revision); 596 /* known versions */ 597 switch (regval & ~0xf) { 598 case 0x100: /* version 1.0 */ 599 case 0x110: /* version 1.1 */ 600 case 0x200: /* version 2.0 */ 601 break; 602 default: 603 dev_err(&hci->master.dev, "unsupported HCI version\n"); 604 return -EPROTONOSUPPORT; 605 } 606 607 hci->caps = reg_read(HC_CAPABILITIES); 608 DBG("caps = %#x", hci->caps); 609 610 regval = reg_read(DAT_SECTION); 611 offset = FIELD_GET(DAT_TABLE_OFFSET, regval); 612 hci->DAT_regs = offset ? hci->base_regs + offset : NULL; 613 hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval); 614 hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval) ? 0 : 8; 615 dev_info(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n", 616 hci->DAT_entries, hci->DAT_entry_size, offset); 617 618 regval = reg_read(DCT_SECTION); 619 offset = FIELD_GET(DCT_TABLE_OFFSET, regval); 620 hci->DCT_regs = offset ? hci->base_regs + offset : NULL; 621 hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval); 622 hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval) ? 0 : 16; 623 dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n", 624 hci->DCT_entries, hci->DCT_entry_size, offset); 625 626 regval = reg_read(RING_HEADERS_SECTION); 627 offset = FIELD_GET(RING_HEADERS_OFFSET, regval); 628 hci->RHS_regs = offset ? hci->base_regs + offset : NULL; 629 dev_info(&hci->master.dev, "Ring Headers at offset %#x\n", offset); 630 631 regval = reg_read(PIO_SECTION); 632 offset = FIELD_GET(PIO_REGS_OFFSET, regval); 633 hci->PIO_regs = offset ? hci->base_regs + offset : NULL; 634 dev_info(&hci->master.dev, "PIO section at offset %#x\n", offset); 635 636 regval = reg_read(EXT_CAPS_SECTION); 637 offset = FIELD_GET(EXT_CAPS_OFFSET, regval); 638 hci->EXTCAPS_regs = offset ? hci->base_regs + offset : NULL; 639 dev_info(&hci->master.dev, "Extended Caps at offset %#x\n", offset); 640 641 ret = i3c_hci_parse_ext_caps(hci); 642 if (ret) 643 return ret; 644 645 /* 646 * Now let's reset the hardware. 647 * SOFT_RST must be clear before we write to it. 648 * Then we must wait until it clears again. 649 */ 650 ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval, 651 !(regval & SOFT_RST), 1, 10000); 652 if (ret) 653 return -ENXIO; 654 reg_write(RESET_CONTROL, SOFT_RST); 655 ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval, 656 !(regval & SOFT_RST), 1, 10000); 657 if (ret) 658 return -ENXIO; 659 660 /* Disable all interrupts and allow all signal updates */ 661 reg_write(INTR_SIGNAL_ENABLE, 0x0); 662 reg_write(INTR_STATUS_ENABLE, 0xffffffff); 663 664 /* Make sure our data ordering fits the host's */ 665 regval = reg_read(HC_CONTROL); 666 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 667 if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) { 668 regval |= HC_CONTROL_DATA_BIG_ENDIAN; 669 reg_write(HC_CONTROL, regval); 670 regval = reg_read(HC_CONTROL); 671 if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) { 672 dev_err(&hci->master.dev, "cannot set BE mode\n"); 673 return -EOPNOTSUPP; 674 } 675 } 676 } else { 677 if (regval & HC_CONTROL_DATA_BIG_ENDIAN) { 678 regval &= ~HC_CONTROL_DATA_BIG_ENDIAN; 679 reg_write(HC_CONTROL, regval); 680 regval = reg_read(HC_CONTROL); 681 if (regval & HC_CONTROL_DATA_BIG_ENDIAN) { 682 dev_err(&hci->master.dev, "cannot clear BE mode\n"); 683 return -EOPNOTSUPP; 684 } 685 } 686 } 687 688 /* Select our command descriptor model */ 689 switch (FIELD_GET(HC_CAP_CMD_SIZE, hci->caps)) { 690 case 0: 691 hci->cmd = &mipi_i3c_hci_cmd_v1; 692 break; 693 case 1: 694 hci->cmd = &mipi_i3c_hci_cmd_v2; 695 break; 696 default: 697 dev_err(&hci->master.dev, "wrong CMD_SIZE capability value\n"); 698 return -EINVAL; 699 } 700 701 /* Try activating DMA operations first */ 702 if (hci->RHS_regs) { 703 reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE); 704 if (reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE) { 705 dev_err(&hci->master.dev, "PIO mode is stuck\n"); 706 ret = -EIO; 707 } else { 708 hci->io = &mipi_i3c_hci_dma; 709 dev_info(&hci->master.dev, "Using DMA\n"); 710 } 711 } 712 713 /* If no DMA, try PIO */ 714 if (!hci->io && hci->PIO_regs) { 715 reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE); 716 if (!(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) { 717 dev_err(&hci->master.dev, "DMA mode is stuck\n"); 718 ret = -EIO; 719 } else { 720 hci->io = &mipi_i3c_hci_pio; 721 dev_info(&hci->master.dev, "Using PIO\n"); 722 } 723 } 724 725 if (!hci->io) { 726 dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n"); 727 if (!ret) 728 ret = -EINVAL; 729 return ret; 730 } 731 732 return 0; 733 } 734 735 static int i3c_hci_probe(struct platform_device *pdev) 736 { 737 struct i3c_hci *hci; 738 int irq, ret; 739 740 hci = devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL); 741 if (!hci) 742 return -ENOMEM; 743 hci->base_regs = devm_platform_ioremap_resource(pdev, 0); 744 if (IS_ERR(hci->base_regs)) 745 return PTR_ERR(hci->base_regs); 746 747 platform_set_drvdata(pdev, hci); 748 /* temporary for dev_printk's, to be replaced in i3c_master_register */ 749 hci->master.dev.init_name = dev_name(&pdev->dev); 750 751 ret = i3c_hci_init(hci); 752 if (ret) 753 return ret; 754 755 irq = platform_get_irq(pdev, 0); 756 ret = devm_request_irq(&pdev->dev, irq, i3c_hci_irq_handler, 757 0, NULL, hci); 758 if (ret) 759 return ret; 760 761 ret = i3c_master_register(&hci->master, &pdev->dev, 762 &i3c_hci_ops, false); 763 if (ret) 764 return ret; 765 766 return 0; 767 } 768 769 static void i3c_hci_remove(struct platform_device *pdev) 770 { 771 struct i3c_hci *hci = platform_get_drvdata(pdev); 772 773 i3c_master_unregister(&hci->master); 774 } 775 776 static const __maybe_unused struct of_device_id i3c_hci_of_match[] = { 777 { .compatible = "mipi-i3c-hci", }, 778 {}, 779 }; 780 MODULE_DEVICE_TABLE(of, i3c_hci_of_match); 781 782 static struct platform_driver i3c_hci_driver = { 783 .probe = i3c_hci_probe, 784 .remove_new = i3c_hci_remove, 785 .driver = { 786 .name = "mipi-i3c-hci", 787 .of_match_table = of_match_ptr(i3c_hci_of_match), 788 }, 789 }; 790 module_platform_driver(i3c_hci_driver); 791 MODULE_ALIAS("platform:mipi-i3c-hci"); 792 793 MODULE_AUTHOR("Nicolas Pitre <npitre@baylibre.com>"); 794 MODULE_DESCRIPTION("MIPI I3C HCI driver"); 795 MODULE_LICENSE("Dual BSD/GPL"); 796