xref: /linux/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt (revision 3d0fe49454652117522f60bfbefb978ba0e5300b) 
1Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
2
3The Generic Memory Interface bus enables memory transfers between internal and
4external memory. Can be used to attach various high speed devices such as
5synchronous/asynchronous NOR, FPGA, UARTS and more.
6
7The actual devices are instantiated from the child nodes of a GMI node.
8
9Required properties:
10 - compatible : Should contain one of the following:
11        For Tegra20 must contain "nvidia,tegra20-gmi".
12        For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
19   addresses in the GMI address space. Should be 2.
20 - #size-cells: The number of cells used to represent the size of an address
21   range in the GMI address space. Should be 1.
22 - ranges: Must be set up to reflect the memory layout with three integer values
23   for each chip-select line in use (only one entry is supported, see below
24   comments):
25   <cs-number> <offset> <physical address of mapping> <size>
26
27Note that the GMI controller does not have any internal chip-select address
28decoding, because of that chip-selects either need to be managed via software
29or by employing external chip-select decoding logic.
30
31If external chip-select logic is used to support multiple devices it is assumed
32that the devices use the same timing and so are probably the same type. It also
33assumes that they can fit in the 256MB address range. In this case only one
34child device is supported which represents the active chip-select line, see
35examples for more insight.
36
37The chip-select number is decoded from the child nodes second address cell of
38'ranges' property, if 'ranges' property is not present or empty chip-select will
39then be decoded from the first cell of the 'reg' property.
40
41Optional child cs node properties:
42
43 - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit.
44 - nvidia,snor-mux-mode: Enable address/data MUX mode.
45 - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
46   If omitted it will be asserted with data.
47 - nvidia,snor-rdy-active-high: RDY signal is active high
48 - nvidia,snor-adv-active-high: ADV signal is active high
49 - nvidia,snor-oe-active-high: WE/OE signal is active high
50 - nvidia,snor-cs-active-high: CS signal is active high
51
52  Note that there is some special handling for the timing values.
53  From Tegra TRM:
54  Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
55
56 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
57   bus. Valid values are 0-15, default is 1
58 - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
59   de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N
60   (in case of MASTER Request). Valid values are 0-15, default is 1
61 - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
62   Valid values are 0-15, default is 1.
63 - nvidia,snor-ce-width: Number of cycles before CE is asserted.
64   Valid values are 0-15, default is 4
65 - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
66   Valid values are 0-15, default is 1
67 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
68   Valid values are 0-255, default is 1
69 - nvidia,snor-wait-width: Number of cycles before READY is asserted.
70   Valid values are 0-255, default is 3
71
72Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
73controllers with a simple-bus node since they are all connected to the same
74chip-select (CS4), in this example external address decoding is provided:
75
76gmi@70009000 {
77	compatible = "nvidia,tegra20-gmi";
78	reg = <0x70009000 0x1000>;
79	#address-cells = <2>;
80	#size-cells = <1>;
81	clocks = <&tegra_car TEGRA20_CLK_NOR>;
82	clock-names = "gmi";
83	resets = <&tegra_car 42>;
84	reset-names = "gmi";
85	ranges = <4 0 0xd0000000 0xfffffff>;
86
87	bus@4,0 {
88		compatible = "simple-bus";
89		#address-cells = <1>;
90		#size-cells = <1>;
91		ranges = <0 4 0 0x40100>;
92
93		nvidia,snor-mux-mode;
94		nvidia,snor-adv-active-high;
95
96		can@0 {
97			reg = <0 0x100>;
98			...
99		};
100
101		can@40000 {
102			reg = <0x40000 0x100>;
103			...
104		};
105	};
106};
107
108Example with one SJA1000 CAN controller connected to the GMI bus
109on CS4:
110
111gmi@70009000 {
112	compatible = "nvidia,tegra20-gmi";
113	reg = <0x70009000 0x1000>;
114	#address-cells = <2>;
115	#size-cells = <1>;
116	clocks = <&tegra_car TEGRA20_CLK_NOR>;
117	clock-names = "gmi";
118	resets = <&tegra_car 42>;
119	reset-names = "gmi";
120	ranges = <4 0 0xd0000000 0xfffffff>;
121
122	can@4,0 {
123		reg = <4 0 0x100>;
124		nvidia,snor-mux-mode;
125		nvidia,snor-adv-active-high;
126		...
127	};
128};
129