1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/iopoll.h> 9 10 #include "dsi_phy.h" 11 #include "dsi.xml.h" 12 #include "dsi_phy_7nm.xml.h" 13 14 /* 15 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram 16 * 17 * dsi0_pll_out_div_clk dsi0_pll_bit_clk 18 * | | 19 * | | 20 * +---------+ | +----------+ | +----+ 21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk 22 * +---------+ | +----------+ | +----+ 23 * | | 24 * | | dsi0_pll_by_2_bit_clk 25 * | | | 26 * | | +----+ | |\ dsi0_pclk_mux 27 * | |--| /2 |--o--| \ | 28 * | | +----+ | \ | +---------+ 29 * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk 30 * |------------------------------| / +---------+ 31 * | +-----+ | / 32 * -----------| /4? |--o----------|/ 33 * +-----+ | | 34 * | |dsiclk_sel 35 * | 36 * dsi0_pll_post_out_div_clk 37 */ 38 39 #define VCO_REF_CLK_RATE 19200000 40 #define FRAC_BITS 18 41 42 /* Hardware is pre V4.1 */ 43 #define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) 44 /* Hardware is V4.1 */ 45 #define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) 46 /* Hardware is V4.2 */ 47 #define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) 48 /* Hardware is V4.3 */ 49 #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) 50 /* Hardware is V5.2 */ 51 #define DSI_PHY_7NM_QUIRK_V5_2 BIT(4) 52 53 struct dsi_pll_config { 54 bool enable_ssc; 55 bool ssc_center; 56 u32 ssc_freq; 57 u32 ssc_offset; 58 u32 ssc_adj_per; 59 60 /* out */ 61 u32 decimal_div_start; 62 u32 frac_div_start; 63 u32 pll_clock_inverters; 64 u32 ssc_stepsize; 65 u32 ssc_div_per; 66 }; 67 68 struct pll_7nm_cached_state { 69 unsigned long vco_rate; 70 u8 bit_clk_div; 71 u8 pix_clk_div; 72 u8 pll_out_div; 73 u8 pll_mux; 74 }; 75 76 struct dsi_pll_7nm { 77 struct clk_hw clk_hw; 78 79 struct msm_dsi_phy *phy; 80 81 u64 vco_current_rate; 82 83 /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ 84 spinlock_t postdiv_lock; 85 86 struct pll_7nm_cached_state cached_state; 87 88 struct dsi_pll_7nm *slave; 89 }; 90 91 #define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw) 92 93 /* 94 * Global list of private DSI PLL struct pointers. We need this for bonded DSI 95 * mode, where the master PLL's clk_ops needs access the slave's private data 96 */ 97 static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; 98 99 static void dsi_pll_setup_config(struct dsi_pll_config *config) 100 { 101 config->ssc_freq = 31500; 102 config->ssc_offset = 4800; 103 config->ssc_adj_per = 2; 104 105 /* TODO: ssc enable */ 106 config->enable_ssc = false; 107 config->ssc_center = 0; 108 } 109 110 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) 111 { 112 u64 fref = VCO_REF_CLK_RATE; 113 u64 pll_freq; 114 u64 divider; 115 u64 dec, dec_multiple; 116 u32 frac; 117 u64 multiplier; 118 119 pll_freq = pll->vco_current_rate; 120 121 divider = fref * 2; 122 123 multiplier = 1 << FRAC_BITS; 124 dec_multiple = div_u64(pll_freq * multiplier, divider); 125 dec = div_u64_rem(dec_multiple, multiplier, &frac); 126 127 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) 128 config->pll_clock_inverters = 0x28; 129 else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { 130 if (pll_freq <= 1300000000ULL) 131 config->pll_clock_inverters = 0xa0; 132 else if (pll_freq <= 2500000000ULL) 133 config->pll_clock_inverters = 0x20; 134 else if (pll_freq <= 4000000000ULL) 135 config->pll_clock_inverters = 0x00; 136 else 137 config->pll_clock_inverters = 0x40; 138 } else { 139 if (pll_freq <= 1000000000ULL) 140 config->pll_clock_inverters = 0xa0; 141 else if (pll_freq <= 2500000000ULL) 142 config->pll_clock_inverters = 0x20; 143 else if (pll_freq <= 3020000000ULL) 144 config->pll_clock_inverters = 0x00; 145 else 146 config->pll_clock_inverters = 0x40; 147 } 148 149 config->decimal_div_start = dec; 150 config->frac_div_start = frac; 151 } 152 153 #define SSC_CENTER BIT(0) 154 #define SSC_EN BIT(1) 155 156 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) 157 { 158 u32 ssc_per; 159 u32 ssc_mod; 160 u64 ssc_step_size; 161 u64 frac; 162 163 if (!config->enable_ssc) { 164 DBG("SSC not enabled\n"); 165 return; 166 } 167 168 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; 169 ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1); 170 ssc_per -= ssc_mod; 171 172 frac = config->frac_div_start; 173 ssc_step_size = config->decimal_div_start; 174 ssc_step_size *= (1 << FRAC_BITS); 175 ssc_step_size += frac; 176 ssc_step_size *= config->ssc_offset; 177 ssc_step_size *= (config->ssc_adj_per + 1); 178 ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1)); 179 ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000); 180 181 config->ssc_div_per = ssc_per; 182 config->ssc_stepsize = ssc_step_size; 183 184 pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n", 185 config->decimal_div_start, frac, FRAC_BITS); 186 pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n", 187 ssc_per, (u32)ssc_step_size, config->ssc_adj_per); 188 } 189 190 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) 191 { 192 void __iomem *base = pll->phy->pll_base; 193 194 if (config->enable_ssc) { 195 pr_debug("SSC is enabled\n"); 196 197 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, 198 config->ssc_stepsize & 0xff); 199 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, 200 config->ssc_stepsize >> 8); 201 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, 202 config->ssc_div_per & 0xff); 203 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, 204 config->ssc_div_per >> 8); 205 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, 206 config->ssc_adj_per & 0xff); 207 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, 208 config->ssc_adj_per >> 8); 209 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, 210 SSC_EN | (config->ssc_center ? SSC_CENTER : 0)); 211 } 212 } 213 214 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) 215 { 216 void __iomem *base = pll->phy->pll_base; 217 u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; 218 219 if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) 220 if (pll->vco_current_rate >= 3100000000ULL) 221 analog_controls_five_1 = 0x03; 222 223 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { 224 if (pll->vco_current_rate < 1520000000ULL) 225 vco_config_1 = 0x08; 226 else if (pll->vco_current_rate < 2990000000ULL) 227 vco_config_1 = 0x01; 228 } 229 230 if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || 231 (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { 232 if (pll->vco_current_rate < 1520000000ULL) 233 vco_config_1 = 0x08; 234 else if (pll->vco_current_rate >= 2990000000ULL) 235 vco_config_1 = 0x01; 236 } 237 238 if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { 239 if (pll->vco_current_rate < 1557000000ULL) 240 vco_config_1 = 0x08; 241 else 242 vco_config_1 = 0x01; 243 } 244 245 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, 246 analog_controls_five_1); 247 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); 248 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01); 249 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); 250 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); 251 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00); 252 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); 253 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); 254 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); 255 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); 256 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00); 257 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00); 258 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); 259 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a); 260 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0); 261 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84); 262 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82); 263 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); 264 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); 265 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29); 266 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); 267 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); 268 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 269 !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22); 270 271 if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { 272 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); 273 if (pll->slave) 274 dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); 275 } 276 } 277 278 static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) 279 { 280 void __iomem *base = pll->phy->pll_base; 281 282 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); 283 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, 284 config->decimal_div_start); 285 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, 286 config->frac_div_start & 0xff); 287 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, 288 (config->frac_div_start & 0xff00) >> 8); 289 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, 290 (config->frac_div_start & 0x30000) >> 16); 291 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); 292 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); 293 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 294 pll->phy->cphy_mode ? 0x00 : 0x10); 295 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, 296 config->pll_clock_inverters); 297 } 298 299 static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, 300 unsigned long parent_rate) 301 { 302 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 303 struct dsi_pll_config config; 304 305 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate, 306 parent_rate); 307 308 pll_7nm->vco_current_rate = rate; 309 310 dsi_pll_setup_config(&config); 311 312 dsi_pll_calc_dec_frac(pll_7nm, &config); 313 314 dsi_pll_calc_ssc(pll_7nm, &config); 315 316 dsi_pll_commit(pll_7nm, &config); 317 318 dsi_pll_config_hzindep_reg(pll_7nm); 319 320 dsi_pll_ssc_commit(pll_7nm, &config); 321 322 /* flush, ensure all register writes are done*/ 323 wmb(); 324 325 return 0; 326 } 327 328 static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) 329 { 330 int rc; 331 u32 status = 0; 332 u32 const delay_us = 100; 333 u32 const timeout_us = 5000; 334 335 rc = readl_poll_timeout_atomic(pll->phy->pll_base + 336 REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE, 337 status, 338 ((status & BIT(0)) > 0), 339 delay_us, 340 timeout_us); 341 if (rc) 342 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", 343 pll->phy->id, status); 344 345 return rc; 346 } 347 348 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) 349 { 350 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 351 352 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); 353 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); 354 ndelay(250); 355 } 356 357 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) 358 { 359 u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); 360 361 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); 362 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); 363 ndelay(250); 364 } 365 366 static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) 367 { 368 u32 data; 369 370 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 371 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); 372 } 373 374 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) 375 { 376 u32 data; 377 378 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); 379 380 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 381 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, 382 data | BIT(5) | BIT(4)); 383 } 384 385 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) 386 { 387 /* 388 * Reset the PHY digital domain. This would be needed when 389 * coming out of a CX or analog rail power collapse while 390 * ensuring that the pads maintain LP00 or LP11 state 391 */ 392 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); 393 wmb(); /* Ensure that the reset is deasserted */ 394 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); 395 wmb(); /* Ensure that the reset is deasserted */ 396 } 397 398 static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) 399 { 400 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 401 int rc; 402 403 dsi_pll_enable_pll_bias(pll_7nm); 404 if (pll_7nm->slave) 405 dsi_pll_enable_pll_bias(pll_7nm->slave); 406 407 /* Start PLL */ 408 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); 409 410 /* 411 * ensure all PLL configurations are written prior to checking 412 * for PLL lock. 413 */ 414 wmb(); 415 416 /* Check for PLL lock */ 417 rc = dsi_pll_7nm_lock_status(pll_7nm); 418 if (rc) { 419 pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id); 420 goto error; 421 } 422 423 pll_7nm->phy->pll_on = true; 424 425 /* 426 * assert power on reset for PHY digital in case the PLL is 427 * enabled after CX of analog domain power collapse. This needs 428 * to be done before enabling the global clk. 429 */ 430 dsi_pll_phy_dig_reset(pll_7nm); 431 if (pll_7nm->slave) 432 dsi_pll_phy_dig_reset(pll_7nm->slave); 433 434 dsi_pll_enable_global_clk(pll_7nm); 435 if (pll_7nm->slave) 436 dsi_pll_enable_global_clk(pll_7nm->slave); 437 438 error: 439 return rc; 440 } 441 442 static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) 443 { 444 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); 445 dsi_pll_disable_pll_bias(pll); 446 } 447 448 static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) 449 { 450 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 451 452 /* 453 * To avoid any stray glitches while abruptly powering down the PLL 454 * make sure to gate the clock using the clock enable bit before 455 * powering down the PLL 456 */ 457 dsi_pll_disable_global_clk(pll_7nm); 458 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); 459 dsi_pll_disable_sub(pll_7nm); 460 if (pll_7nm->slave) { 461 dsi_pll_disable_global_clk(pll_7nm->slave); 462 dsi_pll_disable_sub(pll_7nm->slave); 463 } 464 /* flush, ensure all register writes are done */ 465 wmb(); 466 pll_7nm->phy->pll_on = false; 467 } 468 469 static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, 470 unsigned long parent_rate) 471 { 472 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 473 void __iomem *base = pll_7nm->phy->pll_base; 474 u64 ref_clk = VCO_REF_CLK_RATE; 475 u64 vco_rate = 0x0; 476 u64 multiplier; 477 u32 frac; 478 u32 dec; 479 u64 pll_freq, tmp64; 480 481 dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); 482 dec &= 0xff; 483 484 frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); 485 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & 486 0xff) << 8); 487 frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & 488 0x3) << 16); 489 490 /* 491 * TODO: 492 * 1. Assumes prescaler is disabled 493 */ 494 multiplier = 1 << FRAC_BITS; 495 pll_freq = dec * (ref_clk * 2); 496 tmp64 = (ref_clk * 2 * frac); 497 pll_freq += div_u64(tmp64, multiplier); 498 499 vco_rate = pll_freq; 500 pll_7nm->vco_current_rate = vco_rate; 501 502 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", 503 pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac); 504 505 return (unsigned long)vco_rate; 506 } 507 508 static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw, 509 unsigned long rate, unsigned long *parent_rate) 510 { 511 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); 512 513 if (rate < pll_7nm->phy->cfg->min_pll_rate) 514 return pll_7nm->phy->cfg->min_pll_rate; 515 else if (rate > pll_7nm->phy->cfg->max_pll_rate) 516 return pll_7nm->phy->cfg->max_pll_rate; 517 else 518 return rate; 519 } 520 521 static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { 522 .round_rate = dsi_pll_7nm_clk_round_rate, 523 .set_rate = dsi_pll_7nm_vco_set_rate, 524 .recalc_rate = dsi_pll_7nm_vco_recalc_rate, 525 .prepare = dsi_pll_7nm_vco_prepare, 526 .unprepare = dsi_pll_7nm_vco_unprepare, 527 }; 528 529 /* 530 * PLL Callbacks 531 */ 532 533 static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy) 534 { 535 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); 536 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; 537 void __iomem *phy_base = pll_7nm->phy->base; 538 u32 cmn_clk_cfg0, cmn_clk_cfg1; 539 540 cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base + 541 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); 542 cached->pll_out_div &= 0x3; 543 544 cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); 545 cached->bit_clk_div = cmn_clk_cfg0 & 0xf; 546 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; 547 548 cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 549 cached->pll_mux = cmn_clk_cfg1 & 0x3; 550 551 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", 552 pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div, 553 cached->pix_clk_div, cached->pll_mux); 554 } 555 556 static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) 557 { 558 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); 559 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; 560 void __iomem *phy_base = pll_7nm->phy->base; 561 u32 val; 562 int ret; 563 564 val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); 565 val &= ~0x3; 566 val |= cached->pll_out_div; 567 dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); 568 569 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, 570 cached->bit_clk_div | (cached->pix_clk_div << 4)); 571 572 val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 573 val &= ~0x3; 574 val |= cached->pll_mux; 575 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); 576 577 ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, 578 pll_7nm->vco_current_rate, 579 VCO_REF_CLK_RATE); 580 if (ret) { 581 DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev, 582 "restore vco rate failed. ret=%d\n", ret); 583 return ret; 584 } 585 586 DBG("DSI PLL%d", pll_7nm->phy->id); 587 588 return 0; 589 } 590 591 static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) 592 { 593 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); 594 void __iomem *base = phy->base; 595 u32 data = 0x0; /* internal PLL */ 596 597 DBG("DSI PLL%d", pll_7nm->phy->id); 598 599 switch (phy->usecase) { 600 case MSM_DSI_PHY_STANDALONE: 601 break; 602 case MSM_DSI_PHY_MASTER: 603 pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; 604 break; 605 case MSM_DSI_PHY_SLAVE: 606 data = 0x1; /* external PLL */ 607 break; 608 default: 609 return -EINVAL; 610 } 611 612 /* set PLL src */ 613 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); 614 615 return 0; 616 } 617 618 /* 619 * The post dividers and mux clocks are created using the standard divider and 620 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux 621 * state to follow the master PLL's divider/mux state. Therefore, we don't 622 * require special clock ops that also configure the slave PLL registers 623 */ 624 static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks) 625 { 626 char clk_name[32]; 627 struct clk_init_data vco_init = { 628 .parent_data = &(const struct clk_parent_data) { 629 .fw_name = "ref", 630 }, 631 .num_parents = 1, 632 .name = clk_name, 633 .flags = CLK_IGNORE_UNUSED, 634 .ops = &clk_ops_dsi_pll_7nm_vco, 635 }; 636 struct device *dev = &pll_7nm->phy->pdev->dev; 637 struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit; 638 struct clk_hw *pll_post_out_div, *phy_pll_out_dsi_parent; 639 int ret; 640 641 DBG("DSI%d", pll_7nm->phy->id); 642 643 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_7nm->phy->id); 644 pll_7nm->clk_hw.init = &vco_init; 645 646 ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw); 647 if (ret) 648 return ret; 649 650 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_7nm->phy->id); 651 652 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, 653 &pll_7nm->clk_hw, CLK_SET_RATE_PARENT, 654 pll_7nm->phy->pll_base + 655 REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, 656 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); 657 if (IS_ERR(pll_out_div)) { 658 ret = PTR_ERR(pll_out_div); 659 goto fail; 660 } 661 662 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_7nm->phy->id); 663 664 /* BIT CLK: DIV_CTRL_3_0 */ 665 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name, 666 pll_out_div, CLK_SET_RATE_PARENT, 667 pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, 668 0, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock); 669 if (IS_ERR(pll_bit)) { 670 ret = PTR_ERR(pll_bit); 671 goto fail; 672 } 673 674 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id); 675 676 /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ 677 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, 678 pll_bit, CLK_SET_RATE_PARENT, 1, 679 pll_7nm->phy->cphy_mode ? 7 : 8); 680 if (IS_ERR(hw)) { 681 ret = PTR_ERR(hw); 682 goto fail; 683 } 684 685 provided_clocks[DSI_BYTE_PLL_CLK] = hw; 686 687 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); 688 689 pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev, 690 clk_name, pll_bit, 0, 1, 2); 691 if (IS_ERR(pll_by_2_bit)) { 692 ret = PTR_ERR(pll_by_2_bit); 693 goto fail; 694 } 695 696 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); 697 698 if (pll_7nm->phy->cphy_mode) 699 pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw( 700 dev, clk_name, pll_out_div, 0, 2, 7); 701 else 702 pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw( 703 dev, clk_name, pll_out_div, 0, 1, 4); 704 if (IS_ERR(pll_post_out_div)) { 705 ret = PTR_ERR(pll_post_out_div); 706 goto fail; 707 } 708 709 /* in CPHY mode, pclk_mux will always have post_out_div as parent 710 * don't register a pclk_mux clock and just use post_out_div instead 711 */ 712 if (pll_7nm->phy->cphy_mode) { 713 u32 data; 714 715 data = dsi_phy_read(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); 716 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | 3); 717 718 phy_pll_out_dsi_parent = pll_post_out_div; 719 } else { 720 snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_7nm->phy->id); 721 722 hw = devm_clk_hw_register_mux_parent_hws(dev, clk_name, 723 ((const struct clk_hw *[]){ 724 pll_bit, 725 pll_by_2_bit, 726 }), 2, 0, pll_7nm->phy->base + 727 REG_DSI_7nm_PHY_CMN_CLK_CFG1, 728 0, 1, 0, NULL); 729 if (IS_ERR(hw)) { 730 ret = PTR_ERR(hw); 731 goto fail; 732 } 733 734 phy_pll_out_dsi_parent = hw; 735 } 736 737 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id); 738 739 /* PIX CLK DIV : DIV_CTRL_7_4*/ 740 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, 741 phy_pll_out_dsi_parent, 0, 742 pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, 743 4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock); 744 if (IS_ERR(hw)) { 745 ret = PTR_ERR(hw); 746 goto fail; 747 } 748 749 provided_clocks[DSI_PIXEL_PLL_CLK] = hw; 750 751 return 0; 752 753 fail: 754 755 return ret; 756 } 757 758 static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) 759 { 760 struct platform_device *pdev = phy->pdev; 761 struct dsi_pll_7nm *pll_7nm; 762 int ret; 763 764 pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL); 765 if (!pll_7nm) 766 return -ENOMEM; 767 768 DBG("DSI PLL%d", phy->id); 769 770 pll_7nm_list[phy->id] = pll_7nm; 771 772 spin_lock_init(&pll_7nm->postdiv_lock); 773 774 pll_7nm->phy = phy; 775 776 ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); 777 if (ret) { 778 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); 779 return ret; 780 } 781 782 phy->vco_hw = &pll_7nm->clk_hw; 783 784 /* TODO: Remove this when we have proper display handover support */ 785 msm_dsi_phy_pll_save_state(phy); 786 787 return 0; 788 } 789 790 static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy) 791 { 792 void __iomem *base = phy->base; 793 u32 data = 0; 794 795 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); 796 mb(); /* make sure read happened */ 797 798 return (data & BIT(0)); 799 } 800 801 static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable) 802 { 803 void __iomem *lane_base = phy->lane_base; 804 int phy_lane_0 = 0; /* TODO: Support all lane swap configs */ 805 806 /* 807 * LPRX and CDRX need to enabled only for physical data lane 808 * corresponding to the logical data lane 0 809 */ 810 if (enable) 811 dsi_phy_write(lane_base + 812 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3); 813 else 814 dsi_phy_write(lane_base + 815 REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0); 816 } 817 818 static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) 819 { 820 int i; 821 const u8 tx_dctrl_0[] = { 0x00, 0x00, 0x00, 0x04, 0x01 }; 822 const u8 tx_dctrl_1[] = { 0x40, 0x40, 0x40, 0x46, 0x41 }; 823 const u8 *tx_dctrl = tx_dctrl_0; 824 void __iomem *lane_base = phy->lane_base; 825 826 if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) 827 tx_dctrl = tx_dctrl_1; 828 829 /* Strength ctrl settings */ 830 for (i = 0; i < 5; i++) { 831 /* 832 * Disable LPRX and CDRX for all lanes. And later on, it will 833 * be only enabled for the physical data lane corresponding 834 * to the logical data lane 0 835 */ 836 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0); 837 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0); 838 } 839 840 dsi_phy_hw_v4_0_config_lpcdrx(phy, true); 841 842 /* other settings */ 843 for (i = 0; i < 5; i++) { 844 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0); 845 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0); 846 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa); 847 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]); 848 } 849 } 850 851 static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 852 struct msm_dsi_phy_clk_request *clk_req) 853 { 854 int ret; 855 u32 status; 856 u32 const delay_us = 5; 857 u32 const timeout_us = 1000; 858 struct msm_dsi_dphy_timing *timing = &phy->timing; 859 void __iomem *base = phy->base; 860 bool less_than_1500_mhz; 861 u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0; 862 u32 glbl_pemph_ctrl_0; 863 u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0; 864 u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl; 865 u32 data; 866 867 DBG(""); 868 869 if (phy->cphy_mode) 870 ret = msm_dsi_cphy_timing_calc_v4(timing, clk_req); 871 else 872 ret = msm_dsi_dphy_timing_calc_v4(timing, clk_req); 873 if (ret) { 874 DRM_DEV_ERROR(&phy->pdev->dev, 875 "%s: PHY timing calculation failed\n", __func__); 876 return -EINVAL; 877 } 878 879 if (dsi_phy_hw_v4_0_is_pll_on(phy)) 880 pr_warn("PLL turned on before configuring PHY\n"); 881 882 /* Request for REFGEN READY */ 883 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || 884 (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { 885 dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); 886 udelay(500); 887 } 888 889 /* wait for REFGEN READY */ 890 ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS, 891 status, (status & BIT(0)), 892 delay_us, timeout_us); 893 if (ret) { 894 pr_err("Ref gen not ready. Aborting\n"); 895 return -EINVAL; 896 } 897 898 /* TODO: CPHY enable path (this is for DPHY only) */ 899 900 /* Alter PHY configurations if data rate less than 1.5GHZ*/ 901 less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); 902 903 glbl_str_swi_cal_sel_ctrl = 0x00; 904 if (phy->cphy_mode) { 905 vreg_ctrl_0 = 0x51; 906 vreg_ctrl_1 = 0x55; 907 glbl_hstx_str_ctrl_0 = 0x00; 908 glbl_pemph_ctrl_0 = 0x11; 909 lane_ctrl0 = 0x17; 910 } else { 911 vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; 912 vreg_ctrl_1 = 0x5c; 913 glbl_hstx_str_ctrl_0 = 0x88; 914 glbl_pemph_ctrl_0 = 0x00; 915 lane_ctrl0 = 0x1f; 916 } 917 918 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { 919 if (phy->cphy_mode) { 920 vreg_ctrl_0 = 0x45; 921 vreg_ctrl_1 = 0x45; 922 glbl_rescode_top_ctrl = 0x00; 923 glbl_rescode_bot_ctrl = 0x00; 924 } else { 925 vreg_ctrl_0 = 0x44; 926 vreg_ctrl_1 = 0x19; 927 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03; 928 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c; 929 } 930 } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { 931 if (phy->cphy_mode) { 932 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; 933 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; 934 } else { 935 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; 936 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; 937 } 938 } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { 939 if (phy->cphy_mode) { 940 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; 941 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; 942 } else { 943 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; 944 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; 945 } 946 } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { 947 if (phy->cphy_mode) { 948 glbl_hstx_str_ctrl_0 = 0x88; 949 glbl_rescode_top_ctrl = 0x00; 950 glbl_rescode_bot_ctrl = 0x3c; 951 } else { 952 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; 953 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; 954 } 955 } else { 956 if (phy->cphy_mode) { 957 glbl_str_swi_cal_sel_ctrl = 0x03; 958 glbl_hstx_str_ctrl_0 = 0x66; 959 } else { 960 vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; 961 glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; 962 glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; 963 } 964 glbl_rescode_top_ctrl = 0x03; 965 glbl_rescode_bot_ctrl = 0x3c; 966 } 967 968 /* de-assert digital and pll power down */ 969 data = BIT(6) | BIT(5); 970 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data); 971 972 /* Assert PLL core reset */ 973 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00); 974 975 /* turn off resync FIFO */ 976 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00); 977 978 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ 979 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || 980 (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20) 981 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04); 982 983 /* Configure PHY lane swap (TODO: we need to calculate this) */ 984 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21); 985 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84); 986 987 if (phy->cphy_mode) 988 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL, BIT(6)); 989 990 /* Enable LDO */ 991 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0); 992 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, vreg_ctrl_1); 993 994 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00); 995 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL, 996 glbl_str_swi_cal_sel_ctrl); 997 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0, 998 glbl_hstx_str_ctrl_0); 999 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0, 1000 glbl_pemph_ctrl_0); 1001 if (phy->cphy_mode) 1002 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1, 0x01); 1003 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL, 1004 glbl_rescode_top_ctrl); 1005 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL, 1006 glbl_rescode_bot_ctrl); 1007 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55); 1008 1009 /* Remove power down from all blocks */ 1010 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f); 1011 1012 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, lane_ctrl0); 1013 1014 /* Select full-rate mode */ 1015 if (!phy->cphy_mode) 1016 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40); 1017 1018 ret = dsi_7nm_set_usecase(phy); 1019 if (ret) { 1020 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", 1021 __func__, ret); 1022 return ret; 1023 } 1024 1025 /* DSI PHY timings */ 1026 if (phy->cphy_mode) { 1027 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00); 1028 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit); 1029 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, 1030 timing->shared_timings.clk_pre); 1031 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->clk_prepare); 1032 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, 1033 timing->shared_timings.clk_post); 1034 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst); 1035 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02); 1036 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04); 1037 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00); 1038 } else { 1039 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00); 1040 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero); 1041 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare); 1042 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail); 1043 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit); 1044 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero); 1045 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare); 1046 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail); 1047 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst); 1048 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02); 1049 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04); 1050 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00); 1051 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12, 1052 timing->shared_timings.clk_pre); 1053 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13, 1054 timing->shared_timings.clk_post); 1055 } 1056 1057 /* DSI lane settings */ 1058 dsi_phy_hw_v4_0_lane_settings(phy); 1059 1060 DBG("DSI%d PHY enabled", phy->id); 1061 1062 return 0; 1063 } 1064 1065 static bool dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable) 1066 { 1067 void __iomem *base = phy->base; 1068 u32 data; 1069 1070 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1); 1071 if (enable) 1072 data |= BIT(5) | BIT(6); 1073 else 1074 data &= ~(BIT(5) | BIT(6)); 1075 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1, data); 1076 1077 return enable; 1078 } 1079 1080 static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) 1081 { 1082 void __iomem *base = phy->base; 1083 u32 data; 1084 1085 DBG(""); 1086 1087 if (dsi_phy_hw_v4_0_is_pll_on(phy)) 1088 pr_warn("Turning OFF PHY while PLL is on\n"); 1089 1090 dsi_phy_hw_v4_0_config_lpcdrx(phy, false); 1091 1092 /* Turn off REFGEN Vote */ 1093 if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || 1094 (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { 1095 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); 1096 wmb(); 1097 /* Delay to ensure HW removes vote before PHY shut down */ 1098 udelay(2); 1099 } 1100 1101 data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); 1102 1103 /* disable all lanes */ 1104 data &= ~0x1F; 1105 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data); 1106 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0); 1107 1108 /* Turn off all PHY blocks */ 1109 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00); 1110 /* make sure phy is turned off */ 1111 wmb(); 1112 1113 DBG("DSI%d PHY disabled", phy->id); 1114 } 1115 1116 static const struct regulator_bulk_data dsi_phy_7nm_36mA_regulators[] = { 1117 { .supply = "vdds", .init_load_uA = 36000 }, 1118 }; 1119 1120 static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { 1121 { .supply = "vdds", .init_load_uA = 37550 }, 1122 }; 1123 1124 static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { 1125 { .supply = "vdds", .init_load_uA = 97800 }, 1126 }; 1127 1128 static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = { 1129 { .supply = "vdds", .init_load_uA = 98400 }, 1130 }; 1131 1132 const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { 1133 .has_phy_lane = true, 1134 .regulator_data = dsi_phy_7nm_36mA_regulators, 1135 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators), 1136 .ops = { 1137 .enable = dsi_7nm_phy_enable, 1138 .disable = dsi_7nm_phy_disable, 1139 .pll_init = dsi_pll_7nm_init, 1140 .save_pll_state = dsi_7nm_pll_save_state, 1141 .restore_pll_state = dsi_7nm_pll_restore_state, 1142 .set_continuous_clock = dsi_7nm_set_continuous_clock, 1143 }, 1144 .min_pll_rate = 600000000UL, 1145 #ifdef CONFIG_64BIT 1146 .max_pll_rate = 5000000000UL, 1147 #else 1148 .max_pll_rate = ULONG_MAX, 1149 #endif 1150 .io_start = { 0xae94400, 0xae96400 }, 1151 .num_dsi_phy = 2, 1152 .quirks = DSI_PHY_7NM_QUIRK_V4_1, 1153 }; 1154 1155 const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs = { 1156 .has_phy_lane = true, 1157 .ops = { 1158 .enable = dsi_7nm_phy_enable, 1159 .disable = dsi_7nm_phy_disable, 1160 .pll_init = dsi_pll_7nm_init, 1161 .save_pll_state = dsi_7nm_pll_save_state, 1162 .restore_pll_state = dsi_7nm_pll_restore_state, 1163 }, 1164 .min_pll_rate = 600000000UL, 1165 #ifdef CONFIG_64BIT 1166 .max_pll_rate = 5000000000ULL, 1167 #else 1168 .max_pll_rate = ULONG_MAX, 1169 #endif 1170 .io_start = { 0x5e94400 }, 1171 .num_dsi_phy = 1, 1172 .quirks = DSI_PHY_7NM_QUIRK_V4_1, 1173 }; 1174 1175 const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { 1176 .has_phy_lane = true, 1177 .regulator_data = dsi_phy_7nm_36mA_regulators, 1178 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators), 1179 .ops = { 1180 .enable = dsi_7nm_phy_enable, 1181 .disable = dsi_7nm_phy_disable, 1182 .pll_init = dsi_pll_7nm_init, 1183 .save_pll_state = dsi_7nm_pll_save_state, 1184 .restore_pll_state = dsi_7nm_pll_restore_state, 1185 .set_continuous_clock = dsi_7nm_set_continuous_clock, 1186 }, 1187 .min_pll_rate = 1000000000UL, 1188 .max_pll_rate = 3500000000UL, 1189 .io_start = { 0xae94400, 0xae96400 }, 1190 .num_dsi_phy = 2, 1191 .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, 1192 }; 1193 1194 const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { 1195 .has_phy_lane = true, 1196 .regulator_data = dsi_phy_7nm_37750uA_regulators, 1197 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), 1198 .ops = { 1199 .enable = dsi_7nm_phy_enable, 1200 .disable = dsi_7nm_phy_disable, 1201 .pll_init = dsi_pll_7nm_init, 1202 .save_pll_state = dsi_7nm_pll_save_state, 1203 .restore_pll_state = dsi_7nm_pll_restore_state, 1204 }, 1205 .min_pll_rate = 600000000UL, 1206 #ifdef CONFIG_64BIT 1207 .max_pll_rate = 5000000000ULL, 1208 #else 1209 .max_pll_rate = ULONG_MAX, 1210 #endif 1211 .io_start = { 0xae94400 }, 1212 .num_dsi_phy = 1, 1213 .quirks = DSI_PHY_7NM_QUIRK_V4_1, 1214 }; 1215 1216 const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { 1217 .has_phy_lane = true, 1218 .regulator_data = dsi_phy_7nm_37750uA_regulators, 1219 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), 1220 .ops = { 1221 .enable = dsi_7nm_phy_enable, 1222 .disable = dsi_7nm_phy_disable, 1223 .pll_init = dsi_pll_7nm_init, 1224 .save_pll_state = dsi_7nm_pll_save_state, 1225 .restore_pll_state = dsi_7nm_pll_restore_state, 1226 .set_continuous_clock = dsi_7nm_set_continuous_clock, 1227 }, 1228 .min_pll_rate = 600000000UL, 1229 #ifdef CONFIG_64BIT 1230 .max_pll_rate = 5000000000UL, 1231 #else 1232 .max_pll_rate = ULONG_MAX, 1233 #endif 1234 .io_start = { 0xae94400, 0xae96400 }, 1235 .num_dsi_phy = 2, 1236 .quirks = DSI_PHY_7NM_QUIRK_V4_2, 1237 }; 1238 1239 const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { 1240 .has_phy_lane = true, 1241 .regulator_data = dsi_phy_7nm_97800uA_regulators, 1242 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), 1243 .ops = { 1244 .enable = dsi_7nm_phy_enable, 1245 .disable = dsi_7nm_phy_disable, 1246 .pll_init = dsi_pll_7nm_init, 1247 .save_pll_state = dsi_7nm_pll_save_state, 1248 .restore_pll_state = dsi_7nm_pll_restore_state, 1249 .set_continuous_clock = dsi_7nm_set_continuous_clock, 1250 }, 1251 .min_pll_rate = 600000000UL, 1252 #ifdef CONFIG_64BIT 1253 .max_pll_rate = 5000000000UL, 1254 #else 1255 .max_pll_rate = ULONG_MAX, 1256 #endif 1257 .io_start = { 0xae94400, 0xae96400 }, 1258 .num_dsi_phy = 2, 1259 .quirks = DSI_PHY_7NM_QUIRK_V4_3, 1260 }; 1261 1262 const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = { 1263 .has_phy_lane = true, 1264 .regulator_data = dsi_phy_7nm_98400uA_regulators, 1265 .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators), 1266 .ops = { 1267 .enable = dsi_7nm_phy_enable, 1268 .disable = dsi_7nm_phy_disable, 1269 .pll_init = dsi_pll_7nm_init, 1270 .save_pll_state = dsi_7nm_pll_save_state, 1271 .restore_pll_state = dsi_7nm_pll_restore_state, 1272 .set_continuous_clock = dsi_7nm_set_continuous_clock, 1273 }, 1274 .min_pll_rate = 600000000UL, 1275 #ifdef CONFIG_64BIT 1276 .max_pll_rate = 5000000000UL, 1277 #else 1278 .max_pll_rate = ULONG_MAX, 1279 #endif 1280 .io_start = { 0xae95000, 0xae97000 }, 1281 .num_dsi_phy = 2, 1282 .quirks = DSI_PHY_7NM_QUIRK_V5_2, 1283 }; 1284